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Merging r199832: ------------------------------------------------------------------------ r199832 | rafael.espindola | 2014-01-22 15:20:52 -0500 (Wed, 22 Jan 2014) | 11 lines Fix pr18515. My understanding (from reading just the llvm code) is that * most ppc cpus have a "sync n" instruction and an msync alias that is * "sync 0". * "book e" cpus instead have a msync instruction and not the more general "sync n" This patch reflects that in the .td files, allowing a single codepath for asm ond obj streamer and incidentelly fixes a crash when EmitRawText was called on a obj streamer. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205820 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
2 changed file(s) with 18 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
700700 return;
701701 }
702702 break;
703 case PPC::SYNC:
704 // In Book E sync is called msync, handle this special case here...
705 if (Subtarget.isBookE()) {
706 OutStreamer.EmitRawText(StringRef("\tmsync"));
707 return;
708 }
709 break;
710703 case PPC::LD:
711704 case PPC::STD:
712705 case PPC::LWA_32:
579579 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
580580 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
581581 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
582 def IsNotBookE : Predicate<"!PPCSubTarget.isBookE()">;
582583
583584 //===----------------------------------------------------------------------===//
584585 // PowerPC Multiclass Definitions.
15401541 "stmw $rS, $dst", LdStLMW, []>;
15411542
15421543 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1543 "sync $L", LdStSync, []>;
1544 def : Pat<(int_ppc_sync), (SYNC 0)>;
1544 "sync $L", LdStSync, []>, Requires<[IsNotBookE]>;
1545
1546 let isCodeGenOnly = 1 in {
1547 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1548 "msync", LdStSync, []>, Requires<[IsBookE]> {
1549 let L = 0;
1550 }
1551 }
1552
1553 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1554 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
15451555
15461556 //===----------------------------------------------------------------------===//
15471557 // PPC32 Arithmetic Instructions.
22832293 def : Pat<(f64 (fextend f32:$src)),
22842294 (COPY_TO_REGCLASS $src, F8RC)>;
22852295
2286 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>;
2296 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2297 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
22872298
22882299 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
22892300 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
23722383
23732384 def : InstAlias<"sc", (SC 0)>;
23742385
2375 def : InstAlias<"sync", (SYNC 0)>;
2376 def : InstAlias<"msync", (SYNC 0)>;
2377 def : InstAlias<"lwsync", (SYNC 1)>;
2378 def : InstAlias<"ptesync", (SYNC 2)>;
2386 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
2387 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
2388 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
2389 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
23792390
23802391 def : InstAlias<"wait", (WAIT 0)>;
23812392 def : InstAlias<"waitrsv", (WAIT 1)>;