llvm.org GIT mirror llvm / ee57dd4
[MIPS GlobalISel] Select MSA vector generic and builtin add Select vector G_ADD for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_addv_<format> will be transformed into G_ADD in legalizeIntrinsic and selected in the same way. __builtin_msa_addvi_<format> will be directly selected into ADDVI_<format> in legalizeIntrinsic. MIR tests for it have unnecessary additional copies. Capture current state of tests with run-pass=legalizer with a test in test/CodeGen/MIR/Mips. Differential Revision: https://reviews.llvm.org/D68984 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375501 91177308-0d34-0410-b5e6-96231b3b80d8 Petar Avramovic 1 year, 5 days ago
10 changed file(s) with 964 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
4040 return false;
4141 }
4242
43 static bool CheckTyN(unsigned N, const LegalityQuery &Query,
44 std::initializer_list SupportedValues) {
45 for (auto &Val : SupportedValues)
46 if (Val == Query.Types[N])
47 return true;
48 return false;
49 }
50
4351 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
4452 using namespace TargetOpcode;
4553
5260 const LLT v2s64 = LLT::vector(2, 64);
5361 const LLT p0 = LLT::pointer(0, 32);
5462
55 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
56 .legalFor({s32})
63 getActionDefinitionsBuilder({G_SUB, G_MUL})
64 .legalFor({s32})
65 .clampScalar(0, s32, s32);
66
67 getActionDefinitionsBuilder(G_ADD)
68 .legalIf([=, &ST](const LegalityQuery &Query) {
69 if (CheckTyN(0, Query, {s32}))
70 return true;
71 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
72 return true;
73 return false;
74 })
5775 .clampScalar(0, s32, s32);
5876
5977 getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
269287 return true;
270288 }
271289
290 static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode,
291 MachineIRBuilder &MIRBuilder,
292 const MipsSubtarget &ST) {
293 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
294 if (!MIRBuilder.buildInstr(Opcode)
295 .add(MI.getOperand(0))
296 .add(MI.getOperand(2))
297 .add(MI.getOperand(3))
298 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(),
299 *ST.getRegBankInfo()))
300 return false;
301 MI.eraseFromParent();
302 return true;
303 }
304
305 static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
306 MachineIRBuilder &MIRBuilder,
307 const MipsSubtarget &ST) {
308 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
309 MIRBuilder.buildInstr(Opcode)
310 .add(MI.getOperand(0))
311 .add(MI.getOperand(2))
312 .add(MI.getOperand(3));
313 MI.eraseFromParent();
314 return true;
315 }
316
272317 bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
273318 MachineRegisterInfo &MRI,
274319 MachineIRBuilder &MIRBuilder) const {
305350 MI.eraseFromParent();
306351 return true;
307352 }
353 case Intrinsic::mips_addv_b:
354 case Intrinsic::mips_addv_h:
355 case Intrinsic::mips_addv_w:
356 case Intrinsic::mips_addv_d:
357 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_ADD, MIRBuilder, ST);
358 case Intrinsic::mips_addvi_b:
359 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST);
360 case Intrinsic::mips_addvi_h:
361 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST);
362 case Intrinsic::mips_addvi_w:
363 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST);
364 case Intrinsic::mips_addvi_d:
365 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST);
308366 default:
309367 break;
310368 }
436436
437437 switch (Opc) {
438438 case G_TRUNC:
439 case G_ADD:
440439 case G_SUB:
441440 case G_MUL:
442441 case G_UMULH:
458457 case G_BRINDIRECT:
459458 case G_VASTART:
460459 OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
460 break;
461 case G_ADD:
462 OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
463 if (Op0Size == 128)
464 OperandsMapping = getMSAMapping(MF);
461465 break;
462466 case G_STORE:
463467 case G_LOAD:
0 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -stop-after=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
2
3 ; Check there are no COPY instructions surrounding ADDVI_W instruction.
4 ; All virtual registers were created with createGenericVirtualRegister
5 ; which sets RegClassOrRegBank in VRegInfo.
6 ; Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
7 ; gets selected into ADDVI_W works as expected.
8 ; Check that setRegClassOrRegBank.mir has same output.
9
10 declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
11 define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) {
12 ; P5600-LABEL: name: add_v4i32_builtin_imm
13 ; P5600: bb.1.entry:
14 ; P5600: liveins: $a0, $a1
15 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
16 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
17 ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
18 ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
19 ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
20 ; P5600: RetRA
21 entry:
22 %0 = load <4 x i32>, <4 x i32>* %a, align 16
23 %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 25)
24 store <4 x i32> %1, <4 x i32>* %c, align 16
25 ret void
26 }
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
2
3 # Check there are COPY instructions surrounding ADDVI_W instruction.
4 # MIParser does not set RegClassOrRegBank for parsed virtual registers.
5 # Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
6 # gets selected into ADDVI_W creates additional copies.
7 # FixMe: Make sure this test has same output as setRegClassOrRegBank.ll.
8
9 --- |
10
11 declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
12 define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }
13
14 ...
15 ---
16 name: add_v4i32_builtin_imm
17 alignment: 4
18 tracksRegLiveness: true
19 body: |
20 bb.1.entry:
21 liveins: $a0, $a1
22
23 ; P5600-LABEL: name: add_v4i32_builtin_imm
24 ; P5600: liveins: $a0, $a1
25 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
26 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
27 ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
28 ; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>)
29 ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25
30 ; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]]
31 ; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
32 ; P5600: RetRA
33 %0:_(p0) = COPY $a0
34 %1:_(p0) = COPY $a1
35 %2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
36 %3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25
37 G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
38 RetRA
39
40 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
2 --- |
3
4 define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
5 define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
6 define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
7 define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
8
9 ...
10 ---
11 name: add_v16i8
12 alignment: 4
13 legalized: true
14 regBankSelected: true
15 tracksRegLiveness: true
16 body: |
17 bb.1.entry:
18 liveins: $a0, $a1, $a2
19
20 ; P5600-LABEL: name: add_v16i8
21 ; P5600: liveins: $a0, $a1, $a2
22 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
23 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
24 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
25 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
26 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
27 ; P5600: [[ADDV_B:%[0-9]+]]:msa128b = ADDV_B [[LD_B1]], [[LD_B]]
28 ; P5600: ST_B [[ADDV_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
29 ; P5600: RetRA
30 %0:gprb(p0) = COPY $a0
31 %1:gprb(p0) = COPY $a1
32 %2:gprb(p0) = COPY $a2
33 %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
34 %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
35 %5:fprb(<16 x s8>) = G_ADD %4, %3
36 G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
37 RetRA
38
39 ...
40 ---
41 name: add_v8i16
42 alignment: 4
43 legalized: true
44 regBankSelected: true
45 tracksRegLiveness: true
46 body: |
47 bb.1.entry:
48 liveins: $a0, $a1, $a2
49
50 ; P5600-LABEL: name: add_v8i16
51 ; P5600: liveins: $a0, $a1, $a2
52 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
53 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
54 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
55 ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.a)
56 ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b)
57 ; P5600: [[ADDV_H:%[0-9]+]]:msa128h = ADDV_H [[LD_H1]], [[LD_H]]
58 ; P5600: ST_H [[ADDV_H]], [[COPY2]], 0 :: (store 16 into %ir.c)
59 ; P5600: RetRA
60 %0:gprb(p0) = COPY $a0
61 %1:gprb(p0) = COPY $a1
62 %2:gprb(p0) = COPY $a2
63 %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
64 %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
65 %5:fprb(<8 x s16>) = G_ADD %4, %3
66 G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
67 RetRA
68
69 ...
70 ---
71 name: add_v4i32
72 alignment: 4
73 legalized: true
74 regBankSelected: true
75 tracksRegLiveness: true
76 body: |
77 bb.1.entry:
78 liveins: $a0, $a1, $a2
79
80 ; P5600-LABEL: name: add_v4i32
81 ; P5600: liveins: $a0, $a1, $a2
82 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
83 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
84 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
85 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
86 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
87 ; P5600: [[ADDV_W:%[0-9]+]]:msa128w = ADDV_W [[LD_W1]], [[LD_W]]
88 ; P5600: ST_W [[ADDV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
89 ; P5600: RetRA
90 %0:gprb(p0) = COPY $a0
91 %1:gprb(p0) = COPY $a1
92 %2:gprb(p0) = COPY $a2
93 %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
94 %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
95 %5:fprb(<4 x s32>) = G_ADD %4, %3
96 G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
97 RetRA
98
99 ...
100 ---
101 name: add_v2i64
102 alignment: 4
103 legalized: true
104 regBankSelected: true
105 tracksRegLiveness: true
106 body: |
107 bb.1.entry:
108 liveins: $a0, $a1, $a2
109
110 ; P5600-LABEL: name: add_v2i64
111 ; P5600: liveins: $a0, $a1, $a2
112 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
113 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
114 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
115 ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.a)
116 ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)
117 ; P5600: [[ADDV_D:%[0-9]+]]:msa128d = ADDV_D [[LD_D1]], [[LD_D]]
118 ; P5600: ST_D [[ADDV_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
119 ; P5600: RetRA
120 %0:gprb(p0) = COPY $a0
121 %1:gprb(p0) = COPY $a1
122 %2:gprb(p0) = COPY $a2
123 %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
124 %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
125 %5:fprb(<2 x s64>) = G_ADD %4, %3
126 G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
127 RetRA
128
129 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
2 --- |
3
4 define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
5 define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
6 define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
7 define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
8
9 ...
10 ---
11 name: add_v16i8
12 alignment: 4
13 tracksRegLiveness: true
14 body: |
15 bb.1.entry:
16 liveins: $a0, $a1, $a2
17
18 ; P5600-LABEL: name: add_v16i8
19 ; P5600: liveins: $a0, $a1, $a2
20 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
21 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
22 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
23 ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
24 ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
25 ; P5600: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[LOAD1]], [[LOAD]]
26 ; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
27 ; P5600: RetRA
28 %0:_(p0) = COPY $a0
29 %1:_(p0) = COPY $a1
30 %2:_(p0) = COPY $a2
31 %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
32 %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
33 %5:_(<16 x s8>) = G_ADD %4, %3
34 G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
35 RetRA
36
37 ...
38 ---
39 name: add_v8i16
40 alignment: 4
41 tracksRegLiveness: true
42 body: |
43 bb.1.entry:
44 liveins: $a0, $a1, $a2
45
46 ; P5600-LABEL: name: add_v8i16
47 ; P5600: liveins: $a0, $a1, $a2
48 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
49 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
50 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
51 ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
52 ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
53 ; P5600: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LOAD1]], [[LOAD]]
54 ; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
55 ; P5600: RetRA
56 %0:_(p0) = COPY $a0
57 %1:_(p0) = COPY $a1
58 %2:_(p0) = COPY $a2
59 %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
60 %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
61 %5:_(<8 x s16>) = G_ADD %4, %3
62 G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
63 RetRA
64
65 ...
66 ---
67 name: add_v4i32
68 alignment: 4
69 tracksRegLiveness: true
70 body: |
71 bb.1.entry:
72 liveins: $a0, $a1, $a2
73
74 ; P5600-LABEL: name: add_v4i32
75 ; P5600: liveins: $a0, $a1, $a2
76 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
77 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
78 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
79 ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
80 ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
81 ; P5600: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[LOAD1]], [[LOAD]]
82 ; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
83 ; P5600: RetRA
84 %0:_(p0) = COPY $a0
85 %1:_(p0) = COPY $a1
86 %2:_(p0) = COPY $a2
87 %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
88 %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
89 %5:_(<4 x s32>) = G_ADD %4, %3
90 G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
91 RetRA
92
93 ...
94 ---
95 name: add_v2i64
96 alignment: 4
97 tracksRegLiveness: true
98 body: |
99 bb.1.entry:
100 liveins: $a0, $a1, $a2
101
102 ; P5600-LABEL: name: add_v2i64
103 ; P5600: liveins: $a0, $a1, $a2
104 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
105 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
106 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
107 ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
108 ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
109 ; P5600: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[LOAD1]], [[LOAD]]
110 ; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
111 ; P5600: RetRA
112 %0:_(p0) = COPY $a0
113 %1:_(p0) = COPY $a1
114 %2:_(p0) = COPY $a2
115 %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
116 %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
117 %5:_(<2 x s64>) = G_ADD %4, %3
118 G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
119 RetRA
120
121 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
2 --- |
3
4 declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>)
5 define void @add_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
6
7 declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>)
8 define void @add_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
9
10 declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>)
11 define void @add_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
12
13 declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>)
14 define void @add_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
15
16 declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32 immarg)
17 define void @add_v16i8_builtin_imm(<16 x i8>* %a, <16 x i8>* %c) { entry: ret void }
18
19 declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32 immarg)
20 define void @add_v8i16_builtin_imm(<8 x i16>* %a, <8 x i16>* %c) { entry: ret void }
21
22 declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
23 define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }
24
25 declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32 immarg)
26 define void @add_v2i64_builtin_imm(<2 x i64>* %a, <2 x i64>* %c) { entry: ret void }
27
28 ...
29 ---
30 name: add_v16i8_builtin
31 alignment: 4
32 tracksRegLiveness: true
33 body: |
34 bb.1.entry:
35 liveins: $a0, $a1, $a2
36
37 ; P5600-LABEL: name: add_v16i8_builtin
38 ; P5600: liveins: $a0, $a1, $a2
39 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
40 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
41 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
42 ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
43 ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
44 ; P5600: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[LOAD]], [[LOAD1]]
45 ; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
46 ; P5600: RetRA
47 %0:_(p0) = COPY $a0
48 %1:_(p0) = COPY $a1
49 %2:_(p0) = COPY $a2
50 %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
51 %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
52 %5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.addv.b), %3(<16 x s8>), %4(<16 x s8>)
53 G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
54 RetRA
55
56 ...
57 ---
58 name: add_v8i16_builtin
59 alignment: 4
60 tracksRegLiveness: true
61 body: |
62 bb.1.entry:
63 liveins: $a0, $a1, $a2
64
65 ; P5600-LABEL: name: add_v8i16_builtin
66 ; P5600: liveins: $a0, $a1, $a2
67 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
68 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
69 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
70 ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
71 ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
72 ; P5600: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LOAD]], [[LOAD1]]
73 ; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
74 ; P5600: RetRA
75 %0:_(p0) = COPY $a0
76 %1:_(p0) = COPY $a1
77 %2:_(p0) = COPY $a2
78 %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
79 %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
80 %5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.addv.h), %3(<8 x s16>), %4(<8 x s16>)
81 G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
82 RetRA
83
84 ...
85 ---
86 name: add_v4i32_builtin
87 alignment: 4
88 tracksRegLiveness: true
89 body: |
90 bb.1.entry:
91 liveins: $a0, $a1, $a2
92
93 ; P5600-LABEL: name: add_v4i32_builtin
94 ; P5600: liveins: $a0, $a1, $a2
95 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
96 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
97 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
98 ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
99 ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
100 ; P5600: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[LOAD]], [[LOAD1]]
101 ; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
102 ; P5600: RetRA
103 %0:_(p0) = COPY $a0
104 %1:_(p0) = COPY $a1
105 %2:_(p0) = COPY $a2
106 %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
107 %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
108 %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addv.w), %3(<4 x s32>), %4(<4 x s32>)
109 G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
110 RetRA
111
112 ...
113 ---
114 name: add_v2i64_builtin
115 alignment: 4
116 tracksRegLiveness: true
117 body: |
118 bb.1.entry:
119 liveins: $a0, $a1, $a2
120
121 ; P5600-LABEL: name: add_v2i64_builtin
122 ; P5600: liveins: $a0, $a1, $a2
123 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
124 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
125 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
126 ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
127 ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
128 ; P5600: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[LOAD]], [[LOAD1]]
129 ; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
130 ; P5600: RetRA
131 %0:_(p0) = COPY $a0
132 %1:_(p0) = COPY $a1
133 %2:_(p0) = COPY $a2
134 %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
135 %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
136 %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.addv.d), %3(<2 x s64>), %4(<2 x s64>)
137 G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
138 RetRA
139
140 ...
141 ---
142 name: add_v16i8_builtin_imm
143 alignment: 4
144 tracksRegLiveness: true
145 body: |
146 bb.1.entry:
147 liveins: $a0, $a1
148
149 ; P5600-LABEL: name: add_v16i8_builtin_imm
150 ; P5600: liveins: $a0, $a1
151 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
152 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
153 ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
154 ; P5600: [[COPY2:%[0-9]+]]:msa128b = COPY [[LOAD]](<16 x s8>)
155 ; P5600: [[ADDVI_B:%[0-9]+]]:msa128b = ADDVI_B [[COPY2]], 3
156 ; P5600: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY [[ADDVI_B]]
157 ; P5600: G_STORE [[COPY3]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c)
158 ; P5600: RetRA
159 %0:_(p0) = COPY $a0
160 %1:_(p0) = COPY $a1
161 %2:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
162 %3:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.b), %2(<16 x s8>), 3
163 G_STORE %3(<16 x s8>), %1(p0) :: (store 16 into %ir.c)
164 RetRA
165
166 ...
167 ---
168 name: add_v8i16_builtin_imm
169 alignment: 4
170 tracksRegLiveness: true
171 body: |
172 bb.1.entry:
173 liveins: $a0, $a1
174
175 ; P5600-LABEL: name: add_v8i16_builtin_imm
176 ; P5600: liveins: $a0, $a1
177 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
178 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
179 ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
180 ; P5600: [[COPY2:%[0-9]+]]:msa128h = COPY [[LOAD]](<8 x s16>)
181 ; P5600: [[ADDVI_H:%[0-9]+]]:msa128h = ADDVI_H [[COPY2]], 18
182 ; P5600: [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY [[ADDVI_H]]
183 ; P5600: G_STORE [[COPY3]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c)
184 ; P5600: RetRA
185 %0:_(p0) = COPY $a0
186 %1:_(p0) = COPY $a1
187 %2:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
188 %3:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.h), %2(<8 x s16>), 18
189 G_STORE %3(<8 x s16>), %1(p0) :: (store 16 into %ir.c)
190 RetRA
191
192 ...
193 ---
194 name: add_v4i32_builtin_imm
195 alignment: 4
196 tracksRegLiveness: true
197 body: |
198 bb.1.entry:
199 liveins: $a0, $a1
200
201 ; P5600-LABEL: name: add_v4i32_builtin_imm
202 ; P5600: liveins: $a0, $a1
203 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
204 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
205 ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
206 ; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>)
207 ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25
208 ; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]]
209 ; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
210 ; P5600: RetRA
211 %0:_(p0) = COPY $a0
212 %1:_(p0) = COPY $a1
213 %2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
214 %3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25
215 G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
216 RetRA
217
218 ...
219 ---
220 name: add_v2i64_builtin_imm
221 alignment: 4
222 tracksRegLiveness: true
223 body: |
224 bb.1.entry:
225 liveins: $a0, $a1
226
227 ; P5600-LABEL: name: add_v2i64_builtin_imm
228 ; P5600: liveins: $a0, $a1
229 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
230 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
231 ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
232 ; P5600: [[COPY2:%[0-9]+]]:msa128d = COPY [[LOAD]](<2 x s64>)
233 ; P5600: [[ADDVI_D:%[0-9]+]]:msa128d = ADDVI_D [[COPY2]], 31
234 ; P5600: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY [[ADDVI_D]]
235 ; P5600: G_STORE [[COPY3]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
236 ; P5600: RetRA
237 %0:_(p0) = COPY $a0
238 %1:_(p0) = COPY $a1
239 %2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
240 %3:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.d), %2(<2 x s64>), 31
241 G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.c)
242 RetRA
243
244 ...
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
2
3 define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
4 ; P5600-LABEL: add_v16i8:
5 ; P5600: # %bb.0: # %entry
6 ; P5600-NEXT: ld.b $w0, 0($4)
7 ; P5600-NEXT: ld.b $w1, 0($5)
8 ; P5600-NEXT: addv.b $w0, $w1, $w0
9 ; P5600-NEXT: st.b $w0, 0($6)
10 ; P5600-NEXT: jr $ra
11 ; P5600-NEXT: nop
12 entry:
13 %0 = load <16 x i8>, <16 x i8>* %a, align 16
14 %1 = load <16 x i8>, <16 x i8>* %b, align 16
15 %add = add <16 x i8> %1, %0
16 store <16 x i8> %add, <16 x i8>* %c, align 16
17 ret void
18 }
19
20 define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
21 ; P5600-LABEL: add_v8i16:
22 ; P5600: # %bb.0: # %entry
23 ; P5600-NEXT: ld.h $w0, 0($4)
24 ; P5600-NEXT: ld.h $w1, 0($5)
25 ; P5600-NEXT: addv.h $w0, $w1, $w0
26 ; P5600-NEXT: st.h $w0, 0($6)
27 ; P5600-NEXT: jr $ra
28 ; P5600-NEXT: nop
29 entry:
30 %0 = load <8 x i16>, <8 x i16>* %a, align 16
31 %1 = load <8 x i16>, <8 x i16>* %b, align 16
32 %add = add <8 x i16> %1, %0
33 store <8 x i16> %add, <8 x i16>* %c, align 16
34 ret void
35 }
36
37 define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
38 ; P5600-LABEL: add_v4i32:
39 ; P5600: # %bb.0: # %entry
40 ; P5600-NEXT: ld.w $w0, 0($4)
41 ; P5600-NEXT: ld.w $w1, 0($5)
42 ; P5600-NEXT: addv.w $w0, $w1, $w0
43 ; P5600-NEXT: st.w $w0, 0($6)
44 ; P5600-NEXT: jr $ra
45 ; P5600-NEXT: nop
46 entry:
47 %0 = load <4 x i32>, <4 x i32>* %a, align 16
48 %1 = load <4 x i32>, <4 x i32>* %b, align 16
49 %add = add <4 x i32> %1, %0
50 store <4 x i32> %add, <4 x i32>* %c, align 16
51 ret void
52 }
53
54 define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
55 ; P5600-LABEL: add_v2i64:
56 ; P5600: # %bb.0: # %entry
57 ; P5600-NEXT: ld.d $w0, 0($4)
58 ; P5600-NEXT: ld.d $w1, 0($5)
59 ; P5600-NEXT: addv.d $w0, $w1, $w0
60 ; P5600-NEXT: st.d $w0, 0($6)
61 ; P5600-NEXT: jr $ra
62 ; P5600-NEXT: nop
63 entry:
64 %0 = load <2 x i64>, <2 x i64>* %a, align 16
65 %1 = load <2 x i64>, <2 x i64>* %b, align 16
66 %add = add <2 x i64> %1, %0
67 store <2 x i64> %add, <2 x i64>* %c, align 16
68 ret void
69 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
2
3 declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>)
4 define void @add_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
5 ; P5600-LABEL: add_v16i8_builtin:
6 ; P5600: # %bb.0: # %entry
7 ; P5600-NEXT: ld.b $w0, 0($4)
8 ; P5600-NEXT: ld.b $w1, 0($5)
9 ; P5600-NEXT: addv.b $w0, $w0, $w1
10 ; P5600-NEXT: st.b $w0, 0($6)
11 ; P5600-NEXT: jr $ra
12 ; P5600-NEXT: nop
13 entry:
14 %0 = load <16 x i8>, <16 x i8>* %a, align 16
15 %1 = load <16 x i8>, <16 x i8>* %b, align 16
16 %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
17 store <16 x i8> %2, <16 x i8>* %c, align 16
18 ret void
19 }
20
21 declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>)
22 define void @add_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
23 ; P5600-LABEL: add_v8i16_builtin:
24 ; P5600: # %bb.0: # %entry
25 ; P5600-NEXT: ld.h $w0, 0($4)
26 ; P5600-NEXT: ld.h $w1, 0($5)
27 ; P5600-NEXT: addv.h $w0, $w0, $w1
28 ; P5600-NEXT: st.h $w0, 0($6)
29 ; P5600-NEXT: jr $ra
30 ; P5600-NEXT: nop
31 entry:
32 %0 = load <8 x i16>, <8 x i16>* %a, align 16
33 %1 = load <8 x i16>, <8 x i16>* %b, align 16
34 %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1)
35 store <8 x i16> %2, <8 x i16>* %c, align 16
36 ret void
37 }
38
39 declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>)
40 define void @add_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
41 ; P5600-LABEL: add_v4i32_builtin:
42 ; P5600: # %bb.0: # %entry
43 ; P5600-NEXT: ld.w $w0, 0($4)
44 ; P5600-NEXT: ld.w $w1, 0($5)
45 ; P5600-NEXT: addv.w $w0, $w0, $w1
46 ; P5600-NEXT: st.w $w0, 0($6)
47 ; P5600-NEXT: jr $ra
48 ; P5600-NEXT: nop
49 entry:
50 %0 = load <4 x i32>, <4 x i32>* %a, align 16
51 %1 = load <4 x i32>, <4 x i32>* %b, align 16
52 %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)
53 store <4 x i32> %2, <4 x i32>* %c, align 16
54 ret void
55 }
56
57 declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>)
58 define void @add_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
59 ; P5600-LABEL: add_v2i64_builtin:
60 ; P5600: # %bb.0: # %entry
61 ; P5600-NEXT: ld.d $w0, 0($4)
62 ; P5600-NEXT: ld.d $w1, 0($5)
63 ; P5600-NEXT: addv.d $w0, $w0, $w1
64 ; P5600-NEXT: st.d $w0, 0($6)
65 ; P5600-NEXT: jr $ra
66 ; P5600-NEXT: nop
67 entry:
68 %0 = load <2 x i64>, <2 x i64>* %a, align 16
69 %1 = load <2 x i64>, <2 x i64>* %b, align 16
70 %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1)
71 store <2 x i64> %2, <2 x i64>* %c, align 16
72 ret void
73 }
74
75 declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32 immarg)
76 define void @add_v16i8_builtin_imm(<16 x i8>* %a, <16 x i8>* %c) {
77 ; P5600-LABEL: add_v16i8_builtin_imm:
78 ; P5600: # %bb.0: # %entry
79 ; P5600-NEXT: ld.b $w0, 0($4)
80 ; P5600-NEXT: addvi.b $w0, $w0, 3
81 ; P5600-NEXT: st.b $w0, 0($5)
82 ; P5600-NEXT: jr $ra
83 ; P5600-NEXT: nop
84 entry:
85 %0 = load <16 x i8>, <16 x i8>* %a, align 16
86 %1 = tail call <16 x i8> @llvm.mips.addvi.b(<16 x i8> %0, i32 3)
87 store <16 x i8> %1, <16 x i8>* %c, align 16
88 ret void
89 }
90
91 declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32 immarg)
92 define void @add_v8i16_builtin_imm(<8 x i16>* %a, <8 x i16>* %c) {
93 ; P5600-LABEL: add_v8i16_builtin_imm:
94 ; P5600: # %bb.0: # %entry
95 ; P5600-NEXT: ld.h $w0, 0($4)
96 ; P5600-NEXT: addvi.h $w0, $w0, 18
97 ; P5600-NEXT: st.h $w0, 0($5)
98 ; P5600-NEXT: jr $ra
99 ; P5600-NEXT: nop
100 entry:
101 %0 = load <8 x i16>, <8 x i16>* %a, align 16
102 %1 = tail call <8 x i16> @llvm.mips.addvi.h(<8 x i16> %0, i32 18)
103 store <8 x i16> %1, <8 x i16>* %c, align 16
104 ret void
105 }
106
107 declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
108 define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) {
109 ; P5600-LABEL: add_v4i32_builtin_imm:
110 ; P5600: # %bb.0: # %entry
111 ; P5600-NEXT: ld.w $w0, 0($4)
112 ; P5600-NEXT: addvi.w $w0, $w0, 25
113 ; P5600-NEXT: st.w $w0, 0($5)
114 ; P5600-NEXT: jr $ra
115 ; P5600-NEXT: nop
116 entry:
117 %0 = load <4 x i32>, <4 x i32>* %a, align 16
118 %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 25)
119 store <4 x i32> %1, <4 x i32>* %c, align 16
120 ret void
121 }
122
123 declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32 immarg)
124 define void @add_v2i64_builtin_imm(<2 x i64>* %a, <2 x i64>* %c) {
125 ; P5600-LABEL: add_v2i64_builtin_imm:
126 ; P5600: # %bb.0: # %entry
127 ; P5600-NEXT: ld.d $w0, 0($4)
128 ; P5600-NEXT: addvi.d $w0, $w0, 31
129 ; P5600-NEXT: st.d $w0, 0($5)
130 ; P5600-NEXT: jr $ra
131 ; P5600-NEXT: nop
132 entry:
133 %0 = load <2 x i64>, <2 x i64>* %a, align 16
134 %1 = tail call <2 x i64> @llvm.mips.addvi.d(<2 x i64> %0, i32 31)
135 store <2 x i64> %1, <2 x i64>* %c, align 16
136 ret void
137 }
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
2 --- |
3
4 define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
5 define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
6 define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
7 define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
8
9 ...
10 ---
11 name: add_v16i8
12 alignment: 4
13 legalized: true
14 tracksRegLiveness: true
15 body: |
16 bb.1.entry:
17 liveins: $a0, $a1, $a2
18
19 ; P5600-LABEL: name: add_v16i8
20 ; P5600: liveins: $a0, $a1, $a2
21 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
22 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
23 ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
24 ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
25 ; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
26 ; P5600: [[ADD:%[0-9]+]]:fprb(<16 x s8>) = G_ADD [[LOAD1]], [[LOAD]]
27 ; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
28 ; P5600: RetRA
29 %0:_(p0) = COPY $a0
30 %1:_(p0) = COPY $a1
31 %2:_(p0) = COPY $a2
32 %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
33 %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
34 %5:_(<16 x s8>) = G_ADD %4, %3
35 G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
36 RetRA
37
38 ...
39 ---
40 name: add_v8i16
41 alignment: 4
42 legalized: true
43 tracksRegLiveness: true
44 body: |
45 bb.1.entry:
46 liveins: $a0, $a1, $a2
47
48 ; P5600-LABEL: name: add_v8i16
49 ; P5600: liveins: $a0, $a1, $a2
50 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
51 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
52 ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
53 ; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
54 ; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
55 ; P5600: [[ADD:%[0-9]+]]:fprb(<8 x s16>) = G_ADD [[LOAD1]], [[LOAD]]
56 ; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
57 ; P5600: RetRA
58 %0:_(p0) = COPY $a0
59 %1:_(p0) = COPY $a1
60 %2:_(p0) = COPY $a2
61 %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
62 %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
63 %5:_(<8 x s16>) = G_ADD %4, %3
64 G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
65 RetRA
66
67 ...
68 ---
69 name: add_v4i32
70 alignment: 4
71 legalized: true
72 tracksRegLiveness: true
73 body: |
74 bb.1.entry:
75 liveins: $a0, $a1, $a2
76
77 ; P5600-LABEL: name: add_v4i32
78 ; P5600: liveins: $a0, $a1, $a2
79 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
80 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
81 ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
82 ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
83 ; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
84 ; P5600: [[ADD:%[0-9]+]]:fprb(<4 x s32>) = G_ADD [[LOAD1]], [[LOAD]]
85 ; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
86 ; P5600: RetRA
87 %0:_(p0) = COPY $a0
88 %1:_(p0) = COPY $a1
89 %2:_(p0) = COPY $a2
90 %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
91 %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
92 %5:_(<4 x s32>) = G_ADD %4, %3
93 G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
94 RetRA
95
96 ...
97 ---
98 name: add_v2i64
99 alignment: 4
100 legalized: true
101 tracksRegLiveness: true
102 body: |
103 bb.1.entry:
104 liveins: $a0, $a1, $a2
105
106 ; P5600-LABEL: name: add_v2i64
107 ; P5600: liveins: $a0, $a1, $a2
108 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
109 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
110 ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
111 ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
112 ; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
113 ; P5600: [[ADD:%[0-9]+]]:fprb(<2 x s64>) = G_ADD [[LOAD1]], [[LOAD]]
114 ; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
115 ; P5600: RetRA
116 %0:_(p0) = COPY $a0
117 %1:_(p0) = COPY $a1
118 %2:_(p0) = COPY $a2
119 %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
120 %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
121 %5:_(<2 x s64>) = G_ADD %4, %3
122 G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
123 RetRA
124
125 ...