llvm.org GIT mirror llvm / ee46574
Move getX86RegNum into X86RegisterInfo and use it in the trampoline lowering. Lookup the jump and mov opcodes for the trampoline rather than hard coding them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41577 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan Sands 12 years ago
6 changed file(s) with 80 addition(s) and 88 deletion(s). Raw diff Collapse all Expand all
1212 //===----------------------------------------------------------------------===//
1313
1414 #define DEBUG_TYPE "x86-emitter"
15 #include "X86CodeEmitter.h"
1615 #include "X86InstrInfo.h"
1716 #include "X86Subtarget.h"
1817 #include "X86TargetMachine.h"
192191 MCE.emitWordLE(0); // The relocated value will be added to the displacement
193192 }
194193
195 // getX86RegNum - This function maps LLVM register identifiers to their X86
196 // specific numbering, which is used in various places encoding instructions.
197 //
198194 unsigned Emitter::getX86RegNum(unsigned RegNo) {
199 switch(RegNo) {
200 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
201 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
202 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
203 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
204 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
205 return N86::ESP;
206 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
207 return N86::EBP;
208 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
209 return N86::ESI;
210 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
211 return N86::EDI;
212
213 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
214 return N86::EAX;
215 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
216 return N86::ECX;
217 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
218 return N86::EDX;
219 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
220 return N86::EBX;
221 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
222 return N86::ESP;
223 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
224 return N86::EBP;
225 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
226 return N86::ESI;
227 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
228 return N86::EDI;
229
230 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
231 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
232 return RegNo-X86::ST0;
233
234 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
235 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
236 return II->getRegisterInfo().getDwarfRegNum(RegNo) -
237 II->getRegisterInfo().getDwarfRegNum(X86::XMM0);
238 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
239 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
240 return II->getRegisterInfo().getDwarfRegNum(RegNo) -
241 II->getRegisterInfo().getDwarfRegNum(X86::XMM8);
242
243 default:
244 assert(MRegisterInfo::isVirtualRegister(RegNo) &&
245 "Unknown physical register!");
246 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
247 return 0;
248 }
195 return ((X86RegisterInfo&)II->getRegisterInfo()).getX86RegNum(RegNo);
249196 }
250197
251198 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
+0
-25
lib/Target/X86/X86CodeEmitter.h less more
None //===-- X86CodeEmitter.h - X86 DAG Lowering Interface -----------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by Duncan Sands and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines utilities for X86 code emission.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef X86CODEEMITTER_H
14 #define X86CODEEMITTER_H
15
16 /// N86 namespace - Native X86 Register numbers... used by X86 backend.
17 ///
18 namespace N86 {
19 enum {
20 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
21 };
22 }
23
24 #endif // X86CODEEMITTER_H
1212 //===----------------------------------------------------------------------===//
1313
1414 #include "X86.h"
15 #include "X86CodeEmitter.h"
1615 #include "X86InstrBuilder.h"
1716 #include "X86ISelLowering.h"
1817 #include "X86MachineFunctionInfo.h"
43294328 Function *Func = (Function *)
43304329 cast(cast(Op.getOperand(5))->getValue());
43314330 unsigned CC = Func->getCallingConv();
4332 unsigned char NestReg;
4331 unsigned NestReg;
43334332
43344333 switch (CC) {
43354334 default:
43394338 case CallingConv::X86_StdCall: {
43404339 // Pass 'nest' parameter in ECX.
43414340 // Must be kept in sync with X86CallingConv.td
4342 NestReg = N86::ECX;
4341 NestReg = X86::ECX;
43434342
43444343 // Check that ECX wasn't needed by an 'inreg' parameter.
43454344 const FunctionType *FTy = Func->getFunctionType();
43654364 case CallingConv::X86_FastCall:
43664365 // Pass 'nest' parameter in EAX.
43674366 // Must be kept in sync with X86CallingConv.td
4368 NestReg = N86::EAX;
4367 NestReg = X86::EAX;
43694368 break;
43704369 }
4370
4371 const X86InstrInfo *TII =
4372 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
43714373
43724374 SDOperand OutChains[4];
43734375 SDOperand Addr, Disp;
43754377 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
43764378 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
43774379
4378 const unsigned char MOV32ri = 0xB8;
4379 const unsigned char JMP = 0xE9;
4380
4381 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|NestReg, MVT::i8),
4380 unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
4381 unsigned char N86Reg = ((X86RegisterInfo&)RegInfo).getX86RegNum(NestReg);
4382 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
43824383 Trmp, TrmpSV->getValue(), TrmpSV->getOffset());
43834384
43844385 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
43854386 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
43864387 TrmpSV->getOffset() + 1, false, 1);
43874388
4389 unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
43884390 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
43894391 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
43904392 TrmpSV->getValue() + 5, TrmpSV->getOffset());
274274 const TargetRegisterClass *getPointerRegClass() const;
275275
276276 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
277 // specified opcode number.
277 // specified machine instruction.
278278 //
279279 unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
280280 return TID->TSFlags >> X86II::OpcodeShift;
281281 }
282 unsigned char getBaseOpcodeFor(MachineOpCode Opcode) const {
283 return getBaseOpcodeFor(&get(Opcode));
284 }
282285 };
283286
284287 } // End llvm namespace
6161 SlotSize = 4;
6262 StackPtr = X86::ESP;
6363 FramePtr = X86::EBP;
64 }
65 }
66
67 // getX86RegNum - This function maps LLVM register identifiers to their X86
68 // specific numbering, which is used in various places encoding instructions.
69 //
70 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
71 switch(RegNo) {
72 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
73 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
74 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
75 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
76 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
77 return N86::ESP;
78 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
79 return N86::EBP;
80 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
81 return N86::ESI;
82 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
83 return N86::EDI;
84
85 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
86 return N86::EAX;
87 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
88 return N86::ECX;
89 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
90 return N86::EDX;
91 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
92 return N86::EBX;
93 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
94 return N86::ESP;
95 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
96 return N86::EBP;
97 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
98 return N86::ESI;
99 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
100 return N86::EDI;
101
102 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
103 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
104 return RegNo-X86::ST0;
105
106 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
107 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
108 return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM0);
109 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
110 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
111 return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM8);
112
113 default:
114 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
115 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
116 return 0;
64117 }
65118 }
66119
2121 class TargetInstrInfo;
2222 class X86TargetMachine;
2323
24 /// N86 namespace - Native X86 register numbers
25 ///
26 namespace N86 {
27 enum {
28 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
29 };
30 }
31
2432 class X86RegisterInfo : public X86GenRegisterInfo {
2533 public:
2634 X86TargetMachine &TM;
4149
4250 public:
4351 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
52
53 /// getX86RegNum - Returns the native X86 register number for the given LLVM
54 /// register identifier.
55 unsigned getX86RegNum(unsigned RegNo);
4456
4557 /// Code Generation virtual methods...
4658 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,