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[BranchFolding] Allow hoisting to block with a single conditional branch. Summary: The BranchFolding pass is currently missing opportunities to hoist common code if the hoisted-to block contains a single conditional branch that has register uses. This occurs somewhat frequently on AArch64 with CBZ/TBZ opcodes. This change also eliminates some code differences when debug info is present since the presence of e.g. DBG_VALUE instructions in the hoisted-to block can enable hoisting that wouldn't have occurred without them. Reviewers: MatzeB, rnk, kparzysz, twoh, aprantl, javed.absar Subscribers: kristof.beyls, JDevlieghere, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46324 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332265 91177308-0d34-0410-b5e6-96231b3b80d8 Geoff Berry 1 year, 5 months ago
2 changed file(s) with 34 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
19141914
19151915 if (Uses.empty())
19161916 return Loc;
1917 // If the terminator is the only instruction in the block and Uses is not
1918 // empty (or we would have returned above), we can still safely hoist
1919 // instructions just before the terminator as long as the Defs/Uses are not
1920 // violated (which is checked in HoistCommonCodeInSuccs).
19171921 if (Loc == MBB->begin())
1918 return MBB->end();
1922 return Loc;
19191923
19201924 // The terminator is probably a conditional branch, try not to separate the
19211925 // branch from condition setting instruction.
0 # RUN: llc -o - %s -mtriple=aarch64 -run-pass branch-folder | FileCheck %s
1 # Check that BranchFolding pass is able to hoist a common instruction into a block with a single branch instruction.
2 name: func
3 tracksRegLiveness: true
4 body: |
5 bb.0:
6 ; CHECK-LABEL: name: func
7 ; CHECK-LABEL: bb.0:
8 ; CHECK: $x0 = ADDXri $x0, 1, 0
9 ; CHECK: CBZX $x1, %bb.2
10 liveins: $x1
11 CBZX $x1, %bb.2
12
13 bb.1:
14 ; CHECK-LABEL: bb.1:
15 ; CHECK-NOT: $x0 = ADDXri $x0, 1, 0
16 liveins: $x0
17 $x0 = ADDXri $x0, 1, 0
18 $x0 = ADDXri $x0, 2, 0
19 RET_ReallyLR implicit $x0
20
21 bb.2:
22 ; CHECK-LABEL: bb.2:
23 ; CHECK-NOT: $x0 = ADDXri $x0, 1, 0
24 liveins: $x0
25 $x0 = ADDXri $x0, 1, 0
26 $x0 = ADDXri $x0, 3, 0
27 RET_ReallyLR implicit $x0
28 ...