llvm.org GIT mirror llvm / edb2718
[PowerPC] Fix invalid displacement created by LocalStackAlloc This commit fixes a bug in PPCRegisterInfo::isFrameOffsetLegal that could result in the LocalStackAlloc pass creating an MI instruction out-of-range displacement: %vreg17<def> = LD 33184, %vreg31; mem:LD8[%g](align=32) %G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg31 (In final assembler output the top bits are stripped off, resulting in a negative offset loading from below the stack pointer.) Common code expects the isFrameOffsetLegal routine to verify whether adding a given offset to the offset already present in the instruction results in a valid displacement. However, on PowerPC the routine did not take the already present instruction offset into account. This commit fixes isFrameOffsetLegal to add the instruction offset, and updates a local caller (needsFrameBaseReg) to no longer add the instruction offset itself before calling isFrameOffsetLegal. Reviewed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212832 91177308-0d34-0410-b5e6-96231b3b80d8 Ulrich Weigand 5 years ago
2 changed file(s) with 81 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
884884 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
885885 assert(Offset < 0 && "Local offset must be negative");
886886
887 unsigned FIOperandNum = 0;
888 while (!MI->getOperand(FIOperandNum).isFI()) {
889 ++FIOperandNum;
890 assert(FIOperandNum < MI->getNumOperands() &&
891 "Instr doesn't have FrameIndex operand!");
892 }
893
894 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
895 Offset += MI->getOperand(OffsetOperandNo).getImm();
896
897887 // It's the load/store FI references that cause issues, as it can be difficult
898888 // to materialize the offset if it won't fit in the literal field. Estimate
899889 // based on the size of the local frame and some conservative assumptions
984974
985975 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
986976 int64_t Offset) const {
977 unsigned FIOperandNum = 0;
978 while (!MI->getOperand(FIOperandNum).isFI()) {
979 ++FIOperandNum;
980 assert(FIOperandNum < MI->getNumOperands() &&
981 "Instr doesn't have FrameIndex operand!");
982 }
983
984 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
985 Offset += MI->getOperand(OffsetOperandNo).getImm();
986
987987 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
988988 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));
989989 }
0 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -print-after=localstackalloc <%s >%t 2>&1 && FileCheck <%t %s
1
2 ; Due to a bug in isFrameOffsetLegal we ended up with resolveFrameIndex creating
3 ; addresses with out-of-range displacements. Verify that this no longer happens.
4 ; CHECK-NOT: LD {{3276[8-9]}}
5 ; CHECK-NOT: LD {{327[7-9][0-9]}}
6 ; CHECK-NOT: LD {{32[8-9][0-9][0-9]}}
7 ; CHECK-NOT: LD {{3[3-9][0-9][0-9][0-9]}}
8 ; CHECK-NOT: LD {{[4-9][0-9][0-9][0-9][0-9]}}
9 ; CHECK-NOT: LD {{[1-9][0-9][0-9][0-9][0-9][0-9]+}}
10
11 target datalayout = "e-m:e-i64:64-n32:64"
12 target triple = "powerpc64le-unknown-linux-gnu"
13
14 %struct.S2760 = type { <2 x float>, %struct.anon, i32, [28 x i8] }
15 %struct.anon = type { [11 x %struct.anon.0], i64, [6 x { i64, i64 }], [24 x i8] }
16 %struct.anon.0 = type { [30 x %union.U4DI], i8, [0 x i16], [30 x i8] }
17 %union.U4DI = type { <4 x i64> }
18
19 @s2760 = external global %struct.S2760
20 @fails = external global i32
21
22 define void @check2760(%struct.S2760* noalias sret %agg.result, %struct.S2760* byval align 16, %struct.S2760* %arg1, %struct.S2760* byval align 16) {
23 entry:
24 %arg0 = alloca %struct.S2760, align 32
25 %arg2 = alloca %struct.S2760, align 32
26 %arg1.addr = alloca %struct.S2760*, align 8
27 %ret = alloca %struct.S2760, align 32
28 %b1 = alloca %struct.S2760, align 32
29 %b2 = alloca %struct.S2760, align 32
30 %2 = bitcast %struct.S2760* %arg0 to i8*
31 %3 = bitcast %struct.S2760* %0 to i8*
32 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 11104, i32 16, i1 false)
33 %4 = bitcast %struct.S2760* %arg2 to i8*
34 %5 = bitcast %struct.S2760* %1 to i8*
35 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %4, i8* %5, i64 11104, i32 16, i1 false)
36 store %struct.S2760* %arg1, %struct.S2760** %arg1.addr, align 8
37 %6 = bitcast %struct.S2760* %ret to i8*
38 call void @llvm.memset.p0i8.i64(i8* %6, i8 0, i64 11104, i32 32, i1 false)
39 %7 = bitcast %struct.S2760* %b1 to i8*
40 call void @llvm.memset.p0i8.i64(i8* %7, i8 0, i64 11104, i32 32, i1 false)
41 %8 = bitcast %struct.S2760* %b2 to i8*
42 call void @llvm.memset.p0i8.i64(i8* %8, i8 0, i64 11104, i32 32, i1 false)
43 %b = getelementptr inbounds %struct.S2760* %arg0, i32 0, i32 1
44 %g = getelementptr inbounds %struct.anon* %b, i32 0, i32 1
45 %9 = load i64* %g, align 8
46 %10 = load i64* getelementptr inbounds (%struct.S2760* @s2760, i32 0, i32 1, i32 1), align 8
47 %cmp = icmp ne i64 %9, %10
48 br i1 %cmp, label %if.then, label %if.end
49
50 if.then: ; preds = %entry
51 %11 = load i32* @fails, align 4
52 %inc = add nsw i32 %11, 1
53 store i32 %inc, i32* @fails, align 4
54 br label %if.end
55
56 if.end: ; preds = %if.then, %entry
57 %12 = load i64* getelementptr inbounds (%struct.S2760* @s2760, i32 0, i32 1, i32 1), align 8
58 %b3 = getelementptr inbounds %struct.S2760* %ret, i32 0, i32 1
59 %g4 = getelementptr inbounds %struct.anon* %b3, i32 0, i32 1
60 store i64 %12, i64* %g4, align 8
61 %13 = bitcast %struct.S2760* %agg.result to i8*
62 %14 = bitcast %struct.S2760* %ret to i8*
63 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %13, i8* %14, i64 11104, i32 32, i1 false)
64 ret void
65 }
66
67 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1)
68
69 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
70