llvm.org GIT mirror llvm / edab757
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316479 91177308-0d34-0410-b5e6-96231b3b80d8 Justin Bogner 2 years ago
246 changed file(s) with 5712 addition(s) and 7247 deletion(s). Raw diff Collapse all Expand all
269269 OS << ')';
270270 }
271271
272 static void printRegClassOrBank(unsigned Reg, raw_ostream &OS,
273 const MachineRegisterInfo &RegInfo,
274 const TargetRegisterInfo *TRI) {
275 if (RegInfo.getRegClassOrNull(Reg))
276 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
277 else if (RegInfo.getRegBankOrNull(Reg))
278 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
279 else {
280 OS << "_";
281 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
282 "Generic registers must have a valid type");
283 }
284 }
285
286 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
287 const MachineRegisterInfo &RegInfo,
288 const TargetRegisterInfo *TRI) {
289 raw_string_ostream OS(Dest.Value);
290 printRegClassOrBank(Reg, OS, RegInfo, TRI);
291 }
292
293
272294 void MIRPrinter::convert(yaml::MachineFunction &MF,
273295 const MachineRegisterInfo &RegInfo,
274296 const TargetRegisterInfo *TRI) {
279301 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
280302 yaml::VirtualRegisterDefinition VReg;
281303 VReg.ID = I;
282 if (RegInfo.getRegClassOrNull(Reg))
283 VReg.Class =
284 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
285 else if (RegInfo.getRegBankOrNull(Reg))
286 VReg.Class = StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
287 else {
288 VReg.Class = std::string("_");
289 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
290 "Generic registers must have a valid type");
291 }
304 printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
292305 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
293306 if (PreferredReg)
294307 printReg(PreferredReg, VReg.PreferredRegister, TRI);
914927 bool IsDef) {
915928 printTargetFlags(Op);
916929 switch (Op.getType()) {
917 case MachineOperand::MO_Register:
930 case MachineOperand::MO_Register: {
931 unsigned Reg = Op.getReg();
918932 if (Op.isImplicit())
919933 OS << (Op.isDef() ? "implicit-def " : "implicit ");
920934 else if (!IsDef && Op.isDef())
932946 OS << "early-clobber ";
933947 if (Op.isDebug())
934948 OS << "debug-use ";
935 printReg(Op.getReg(), OS, TRI);
949 printReg(Reg, OS, TRI);
936950 // Print the sub register.
937951 if (Op.getSubReg() != 0)
938952 OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
953 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
954 const MachineRegisterInfo &MRI = Op.getParent()->getMF()->getRegInfo();
955 if (IsDef || MRI.def_empty(Reg)) {
956 OS << ':';
957 printRegClassOrBank(Reg, OS, MRI, TRI);
958 }
959 }
939960 if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
940961 OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
941962 if (TypeToPrint.isValid())
942963 OS << '(' << TypeToPrint << ')';
943964 break;
965 }
944966 case MachineOperand::MO_Immediate:
945967 OS << Op.getImm();
946968 break;
33 target triple = "aarch64-apple-ios9.0"
44
55 ; CHECK-LABEL: name: test_varargs
6 ; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
7 ; CHECK: [[D_ONE:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00
8 ; CHECK: [[TWELVE:%[0-9]+]](s64) = G_CONSTANT i64 12
9 ; CHECK: [[THREE:%[0-9]+]](s8) = G_CONSTANT i8 3
10 ; CHECK: [[ONE:%[0-9]+]](s16) = G_CONSTANT i16 1
11 ; CHECK: [[FOUR:%[0-9]+]](s32) = G_CONSTANT i32 4
12 ; CHECK: [[F_ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
13 ; CHECK: [[TWO:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
6 ; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
7 ; CHECK: [[D_ONE:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
8 ; CHECK: [[TWELVE:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
9 ; CHECK: [[THREE:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
10 ; CHECK: [[ONE:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
11 ; CHECK: [[FOUR:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
12 ; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
13 ; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
1414
1515 ; CHECK: %w0 = COPY [[ANSWER]]
1616 ; CHECK: %d0 = COPY [[D_ONE]]
33 target triple = "aarch64-linux-gnu"
44
55 ; CHECK-LABEL: name: args_i32
6 ; CHECK: %[[ARG0:[0-9]+]](s32) = COPY %w0
7 ; CHECK: %{{[0-9]+}}(s32) = COPY %w1
8 ; CHECK: %{{[0-9]+}}(s32) = COPY %w2
9 ; CHECK: %{{[0-9]+}}(s32) = COPY %w3
10 ; CHECK: %{{[0-9]+}}(s32) = COPY %w4
11 ; CHECK: %{{[0-9]+}}(s32) = COPY %w5
12 ; CHECK: %{{[0-9]+}}(s32) = COPY %w6
13 ; CHECK: %{{[0-9]+}}(s32) = COPY %w7
6 ; CHECK: %[[ARG0:[0-9]+]]:_(s32) = COPY %w0
7 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w1
8 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w2
9 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w3
10 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w4
11 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w5
12 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w6
13 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w7
1414 ; CHECK: %w0 = COPY %[[ARG0]]
1515
1616 define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
1919 }
2020
2121 ; CHECK-LABEL: name: args_i64
22 ; CHECK: %[[ARG0:[0-9]+]](s64) = COPY %x0
23 ; CHECK: %{{[0-9]+}}(s64) = COPY %x1
24 ; CHECK: %{{[0-9]+}}(s64) = COPY %x2
25 ; CHECK: %{{[0-9]+}}(s64) = COPY %x3
26 ; CHECK: %{{[0-9]+}}(s64) = COPY %x4
27 ; CHECK: %{{[0-9]+}}(s64) = COPY %x5
28 ; CHECK: %{{[0-9]+}}(s64) = COPY %x6
29 ; CHECK: %{{[0-9]+}}(s64) = COPY %x7
22 ; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %x0
23 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x1
24 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x2
25 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x3
26 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x4
27 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x5
28 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x6
29 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x7
3030 ; CHECK: %x0 = COPY %[[ARG0]]
3131 define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
3232 i64 %x4, i64 %x5, i64 %x6, i64 %x7) {
3535
3636
3737 ; CHECK-LABEL: name: args_ptrs
38 ; CHECK: %[[ARG0:[0-9]+]](p0) = COPY %x0
39 ; CHECK: %{{[0-9]+}}(p0) = COPY %x1
40 ; CHECK: %{{[0-9]+}}(p0) = COPY %x2
41 ; CHECK: %{{[0-9]+}}(p0) = COPY %x3
42 ; CHECK: %{{[0-9]+}}(p0) = COPY %x4
43 ; CHECK: %{{[0-9]+}}(p0) = COPY %x5
44 ; CHECK: %{{[0-9]+}}(p0) = COPY %x6
45 ; CHECK: %{{[0-9]+}}(p0) = COPY %x7
38 ; CHECK: %[[ARG0:[0-9]+]]:_(p0) = COPY %x0
39 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x1
40 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x2
41 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x3
42 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x4
43 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x5
44 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x6
45 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x7
4646 ; CHECK: %x0 = COPY %[[ARG0]]
4747 define i8* @args_ptrs(i8* %x0, i16* %x1, <2 x i8>* %x2, {i8, i16, i32}* %x3,
4848 [3 x float]* %x4, double* %x5, i8* %x6, i8* %x7) {
5050 }
5151
5252 ; CHECK-LABEL: name: args_arr
53 ; CHECK: %[[ARG0:[0-9]+]](s64) = COPY %d0
53 ; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %d0
5454 ; CHECK: %d0 = COPY %[[ARG0]]
5555 define [1 x double] @args_arr([1 x double] %d0) {
5656 ret [1 x double] %d0
5757 }
5858
5959 ; CHECK-LABEL: name: test_varargs
60 ; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
61 ; CHECK: [[D_ONE:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00
62 ; CHECK: [[TWELVE:%[0-9]+]](s64) = G_CONSTANT i64 12
63 ; CHECK: [[THREE:%[0-9]+]](s8) = G_CONSTANT i8 3
64 ; CHECK: [[ONE:%[0-9]+]](s16) = G_CONSTANT i16 1
65 ; CHECK: [[FOUR:%[0-9]+]](s32) = G_CONSTANT i32 4
66 ; CHECK: [[F_ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
67 ; CHECK: [[TWO:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
60 ; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
61 ; CHECK: [[D_ONE:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
62 ; CHECK: [[TWELVE:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
63 ; CHECK: [[THREE:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
64 ; CHECK: [[ONE:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
65 ; CHECK: [[FOUR:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
66 ; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
67 ; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
6868
6969 ; CHECK: %w0 = COPY [[ANSWER]]
7070 ; CHECK: %d0 = COPY [[D_ONE]]
7171 ; CHECK: %x1 = COPY [[TWELVE]]
72 ; CHECK: [[THREE_TMP:%[0-9]+]](s32) = G_ANYEXT [[THREE]]
72 ; CHECK: [[THREE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[THREE]]
7373 ; CHECK: %w2 = COPY [[THREE_TMP]](s32)
74 ; CHECK: [[ONE_TMP:%[0-9]+]](s32) = G_ANYEXT [[ONE]]
74 ; CHECK: [[ONE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[ONE]]
7575 ; CHECK: %w3 = COPY [[ONE_TMP]](s32)
7676 ; CHECK: %w4 = COPY [[FOUR]](s32)
7777 ; CHECK: %s1 = COPY [[F_ONE]](s32)
66 ; CHECK: - { id: 0, name: StackGuardSlot, type: default, offset: 0, size: 8, alignment: 8,
77 ; CHECK-NOT: id: 1
88
9 ; CHECK: [[GUARD_SLOT:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
10 ; CHECK: [[GUARD:%[0-9]+]](p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
9 ; CHECK: [[GUARD_SLOT:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
10 ; CHECK: [[GUARD:%[0-9]+]]:gpr64sp(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
1111 ; CHECK: G_STORE [[GUARD]](p0), [[GUARD_SLOT]](p0) :: (volatile store 8 into %stack.0.StackGuardSlot)
1212 declare void @llvm.stackprotector(i8*, i8**)
1313 define void @test_stack_guard_remat2() {
66
77 ; Tests for add.
88 ; CHECK-LABEL: name: addi64
9 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
10 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
11 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_ADD [[ARG1]], [[ARG2]]
9 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
10 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
11 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_ADD [[ARG1]], [[ARG2]]
1212 ; CHECK-NEXT: %x0 = COPY [[RES]]
1313 ; CHECK-NEXT: RET_ReallyLR implicit %x0
1414 define i64 @addi64(i64 %arg1, i64 %arg2) {
1717 }
1818
1919 ; CHECK-LABEL: name: muli64
20 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
21 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
22 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_MUL [[ARG1]], [[ARG2]]
20 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
21 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
22 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_MUL [[ARG1]], [[ARG2]]
2323 ; CHECK-NEXT: %x0 = COPY [[RES]]
2424 ; CHECK-NEXT: RET_ReallyLR implicit %x0
2525 define i64 @muli64(i64 %arg1, i64 %arg2) {
4040 ; CHECK-NEXT: stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
4141 ; CHECK-NEXT: di-variable: '', di-expression: '', di-location: '' }
4242 ; CHECK-NEXT: - { id: 3, name: ptr4, type: default, offset: 0, size: 1, alignment: 8,
43 ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.0.ptr1
44 ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.1.ptr2
45 ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.2.ptr3
46 ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.3.ptr4
43 ; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.0.ptr1
44 ; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.1.ptr2
45 ; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.2.ptr3
46 ; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.3.ptr4
4747 define void @allocai64() {
4848 %ptr1 = alloca i64
4949 %ptr2 = alloca i64, align 1
106106 ; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+.true]](0x40000000),
107107 ; CHECK: %[[FALSE:bb.[0-9]+.false]](0x40000000)
108108 ;
109 ; CHECK: [[ADDR:%.*]](p0) = COPY %x0
109 ; CHECK: [[ADDR:%.*]]:_(p0) = COPY %x0
110110 ;
111111 ; Check that we emit the correct branch.
112 ; CHECK: [[TST:%.*]](s1) = G_LOAD [[ADDR]](p0)
112 ; CHECK: [[TST:%.*]]:_(s1) = G_LOAD [[ADDR]](p0)
113113 ; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]]
114114 ; CHECK: G_BR %[[FALSE]]
115115 ;
134134 ;
135135 ; CHECK: {{bb.[0-9]+.entry}}:
136136 ; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+.case100]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
137 ; CHECK: %0(s32) = COPY %w0
138 ; CHECK: %[[reg100:[0-9]+]](s32) = G_CONSTANT i32 100
139 ; CHECK: %[[reg200:[0-9]+]](s32) = G_CONSTANT i32 200
140 ; CHECK: %[[reg0:[0-9]+]](s32) = G_CONSTANT i32 0
141 ; CHECK: %[[reg1:[0-9]+]](s32) = G_CONSTANT i32 1
142 ; CHECK: %[[reg2:[0-9]+]](s32) = G_CONSTANT i32 2
143 ; CHECK: %[[regicmp100:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg100]](s32), %0
137 ; CHECK: %0:_(s32) = COPY %w0
138 ; CHECK: %[[reg100:[0-9]+]]:_(s32) = G_CONSTANT i32 100
139 ; CHECK: %[[reg200:[0-9]+]]:_(s32) = G_CONSTANT i32 200
140 ; CHECK: %[[reg0:[0-9]+]]:_(s32) = G_CONSTANT i32 0
141 ; CHECK: %[[reg1:[0-9]+]]:_(s32) = G_CONSTANT i32 1
142 ; CHECK: %[[reg2:[0-9]+]]:_(s32) = G_CONSTANT i32 2
143 ; CHECK: %[[regicmp100:[0-9]+]]:_(s1) = G_ICMP intpred(eq), %[[reg100]](s32), %0
144144 ; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]]
145145 ; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]]
146146 ;
147147 ; CHECK: [[BB_NOTCASE100_CHECKNEXT]]:
148148 ; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+.case200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
149 ; CHECK: %[[regicmp200:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
149 ; CHECK: %[[regicmp200:[0-9]+]]:_(s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
150150 ; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]]
151151 ; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]]
152152 ;
156156 ;
157157 ; CHECK: [[BB_DEFAULT]]:
158158 ; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
159 ; CHECK: %[[regretdefault:[0-9]+]](s32) = G_ADD %0, %[[reg0]]
159 ; CHECK: %[[regretdefault:[0-9]+]]:_(s32) = G_ADD %0, %[[reg0]]
160160 ; CHECK: G_BR %[[BB_RET]]
161161 ;
162162 ; CHECK: [[BB_CASE100]]:
163163 ; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
164 ; CHECK: %[[regretc100:[0-9]+]](s32) = G_ADD %0, %[[reg1]]
164 ; CHECK: %[[regretc100:[0-9]+]]:_(s32) = G_ADD %0, %[[reg1]]
165165 ; CHECK: G_BR %[[BB_RET]]
166166 ;
167167 ; CHECK: [[BB_CASE200]]:
168168 ; CHECK-NEXT: successors: %[[BB_RET]](0x80000000)
169 ; CHECK: %[[regretc200:[0-9]+]](s32) = G_ADD %0, %[[reg2]]
169 ; CHECK: %[[regretc200:[0-9]+]]:_(s32) = G_ADD %0, %[[reg2]]
170170 ;
171171 ; CHECK: [[BB_RET]]:
172 ; CHECK-NEXT: %[[regret:[0-9]+]](s32) = G_PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]]
172 ; CHECK-NEXT: %[[regret:[0-9]+]]:_(s32) = G_PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]]
173173 ; CHECK: %w0 = COPY %[[regret]](s32)
174174 ; CHECK: RET_ReallyLR implicit %w0
175175 ;
288288
289289 ; Tests for or.
290290 ; CHECK-LABEL: name: ori64
291 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
292 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
293 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_OR [[ARG1]], [[ARG2]]
291 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
292 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
293 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_OR [[ARG1]], [[ARG2]]
294294 ; CHECK-NEXT: %x0 = COPY [[RES]]
295295 ; CHECK-NEXT: RET_ReallyLR implicit %x0
296296 define i64 @ori64(i64 %arg1, i64 %arg2) {
299299 }
300300
301301 ; CHECK-LABEL: name: ori32
302 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
303 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
304 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_OR [[ARG1]], [[ARG2]]
302 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
303 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
304 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_OR [[ARG1]], [[ARG2]]
305305 ; CHECK-NEXT: %w0 = COPY [[RES]]
306306 ; CHECK-NEXT: RET_ReallyLR implicit %w0
307307 define i32 @ori32(i32 %arg1, i32 %arg2) {
311311
312312 ; Tests for xor.
313313 ; CHECK-LABEL: name: xori64
314 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
315 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
316 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_XOR [[ARG1]], [[ARG2]]
314 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
315 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
316 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_XOR [[ARG1]], [[ARG2]]
317317 ; CHECK-NEXT: %x0 = COPY [[RES]]
318318 ; CHECK-NEXT: RET_ReallyLR implicit %x0
319319 define i64 @xori64(i64 %arg1, i64 %arg2) {
322322 }
323323
324324 ; CHECK-LABEL: name: xori32
325 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
326 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
327 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_XOR [[ARG1]], [[ARG2]]
325 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
326 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
327 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_XOR [[ARG1]], [[ARG2]]
328328 ; CHECK-NEXT: %w0 = COPY [[RES]]
329329 ; CHECK-NEXT: RET_ReallyLR implicit %w0
330330 define i32 @xori32(i32 %arg1, i32 %arg2) {
334334
335335 ; Tests for and.
336336 ; CHECK-LABEL: name: andi64
337 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
338 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
339 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_AND [[ARG1]], [[ARG2]]
337 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
338 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
339 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_AND [[ARG1]], [[ARG2]]
340340 ; CHECK-NEXT: %x0 = COPY [[RES]]
341341 ; CHECK-NEXT: RET_ReallyLR implicit %x0
342342 define i64 @andi64(i64 %arg1, i64 %arg2) {
345345 }
346346
347347 ; CHECK-LABEL: name: andi32
348 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
349 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
350 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_AND [[ARG1]], [[ARG2]]
348 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
349 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
350 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_AND [[ARG1]], [[ARG2]]
351351 ; CHECK-NEXT: %w0 = COPY [[RES]]
352352 ; CHECK-NEXT: RET_ReallyLR implicit %w0
353353 define i32 @andi32(i32 %arg1, i32 %arg2) {
357357
358358 ; Tests for sub.
359359 ; CHECK-LABEL: name: subi64
360 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
361 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
362 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_SUB [[ARG1]], [[ARG2]]
360 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
361 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
362 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_SUB [[ARG1]], [[ARG2]]
363363 ; CHECK-NEXT: %x0 = COPY [[RES]]
364364 ; CHECK-NEXT: RET_ReallyLR implicit %x0
365365 define i64 @subi64(i64 %arg1, i64 %arg2) {
368368 }
369369
370370 ; CHECK-LABEL: name: subi32
371 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
372 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
373 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SUB [[ARG1]], [[ARG2]]
371 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
372 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
373 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SUB [[ARG1]], [[ARG2]]
374374 ; CHECK-NEXT: %w0 = COPY [[RES]]
375375 ; CHECK-NEXT: RET_ReallyLR implicit %w0
376376 define i32 @subi32(i32 %arg1, i32 %arg2) {
379379 }
380380
381381 ; CHECK-LABEL: name: ptrtoint
382 ; CHECK: [[ARG1:%[0-9]+]](p0) = COPY %x0
383 ; CHECK: [[RES:%[0-9]+]](s64) = G_PTRTOINT [[ARG1]]
382 ; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY %x0
383 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[ARG1]]
384384 ; CHECK: %x0 = COPY [[RES]]
385385 ; CHECK: RET_ReallyLR implicit %x0
386386 define i64 @ptrtoint(i64* %a) {
389389 }
390390
391391 ; CHECK-LABEL: name: inttoptr
392 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
393 ; CHECK: [[RES:%[0-9]+]](p0) = G_INTTOPTR [[ARG1]]
392 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
393 ; CHECK: [[RES:%[0-9]+]]:_(p0) = G_INTTOPTR [[ARG1]]
394394 ; CHECK: %x0 = COPY [[RES]]
395395 ; CHECK: RET_ReallyLR implicit %x0
396396 define i64* @inttoptr(i64 %a) {
399399 }
400400
401401 ; CHECK-LABEL: name: trivial_bitcast
402 ; CHECK: [[ARG1:%[0-9]+]](p0) = COPY %x0
402 ; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY %x0
403403 ; CHECK: %x0 = COPY [[ARG1]]
404404 ; CHECK: RET_ReallyLR implicit %x0
405405 define i64* @trivial_bitcast(i8* %a) {
408408 }
409409
410410 ; CHECK-LABEL: name: trivial_bitcast_with_copy
411 ; CHECK: [[A:%[0-9]+]](p0) = COPY %x0
411 ; CHECK: [[A:%[0-9]+]]:_(p0) = COPY %x0
412412 ; CHECK: G_BR %[[CAST:bb\.[0-9]+.cast]]
413413
414414 ; CHECK: [[END:bb\.[0-9]+.end]]:
415415
416416 ; CHECK: [[CAST]]:
417 ; CHECK: {{%[0-9]+}}(p0) = COPY [[A]]
417 ; CHECK: {{%[0-9]+}}:_(p0) = COPY [[A]]
418418 ; CHECK: G_BR %[[END]]
419419 define i64* @trivial_bitcast_with_copy(i8* %a) {
420420 br label %cast
428428 }
429429
430430 ; CHECK-LABEL: name: bitcast
431 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
432 ; CHECK: [[RES1:%[0-9]+]](<2 x s32>) = G_BITCAST [[ARG1]]
433 ; CHECK: [[RES2:%[0-9]+]](s64) = G_BITCAST [[RES1]]
431 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
432 ; CHECK: [[RES1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[ARG1]]
433 ; CHECK: [[RES2:%[0-9]+]]:_(s64) = G_BITCAST [[RES1]]
434434 ; CHECK: %x0 = COPY [[RES2]]
435435 ; CHECK: RET_ReallyLR implicit %x0
436436 define i64 @bitcast(i64 %a) {
440440 }
441441
442442 ; CHECK-LABEL: name: trunc
443 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
444 ; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_LOAD
445 ; CHECK: [[RES1:%[0-9]+]](s8) = G_TRUNC [[ARG1]]
446 ; CHECK: [[RES2:%[0-9]+]](<4 x s16>) = G_TRUNC [[VEC]]
443 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
444 ; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_LOAD
445 ; CHECK: [[RES1:%[0-9]+]]:_(s8) = G_TRUNC [[ARG1]]
446 ; CHECK: [[RES2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[VEC]]
447447 define void @trunc(i64 %a) {
448448 %vecptr = alloca <4 x i32>
449449 %vec = load <4 x i32>, <4 x i32>* %vecptr
453453 }
454454
455455 ; CHECK-LABEL: name: load
456 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
457 ; CHECK: [[ADDR42:%[0-9]+]](p42) = COPY %x1
458 ; CHECK: [[VAL1:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 16)
459 ; CHECK: [[VAL2:%[0-9]+]](s64) = G_LOAD [[ADDR42]](p42) :: (load 8 from %ir.addr42)
460 ; CHECK: [[SUM2:%.*]](s64) = G_ADD [[VAL1]], [[VAL2]]
461 ; CHECK: [[VAL3:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (volatile load 8 from %ir.addr)
462 ; CHECK: [[SUM3:%[0-9]+]](s64) = G_ADD [[SUM2]], [[VAL3]]
456 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
457 ; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY %x1
458 ; CHECK: [[VAL1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 16)
459 ; CHECK: [[VAL2:%[0-9]+]]:_(s64) = G_LOAD [[ADDR42]](p42) :: (load 8 from %ir.addr42)
460 ; CHECK: [[SUM2:%.*]]:_(s64) = G_ADD [[VAL1]], [[VAL2]]
461 ; CHECK: [[VAL3:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (volatile load 8 from %ir.addr)
462 ; CHECK: [[SUM3:%[0-9]+]]:_(s64) = G_ADD [[SUM2]], [[VAL3]]
463463 ; CHECK: %x0 = COPY [[SUM3]]
464464 ; CHECK: RET_ReallyLR implicit %x0
465465 define i64 @load(i64* %addr, i64 addrspace(42)* %addr42) {
474474 }
475475
476476 ; CHECK-LABEL: name: store
477 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
478 ; CHECK: [[ADDR42:%[0-9]+]](p42) = COPY %x1
479 ; CHECK: [[VAL1:%[0-9]+]](s64) = COPY %x2
480 ; CHECK: [[VAL2:%[0-9]+]](s64) = COPY %x3
477 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
478 ; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY %x1
479 ; CHECK: [[VAL1:%[0-9]+]]:_(s64) = COPY %x2
480 ; CHECK: [[VAL2:%[0-9]+]]:_(s64) = COPY %x3
481481 ; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr, align 16)
482482 ; CHECK: G_STORE [[VAL2]](s64), [[ADDR42]](p42) :: (store 8 into %ir.addr42)
483483 ; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (volatile store 8 into %ir.addr)
491491 }
492492
493493 ; CHECK-LABEL: name: intrinsics
494 ; CHECK: [[CUR:%[0-9]+]](s32) = COPY %w0
495 ; CHECK: [[BITS:%[0-9]+]](s32) = COPY %w1
496 ; CHECK: [[CREG:%[0-9]+]](s32) = G_CONSTANT i32 0
497 ; CHECK: [[PTR:%[0-9]+]](p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), [[CREG]]
498 ; CHECK: [[PTR_VEC:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.ptr.vec
499 ; CHECK: [[VEC:%[0-9]+]](<8 x s8>) = G_LOAD [[PTR_VEC]]
494 ; CHECK: [[CUR:%[0-9]+]]:_(s32) = COPY %w0
495 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = COPY %w1
496 ; CHECK: [[CREG:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
497 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), [[CREG]]
498 ; CHECK: [[PTR_VEC:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr.vec
499 ; CHECK: [[VEC:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[PTR_VEC]]
500500 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), [[VEC]](<8 x s8>), [[VEC]](<8 x s8>), [[PTR]](p0)
501501 ; CHECK: RET_ReallyLR
502502 declare i8* @llvm.returnaddress(i32)
515515 ; CHECK: G_BR %[[FALSE:bb\.[0-9]+.false]]
516516
517517 ; CHECK: [[TRUE]]:
518 ; CHECK: [[RES1:%[0-9]+]](s32) = G_LOAD
518 ; CHECK: [[RES1:%[0-9]+]]:_(s32) = G_LOAD
519519
520520 ; CHECK: [[FALSE]]:
521 ; CHECK: [[RES2:%[0-9]+]](s32) = G_LOAD
522
523 ; CHECK: [[RES:%[0-9]+]](s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
521 ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_LOAD
522
523 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
524524 ; CHECK: %w0 = COPY [[RES]]
525525 define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) {
526526 br i1 %tst, label %true, label %false
550550 ; It's important that constants are after argument passing, but before the
551551 ; rest of the entry block.
552552 ; CHECK-LABEL: name: constant_int
553 ; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
554 ; CHECK: [[ONE:%[0-9]+]](s32) = G_CONSTANT i32 1
553 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
554 ; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
555555
556556 ; CHECK: {{bb.[0-9]+}}.next:
557 ; CHECK: [[SUM1:%[0-9]+]](s32) = G_ADD [[IN]], [[ONE]]
558 ; CHECK: [[SUM2:%[0-9]+]](s32) = G_ADD [[IN]], [[ONE]]
559 ; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[SUM1]], [[SUM2]]
557 ; CHECK: [[SUM1:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
558 ; CHECK: [[SUM2:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
559 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[SUM1]], [[SUM2]]
560560 ; CHECK: %w0 = COPY [[RES]]
561561
562562 define i32 @constant_int(i32 %in) {
570570 }
571571
572572 ; CHECK-LABEL: name: constant_int_start
573 ; CHECK: [[TWO:%[0-9]+]](s32) = G_CONSTANT i32 2
574 ; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
575 ; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[TWO]], [[ANSWER]]
573 ; CHECK: [[TWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
574 ; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
575 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[TWO]], [[ANSWER]]
576576 define i32 @constant_int_start() {
577577 %res = add i32 2, 42
578578 ret i32 %res
579579 }
580580
581581 ; CHECK-LABEL: name: test_undef
582 ; CHECK: [[UNDEF:%[0-9]+]](s32) = G_IMPLICIT_DEF
582 ; CHECK: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
583583 ; CHECK: %w0 = COPY [[UNDEF]]
584584 define i32 @test_undef() {
585585 ret i32 undef
586586 }
587587
588588 ; CHECK-LABEL: name: test_constant_inttoptr
589 ; CHECK: [[ONE:%[0-9]+]](s64) = G_CONSTANT i64 1
590 ; CHECK: [[PTR:%[0-9]+]](p0) = G_INTTOPTR [[ONE]]
589 ; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
590 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ONE]]
591591 ; CHECK: %x0 = COPY [[PTR]]
592592 define i8* @test_constant_inttoptr() {
593593 ret i8* inttoptr(i64 1 to i8*)
596596 ; This failed purely because the Constant -> VReg map was kept across
597597 ; functions, so reuse the "i64 1" from above.
598598 ; CHECK-LABEL: name: test_reused_constant
599 ; CHECK: [[ONE:%[0-9]+]](s64) = G_CONSTANT i64 1
599 ; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
600600 ; CHECK: %x0 = COPY [[ONE]]
601601 define i64 @test_reused_constant() {
602602 ret i64 1
603603 }
604604
605605 ; CHECK-LABEL: name: test_sext
606 ; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
607 ; CHECK: [[RES:%[0-9]+]](s64) = G_SEXT [[IN]]
606 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
607 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_SEXT [[IN]]
608608 ; CHECK: %x0 = COPY [[RES]]
609609 define i64 @test_sext(i32 %in) {
610610 %res = sext i32 %in to i64
612612 }
613613
614614 ; CHECK-LABEL: name: test_zext
615 ; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
616 ; CHECK: [[RES:%[0-9]+]](s64) = G_ZEXT [[IN]]
615 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
616 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ZEXT [[IN]]
617617 ; CHECK: %x0 = COPY [[RES]]
618618 define i64 @test_zext(i32 %in) {
619619 %res = zext i32 %in to i64
621621 }
622622
623623 ; CHECK-LABEL: name: test_shl
624 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
625 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
626 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SHL [[ARG1]], [[ARG2]]
624 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
625 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
626 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SHL [[ARG1]], [[ARG2]]
627627 ; CHECK-NEXT: %w0 = COPY [[RES]]
628628 ; CHECK-NEXT: RET_ReallyLR implicit %w0
629629 define i32 @test_shl(i32 %arg1, i32 %arg2) {
633633
634634
635635 ; CHECK-LABEL: name: test_lshr
636 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
637 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
638 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_LSHR [[ARG1]], [[ARG2]]
636 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
637 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
638 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_LSHR [[ARG1]], [[ARG2]]
639639 ; CHECK-NEXT: %w0 = COPY [[RES]]
640640 ; CHECK-NEXT: RET_ReallyLR implicit %w0
641641 define i32 @test_lshr(i32 %arg1, i32 %arg2) {
644644 }
645645
646646 ; CHECK-LABEL: name: test_ashr
647 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
648 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
649 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_ASHR [[ARG1]], [[ARG2]]
647 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
648 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
649 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_ASHR [[ARG1]], [[ARG2]]
650650 ; CHECK-NEXT: %w0 = COPY [[RES]]
651651 ; CHECK-NEXT: RET_ReallyLR implicit %w0
652652 define i32 @test_ashr(i32 %arg1, i32 %arg2) {
655655 }
656656
657657 ; CHECK-LABEL: name: test_sdiv
658 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
659 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
660 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SDIV [[ARG1]], [[ARG2]]
658 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
659 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
660 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SDIV [[ARG1]], [[ARG2]]
661661 ; CHECK-NEXT: %w0 = COPY [[RES]]
662662 ; CHECK-NEXT: RET_ReallyLR implicit %w0
663663 define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
666666 }
667667
668668 ; CHECK-LABEL: name: test_udiv
669 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
670 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
671 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UDIV [[ARG1]], [[ARG2]]
669 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
670 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
671 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UDIV [[ARG1]], [[ARG2]]
672672 ; CHECK-NEXT: %w0 = COPY [[RES]]
673673 ; CHECK-NEXT: RET_ReallyLR implicit %w0
674674 define i32 @test_udiv(i32 %arg1, i32 %arg2) {
677677 }
678678
679679 ; CHECK-LABEL: name: test_srem
680 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
681 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
682 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SREM [[ARG1]], [[ARG2]]
680 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
681 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
682 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SREM [[ARG1]], [[ARG2]]
683683 ; CHECK-NEXT: %w0 = COPY [[RES]]
684684 ; CHECK-NEXT: RET_ReallyLR implicit %w0
685685 define i32 @test_srem(i32 %arg1, i32 %arg2) {
688688 }
689689
690690 ; CHECK-LABEL: name: test_urem
691 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
692 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
693 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UREM [[ARG1]], [[ARG2]]
691 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
692 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
693 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UREM [[ARG1]], [[ARG2]]
694694 ; CHECK-NEXT: %w0 = COPY [[RES]]
695695 ; CHECK-NEXT: RET_ReallyLR implicit %w0
696696 define i32 @test_urem(i32 %arg1, i32 %arg2) {
699699 }
700700
701701 ; CHECK-LABEL: name: test_constant_null
702 ; CHECK: [[NULL:%[0-9]+]](p0) = G_CONSTANT i64 0
702 ; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
703703 ; CHECK: %x0 = COPY [[NULL]]
704704 define i8* @test_constant_null() {
705705 ret i8* null
706706 }
707707
708708 ; CHECK-LABEL: name: test_struct_memops
709 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
710 ; CHECK: [[VAL:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 4)
709 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
710 ; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 4)
711711 ; CHECK: G_STORE [[VAL]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr, align 4)
712712 define void @test_struct_memops({ i8, i32 }* %addr) {
713713 %val = load { i8, i32 }, { i8, i32 }* %addr
716716 }
717717
718718 ; CHECK-LABEL: name: test_i1_memops
719 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
720 ; CHECK: [[VAL:%[0-9]+]](s1) = G_LOAD [[ADDR]](p0) :: (load 1 from %ir.addr)
719 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
720 ; CHECK: [[VAL:%[0-9]+]]:_(s1) = G_LOAD [[ADDR]](p0) :: (load 1 from %ir.addr)
721721 ; CHECK: G_STORE [[VAL]](s1), [[ADDR]](p0) :: (store 1 into %ir.addr)
722722 define void @test_i1_memops(i1* %addr) {
723723 %val = load i1, i1* %addr
726726 }
727727
728728 ; CHECK-LABEL: name: int_comparison
729 ; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
730 ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
731 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
732 ; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]]
729 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
730 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
731 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
732 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]]
733733 ; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
734734 define void @int_comparison(i32 %a, i32 %b, i1* %addr) {
735735 %res = icmp ne i32 %a, %b
738738 }
739739
740740 ; CHECK-LABEL: name: ptr_comparison
741 ; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x0
742 ; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x1
743 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
744 ; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
741 ; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY %x0
742 ; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY %x1
743 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
744 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
745745 ; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
746746 define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
747747 %res = icmp eq i8* %a, %b
750750 }
751751
752752 ; CHECK-LABEL: name: test_fadd
753 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
754 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
755 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FADD [[ARG1]], [[ARG2]]
753 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
754 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
755 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FADD [[ARG1]], [[ARG2]]
756756 ; CHECK-NEXT: %s0 = COPY [[RES]]
757757 ; CHECK-NEXT: RET_ReallyLR implicit %s0
758758 define float @test_fadd(float %arg1, float %arg2) {
761761 }
762762
763763 ; CHECK-LABEL: name: test_fsub
764 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
765 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
766 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FSUB [[ARG1]], [[ARG2]]
764 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
765 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
766 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FSUB [[ARG1]], [[ARG2]]
767767 ; CHECK-NEXT: %s0 = COPY [[RES]]
768768 ; CHECK-NEXT: RET_ReallyLR implicit %s0
769769 define float @test_fsub(float %arg1, float %arg2) {
772772 }
773773
774774 ; CHECK-LABEL: name: test_fmul
775 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
776 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
777 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FMUL [[ARG1]], [[ARG2]]
775 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
776 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
777 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FMUL [[ARG1]], [[ARG2]]
778778 ; CHECK-NEXT: %s0 = COPY [[RES]]
779779 ; CHECK-NEXT: RET_ReallyLR implicit %s0
780780 define float @test_fmul(float %arg1, float %arg2) {
783783 }
784784
785785 ; CHECK-LABEL: name: test_fdiv
786 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
787 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
788 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FDIV [[ARG1]], [[ARG2]]
786 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
787 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
788 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FDIV [[ARG1]], [[ARG2]]
789789 ; CHECK-NEXT: %s0 = COPY [[RES]]
790790 ; CHECK-NEXT: RET_ReallyLR implicit %s0
791791 define float @test_fdiv(float %arg1, float %arg2) {
794794 }
795795
796796 ; CHECK-LABEL: name: test_frem
797 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
798 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
799 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FREM [[ARG1]], [[ARG2]]
797 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
798 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
799 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FREM [[ARG1]], [[ARG2]]
800800 ; CHECK-NEXT: %s0 = COPY [[RES]]
801801 ; CHECK-NEXT: RET_ReallyLR implicit %s0
802802 define float @test_frem(float %arg1, float %arg2) {
805805 }
806806
807807 ; CHECK-LABEL: name: test_sadd_overflow
808 ; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
809 ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
810 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
811 ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SADDO [[LHS]], [[RHS]]
812 ; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
813 ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
814 ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
808 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
809 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
810 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
811 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SADDO [[LHS]], [[RHS]]
812 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
813 ; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
814 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
815815 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
816816 declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
817817 define void @test_sadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
821821 }
822822
823823 ; CHECK-LABEL: name: test_uadd_overflow
824 ; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
825 ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
826 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
827 ; CHECK: [[ZERO:%[0-9]+]](s1) = G_CONSTANT i1 false
828 ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_UADDE [[LHS]], [[RHS]], [[ZERO]]
829 ; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
830 ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
831 ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
824 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
825 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
826 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
827 ; CHECK: [[ZERO:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
828 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UADDE [[LHS]], [[RHS]], [[ZERO]]
829 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
830 ; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
831 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
832832 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
833833 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
834834 define void @test_uadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
838838 }
839839
840840 ; CHECK-LABEL: name: test_ssub_overflow
841 ; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
842 ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
843 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
844 ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SSUBO [[LHS]], [[RHS]]
845 ; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
846 ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
847 ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
841 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
842 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
843 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
844 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SSUBO [[LHS]], [[RHS]]
845 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
846 ; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
847 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
848848 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
849849 declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32)
850850 define void @test_ssub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) {
854854 }
855855
856856 ; CHECK-LABEL: name: test_usub_overflow
857 ; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
858 ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
859 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
860 ; CHECK: [[ZERO:%[0-9]+]](s1) = G_CONSTANT i1 false
861 ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_USUBE [[LHS]], [[RHS]], [[ZERO]]
862 ; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
863 ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
864 ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
857 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
858 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
859 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
860 ; CHECK: [[ZERO:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
861 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_USUBE [[LHS]], [[RHS]], [[ZERO]]
862 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
863 ; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
864 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
865865 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
866866 declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32)
867867 define void @test_usub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) {
871871 }
872872
873873 ; CHECK-LABEL: name: test_smul_overflow
874 ; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
875 ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
876 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
877 ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SMULO [[LHS]], [[RHS]]
878 ; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
879 ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
880 ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
874 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
875 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
876 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
877 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SMULO [[LHS]], [[RHS]]
878 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
879 ; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
880 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
881881 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
882882 declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
883883 define void @test_smul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
887887 }
888888
889889 ; CHECK-LABEL: name: test_umul_overflow
890 ; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
891 ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
892 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
893 ; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_UMULO [[LHS]], [[RHS]]
894 ; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
895 ; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
896 ; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
890 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
891 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
892 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
893 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UMULO [[LHS]], [[RHS]]
894 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
895 ; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
896 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
897897 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
898898 declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
899899 define void @test_umul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
903903 }
904904
905905 ; CHECK-LABEL: name: test_extractvalue
906 ; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
907 ; CHECK: [[RES:%[0-9]+]](s32) = G_EXTRACT [[STRUCT]](s128), 64
906 ; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
907 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT [[STRUCT]](s128), 64
908908 ; CHECK: %w0 = COPY [[RES]]
909909 %struct.nested = type {i8, { i8, i32 }, i32}
910910 define i32 @test_extractvalue(%struct.nested* %addr) {
914914 }
915915
916916 ; CHECK-LABEL: name: test_extractvalue_agg
917 ; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
918 ; CHECK: [[RES:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 32
917 ; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
918 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 32
919919 ; CHECK: G_STORE [[RES]]
920920 define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
921921 %struct = load %struct.nested, %struct.nested* %addr
925925 }
926926
927927 ; CHECK-LABEL: name: test_insertvalue
928 ; CHECK: [[VAL:%[0-9]+]](s32) = COPY %w1
929 ; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
930 ; CHECK: [[NEWSTRUCT:%[0-9]+]](s128) = G_INSERT [[STRUCT]], [[VAL]](s32), 64
928 ; CHECK: [[VAL:%[0-9]+]]:_(s32) = COPY %w1
929 ; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
930 ; CHECK: [[NEWSTRUCT:%[0-9]+]]:_(s128) = G_INSERT [[STRUCT]], [[VAL]](s32), 64
931931 ; CHECK: G_STORE [[NEWSTRUCT]](s128),
932932 define void @test_insertvalue(%struct.nested* %addr, i32 %val) {
933933 %struct = load %struct.nested, %struct.nested* %addr
938938
939939 define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) {
940940 ; CHECK-LABEL: name: test_trivial_insert
941 ; CHECK: [[STRUCT:%[0-9]+]](s64) = COPY %x0
942 ; CHECK: [[VAL:%[0-9]+]](s64) = COPY %x1
943 ; CHECK: [[RES:%[0-9]+]](s64) = COPY [[VAL]](s64)
941 ; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY %x0
942 ; CHECK: [[VAL:%[0-9]+]]:_(s64) = COPY %x1
943 ; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY [[VAL]](s64)
944944 ; CHECK: %x0 = COPY [[RES]]
945945 %res = insertvalue [1 x i64] %s, i64 %val, 0
946946 ret [1 x i64] %res
948948
949949 define [1 x i8*] @test_trivial_insert_ptr([1 x i8*] %s, i8* %val) {
950950 ; CHECK-LABEL: name: test_trivial_insert_ptr
951 ; CHECK: [[STRUCT:%[0-9]+]](s64) = COPY %x0
952 ; CHECK: [[VAL:%[0-9]+]](p0) = COPY %x1
953 ; CHECK: [[RES:%[0-9]+]](s64) = G_PTRTOINT [[VAL]](p0)
951 ; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY %x0
952 ; CHECK: [[VAL:%[0-9]+]]:_(p0) = COPY %x1
953 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[VAL]](p0)
954954 ; CHECK: %x0 = COPY [[RES]]
955955 %res = insertvalue [1 x i8*] %s, i8* %val, 0
956956 ret [1 x i8*] %res
957957 }
958958
959959 ; CHECK-LABEL: name: test_insertvalue_agg
960 ; CHECK: [[SMALLSTRUCT:%[0-9]+]](s64) = G_LOAD
961 ; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
962 ; CHECK: [[RES:%[0-9]+]](s128) = G_INSERT [[STRUCT]], [[SMALLSTRUCT]](s64), 32
960 ; CHECK: [[SMALLSTRUCT:%[0-9]+]]:_(s64) = G_LOAD
961 ; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
962 ; CHECK: [[RES:%[0-9]+]]:_(s128) = G_INSERT [[STRUCT]], [[SMALLSTRUCT]](s64), 32
963963 ; CHECK: G_STORE [[RES]](s128)
964964 define void @test_insertvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
965965 %smallstruct = load {i8, i32}, {i8, i32}* %addr2
970970 }
971971
972972 ; CHECK-LABEL: name: test_select
973 ; CHECK: [[TST_C:%[0-9]+]](s32) = COPY %w0
974 ; CHECK: [[TST:%[0-9]+]](s1) = G_TRUNC [[TST_C]]
975 ; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w1
976 ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w2
977 ; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
973 ; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
974 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
975 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w1
976 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w2
977 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
978978 ; CHECK: %w0 = COPY [[RES]]
979979 define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {
980980 %res = select i1 %tst, i32 %lhs, i32 %rhs
982982 }
983983
984984 ; CHECK-LABEL: name: test_select_ptr
985 ; CHECK: [[TST_C:%[0-9]+]](s32) = COPY %w0
986 ; CHECK: [[TST:%[0-9]+]](s1) = G_TRUNC [[TST_C]]
987 ; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x1
988 ; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x2
989 ; CHECK: [[RES:%[0-9]+]](p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
985 ; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
986 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
987 ; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY %x1
988 ; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY %x2
989 ; CHECK: [[RES:%[0-9]+]]:_(p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
990990 ; CHECK: %x0 = COPY [[RES]]
991991 define i8* @test_select_ptr(i1 %tst, i8* %lhs, i8* %rhs) {
992992 %res = select i1 %tst, i8* %lhs, i8* %rhs
994994 }
995995
996996 ; CHECK-LABEL: name: test_select_vec
997 ; CHECK: [[TST_C:%[0-9]+]](s32) = COPY %w0
998 ; CHECK: [[TST:%[0-9]+]](s1) = G_TRUNC [[TST_C]]
999 ; CHECK: [[LHS:%[0-9]+]](<4 x s32>) = COPY %q0
1000 ; CHECK: [[RHS:%[0-9]+]](<4 x s32>) = COPY %q1
1001 ; CHECK: [[RES:%[0-9]+]](<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
997 ; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
998 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
999 ; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY %q0
1000 ; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY %q1
1001 ; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
10021002 ; CHECK: %q0 = COPY [[RES]]
10031003 define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
10041004 %res = select i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs
10061006 }
10071007
10081008 ; CHECK-LABEL: name: test_vselect_vec
1009 ; CHECK: [[TST32:%[0-9]+]](<4 x s32>) = COPY %q0
1010 ; CHECK: [[LHS:%[0-9]+]](<4 x s32>) = COPY %q1
1011 ; CHECK: [[RHS:%[0-9]+]](<4 x s32>) = COPY %q2
1012 ; CHECK: [[TST:%[0-9]+]](<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>)
1013 ; CHECK: [[RES:%[0-9]+]](<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]]
1009 ; CHECK: [[TST32:%[0-9]+]]:_(<4 x s32>) = COPY %q0
1010 ; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY %q1
1011 ; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY %q2
1012 ; CHECK: [[TST:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>)
1013 ; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]]
10141014 ; CHECK: %q0 = COPY [[RES]]
10151015 define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %rhs) {
10161016 %tst = trunc <4 x i32> %tst32 to <4 x i1>
10191019 }
10201020
10211021 ; CHECK-LABEL: name: test_fptosi
1022 ; CHECK: [[FPADDR:%[0-9]+]](p0) = COPY %x0
1023 ; CHECK: [[FP:%[0-9]+]](s32) = G_LOAD [[FPADDR]](p0)
1024 ; CHECK: [[RES:%[0-9]+]](s64) = G_FPTOSI [[FP]](s32)
1022 ; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY %x0
1023 ; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
1024 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOSI [[FP]](s32)
10251025 ; CHECK: %x0 = COPY [[RES]]
10261026 define i64 @test_fptosi(float* %fp.addr) {
10271027 %fp = load float, float* %fp.addr
10301030 }
10311031
10321032 ; CHECK-LABEL: name: test_fptoui
1033 ; CHECK: [[FPADDR:%[0-9]+]](p0) = COPY %x0
1034 ; CHECK: [[FP:%[0-9]+]](s32) = G_LOAD [[FPADDR]](p0)
1035 ; CHECK: [[RES:%[0-9]+]](s64) = G_FPTOUI [[FP]](s32)
1033 ; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY %x0
1034 ; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
1035 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOUI [[FP]](s32)
10361036 ; CHECK: %x0 = COPY [[RES]]
10371037 define i64 @test_fptoui(float* %fp.addr) {
10381038 %fp = load float, float* %fp.addr
10411041 }
10421042
10431043 ; CHECK-LABEL: name: test_sitofp
1044 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
1045 ; CHECK: [[IN:%[0-9]+]](s32) = COPY %w1
1046 ; CHECK: [[FP:%[0-9]+]](s64) = G_SITOFP [[IN]](s32)
1044 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1045 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w1
1046 ; CHECK: [[FP:%[0-9]+]]:_(s64) = G_SITOFP [[IN]](s32)
10471047 ; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
10481048 define void @test_sitofp(double* %addr, i32 %in) {
10491049 %fp = sitofp i32 %in to double
10521052 }
10531053
10541054 ; CHECK-LABEL: name: test_uitofp
1055 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
1056 ; CHECK: [[IN:%[0-9]+]](s32) = COPY %w1
1057 ; CHECK: [[FP:%[0-9]+]](s64) = G_UITOFP [[IN]](s32)
1055 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1056 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w1
1057 ; CHECK: [[FP:%[0-9]+]]:_(s64) = G_UITOFP [[IN]](s32)
10581058 ; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
10591059 define void @test_uitofp(double* %addr, i32 %in) {
10601060 %fp = uitofp i32 %in to double
10631063 }
10641064
10651065 ; CHECK-LABEL: name: test_fpext
1066 ; CHECK: [[IN:%[0-9]+]](s32) = COPY %s0
1067 ; CHECK: [[RES:%[0-9]+]](s64) = G_FPEXT [[IN]](s32)
1066 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %s0
1067 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPEXT [[IN]](s32)
10681068 ; CHECK: %d0 = COPY [[RES]]
10691069 define double @test_fpext(float %in) {
10701070 %res = fpext float %in to double
10721072 }
10731073
10741074 ; CHECK-LABEL: name: test_fptrunc
1075 ; CHECK: [[IN:%[0-9]+]](s64) = COPY %d0
1076 ; CHECK: [[RES:%[0-9]+]](s32) = G_FPTRUNC [[IN]](s64)
1075 ; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %d0
1076 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPTRUNC [[IN]](s64)
10771077 ; CHECK: %s0 = COPY [[RES]]
10781078 define float @test_fptrunc(double %in) {
10791079 %res = fptrunc double %in to float
10811081 }
10821082
10831083 ; CHECK-LABEL: name: test_constant_float
1084 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
1085 ; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT float 1.500000e+00
1084 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1085 ; CHECK: [[TMP:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+00
10861086 ; CHECK: G_STORE [[TMP]](s32), [[ADDR]](p0)
10871087 define void @test_constant_float(float* %addr) {
10881088 store float 1.5, float* %addr
10901090 }
10911091
10921092 ; CHECK-LABEL: name: float_comparison
1093 ; CHECK: [[LHSADDR:%[0-9]+]](p0) = COPY %x0
1094 ; CHECK: [[RHSADDR:%[0-9]+]](p0) = COPY %x1
1095 ; CHECK: [[BOOLADDR:%[0-9]+]](p0) = COPY %x2
1096 ; CHECK: [[LHS:%[0-9]+]](s32) = G_LOAD [[LHSADDR]](p0)
1097 ; CHECK: [[RHS:%[0-9]+]](s32) = G_LOAD [[RHSADDR]](p0)
1098 ; CHECK: [[TST:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
1093 ; CHECK: [[LHSADDR:%[0-9]+]]:_(p0) = COPY %x0
1094 ; CHECK: [[RHSADDR:%[0-9]+]]:_(p0) = COPY %x1
1095 ; CHECK: [[BOOLADDR:%[0-9]+]]:_(p0) = COPY %x2
1096 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_LOAD [[LHSADDR]](p0)
1097 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_LOAD [[RHSADDR]](p0)
1098 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
10991099 ; CHECK: G_STORE [[TST]](s1), [[BOOLADDR]](p0)
11001100 define void @float_comparison(float* %a.addr, float* %b.addr, i1* %bool.addr) {
11011101 %a = load float, float* %a.addr
11061106 }
11071107
11081108 ; CHECK-LABEL: name: trivial_float_comparison
1109 ; CHECK: [[ENTRY_R1:%[0-9]+]](s1) = G_CONSTANT i1 false
1110 ; CHECK: [[ENTRY_R2:%[0-9]+]](s1) = G_CONSTANT i1 true
1111 ; CHECK: [[R1:%[0-9]+]](s1) = COPY [[ENTRY_R1]](s1)
1112 ; CHECK: [[R2:%[0-9]+]](s1) = COPY [[ENTRY_R2]](s1)
1109 ; CHECK: [[ENTRY_R1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
1110 ; CHECK: [[ENTRY_R2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
1111 ; CHECK: [[R1:%[0-9]+]]:_(s1) = COPY [[ENTRY_R1]](s1)
1112 ; CHECK: [[R2:%[0-9]+]]:_(s1) = COPY [[ENTRY_R2]](s1)
11131113 ; CHECK: G_ADD [[R1]], [[R2]]
11141114 define i1 @trivial_float_comparison(double %a, double %b) {
11151115 %r1 = fcmp false double %a, %b
11221122
11231123 define i32* @test_global() {
11241124 ; CHECK-LABEL: name: test_global
1125 ; CHECK: [[TMP:%[0-9]+]](p0) = G_GLOBAL_VALUE @var{{$}}
1125 ; CHECK: [[TMP:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var{{$}}
11261126 ; CHECK: %x0 = COPY [[TMP]](p0)
11271127
11281128 ret i32* @var
11311131 @var1 = addrspace(42) global i32 0
11321132 define i32 addrspace(42)* @test_global_addrspace() {
11331133 ; CHECK-LABEL: name: test_global
1134 ; CHECK: [[TMP:%[0-9]+]](p42) = G_GLOBAL_VALUE @var1{{$}}
1134 ; CHECK: [[TMP:%[0-9]+]]:_(p42) = G_GLOBAL_VALUE @var1{{$}}
11351135 ; CHECK: %x0 = COPY [[TMP]](p42)
11361136
11371137 ret i32 addrspace(42)* @var1
11401140
11411141 define void()* @test_global_func() {
11421142 ; CHECK-LABEL: name: test_global_func
1143 ; CHECK: [[TMP:%[0-9]+]](p0) = G_GLOBAL_VALUE @allocai64{{$}}
1143 ; CHECK: [[TMP:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @allocai64{{$}}
11441144 ; CHECK: %x0 = COPY [[TMP]](p0)
11451145
11461146 ret void()* @allocai64
11491149 declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32 %align, i1 %volatile)
11501150 define void @test_memcpy(i8* %dst, i8* %src, i64 %size) {
11511151 ; CHECK-LABEL: name: test_memcpy
1152 ; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
1153 ; CHECK: [[SRC:%[0-9]+]](p0) = COPY %x1
1154 ; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
1152 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
1153 ; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY %x1
1154 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
11551155 ; CHECK: %x0 = COPY [[DST]]
11561156 ; CHECK: %x1 = COPY [[SRC]]
11571157 ; CHECK: %x2 = COPY [[SIZE]]
11631163 declare void @llvm.memmove.p0i8.p0i8.i64(i8*, i8*, i64, i32 %align, i1 %volatile)
11641164 define void @test_memmove(i8* %dst, i8* %src, i64 %size) {
11651165 ; CHECK-LABEL: name: test_memmove
1166 ; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
1167 ; CHECK: [[SRC:%[0-9]+]](p0) = COPY %x1
1168 ; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
1166 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
1167 ; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY %x1
1168 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
11691169 ; CHECK: %x0 = COPY [[DST]]
11701170 ; CHECK: %x1 = COPY [[SRC]]
11711171 ; CHECK: %x2 = COPY [[SIZE]]
11771177 declare void @llvm.memset.p0i8.i64(i8*, i8, i64, i32 %align, i1 %volatile)
11781178 define void @test_memset(i8* %dst, i8 %val, i64 %size) {
11791179 ; CHECK-LABEL: name: test_memset
1180 ; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
1181 ; CHECK: [[SRC_C:%[0-9]+]](s32) = COPY %w1
1182 ; CHECK: [[SRC:%[0-9]+]](s8) = G_TRUNC [[SRC_C]]
1183 ; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
1180 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
1181 ; CHECK: [[SRC_C:%[0-9]+]]:_(s32) = COPY %w1
1182 ; CHECK: [[SRC:%[0-9]+]]:_(s8) = G_TRUNC [[SRC_C]]
1183 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
11841184 ; CHECK: %x0 = COPY [[DST]]
1185 ; CHECK: [[SRC_TMP:%[0-9]+]](s32) = G_ANYEXT [[SRC]]
1185 ; CHECK: [[SRC_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[SRC]]
11861186 ; CHECK: %w1 = COPY [[SRC_TMP]]
11871187 ; CHECK: %x2 = COPY [[SIZE]]
11881188 ; CHECK: BL $memset, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %w1, implicit %x2
11941194 declare i32 @llvm.objectsize.i32(i8*, i1)
11951195 define void @test_objectsize(i8* %addr0, i8* %addr1) {
11961196 ; CHECK-LABEL: name: test_objectsize
1197 ; CHECK: [[ADDR0:%[0-9]+]](p0) = COPY %x0
1198 ; CHECK: [[ADDR1:%[0-9]+]](p0) = COPY %x1
1199 ; CHECK: {{%[0-9]+}}(s64) = G_CONSTANT i64 -1
1200 ; CHECK: {{%[0-9]+}}(s64) = G_CONSTANT i64 0
1201 ; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT i32 -1
1202 ; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT i32 0
1197 ; CHECK: [[ADDR0:%[0-9]+]]:_(p0) = COPY %x0
1198 ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY %x1
1199 ; CHECK: {{%[0-9]+}}:_(s64) = G_CONSTANT i64 -1
1200 ; CHECK: {{%[0-9]+}}:_(s64) = G_CONSTANT i64 0
1201 ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 -1
1202 ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 0
12031203 %size64.0 = call i64 @llvm.objectsize.i64(i8* %addr0, i1 0)
12041204 %size64.intmin = call i64 @llvm.objectsize.i64(i8* %addr0, i1 1)
12051205 %size32.0 = call i32 @llvm.objectsize.i32(i8* %addr0, i1 0)
12091209
12101210 define void @test_large_const(i128* %addr) {
12111211 ; CHECK-LABEL: name: test_large_const
1212 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
1213 ; CHECK: [[VAL:%[0-9]+]](s128) = G_CONSTANT i128 42
1212 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1213 ; CHECK: [[VAL:%[0-9]+]]:_(s128) = G_CONSTANT i128 42
12141214 ; CHECK: G_STORE [[VAL]](s128), [[ADDR]](p0)
12151215 store i128 42, i128* %addr
12161216 ret void
12231223 define i8* @test_const_placement() {
12241224 ; CHECK-LABEL: name: test_const_placement
12251225 ; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
1226 ; CHECK: [[VAL_INT:%[0-9]+]](s32) = G_CONSTANT i32 42
1227 ; CHECK: [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32)
1226 ; CHECK: [[VAL_INT:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
1227 ; CHECK: [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](s32)
12281228 ; CHECK: {{bb.[0-9]+}}.next:
12291229 br label %next
12301230
12441244
12451245 define void @test_va_arg(i8* %list) {
12461246 ; CHECK-LABEL: test_va_arg
1247 ; CHECK: [[LIST:%[0-9]+]](p0) = COPY %x0
1247 ; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY %x0
12481248 ; CHECK: G_VAARG [[LIST]](p0), 8
12491249 ; CHECK: G_VAARG [[LIST]](p0), 1
12501250 ; CHECK: G_VAARG [[LIST]](p0), 16
12581258 declare float @llvm.pow.f32(float, float)
12591259 define float @test_pow_intrin(float %l, float %r) {
12601260 ; CHECK-LABEL: name: test_pow_intrin
1261 ; CHECK: [[LHS:%[0-9]+]](s32) = COPY %s0
1262 ; CHECK: [[RHS:%[0-9]+]](s32) = COPY %s1
1263 ; CHECK: [[RES:%[0-9]+]](s32) = G_FPOW [[LHS]], [[RHS]]
1261 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %s0
1262 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %s1
1263 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPOW [[LHS]], [[RHS]]
12641264 ; CHECK: %s0 = COPY [[RES]]
12651265 %res = call float @llvm.pow.f32(float %l, float %r)
12661266 ret float %res
12691269 declare float @llvm.fma.f32(float, float, float)
12701270 define float @test_fma_intrin(float %a, float %b, float %c) {
12711271 ; CHECK-LABEL: name: test_fma_intrin
1272 ; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
1273 ; CHECK: [[B:%[0-9]+]](s32) = COPY %s1
1274 ; CHECK: [[C:%[0-9]+]](s32) = COPY %s2
1275 ; CHECK: [[RES:%[0-9]+]](s32) = G_FMA [[A]], [[B]], [[C]]
1272 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
1273 ; CHECK: [[B:%[0-9]+]]:_(s32) = COPY %s1
1274 ; CHECK: [[C:%[0-9]+]]:_(s32) = COPY %s2
1275 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FMA [[A]], [[B]], [[C]]
12761276 ; CHECK: %s0 = COPY [[RES]]
12771277 %res = call float @llvm.fma.f32(float %a, float %b, float %c)
12781278 ret float %res
12811281 declare float @llvm.exp.f32(float)
12821282 define float @test_exp_intrin(float %a) {
12831283 ; CHECK-LABEL: name: test_exp_intrin
1284 ; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
1285 ; CHECK: [[RES:%[0-9]+]](s32) = G_FEXP [[A]]
1284 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
1285 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FEXP [[A]]
12861286 ; CHECK: %s0 = COPY [[RES]]
12871287 %res = call float @llvm.exp.f32(float %a)
12881288 ret float %res
12911291 declare float @llvm.exp2.f32(float)
12921292 define float @test_exp2_intrin(float %a) {
12931293 ; CHECK-LABEL: name: test_exp2_intrin
1294 ; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
1295 ; CHECK: [[RES:%[0-9]+]](s32) = G_FEXP2 [[A]]
1294 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
1295 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FEXP2 [[A]]
12961296 ; CHECK: %s0 = COPY [[RES]]
12971297 %res = call float @llvm.exp2.f32(float %a)
12981298 ret float %res
13011301 declare float @llvm.log.f32(float)
13021302 define float @test_log_intrin(float %a) {
13031303 ; CHECK-LABEL: name: test_log_intrin
1304 ; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
1305 ; CHECK: [[RES:%[0-9]+]](s32) = G_FLOG [[A]]
1304 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
1305 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG [[A]]
13061306 ; CHECK: %s0 = COPY [[RES]]
13071307 %res = call float @llvm.log.f32(float %a)
13081308 ret float %res
13111311 declare float @llvm.log2.f32(float)
13121312 define float @test_log2_intrin(float %a) {
13131313 ; CHECK-LABEL: name: test_log2_intrin
1314 ; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
1315 ; CHECK: [[RES:%[0-9]+]](s32) = G_FLOG2 [[A]]
1314 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
1315 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG2 [[A]]
13161316 ; CHECK: %s0 = COPY [[RES]]
13171317 %res = call float @llvm.log2.f32(float %a)
13181318 ret float %res
13301330
13311331 define void @test_load_store_atomics(i8* %addr) {
13321332 ; CHECK-LABEL: name: test_load_store_atomics
1333 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
1334 ; CHECK: [[V0:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load unordered 1 from %ir.addr)
1333 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1334 ; CHECK: [[V0:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load unordered 1 from %ir.addr)
13351335 ; CHECK: G_STORE [[V0]](s8), [[ADDR]](p0) :: (store monotonic 1 into %ir.addr)
1336 ; CHECK: [[V1:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load acquire 1 from %ir.addr)
1336 ; CHECK: [[V1:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load acquire 1 from %ir.addr)
13371337 ; CHECK: G_STORE [[V1]](s8), [[ADDR]](p0) :: (store release 1 into %ir.addr)
1338 ; CHECK: [[V2:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst 1 from %ir.addr)
1338 ; CHECK: [[V2:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst 1 from %ir.addr)
13391339 ; CHECK: G_STORE [[V2]](s8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic 1 into %ir.addr)
13401340 %v0 = load atomic i8, i8* %addr unordered, align 1
13411341 store atomic i8 %v0, i8* %addr monotonic, align 1
13511351
13521352 define float @test_fneg_f32(float %x) {
13531353 ; CHECK-LABEL: name: test_fneg_f32
1354 ; CHECK: [[ARG:%[0-9]+]](s32) = COPY %s0
1355 ; CHECK: [[RES:%[0-9]+]](s32) = G_FNEG [[ARG]]
1354 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %s0
1355 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FNEG [[ARG]]
13561356 ; CHECK: %s0 = COPY [[RES]](s32)
13571357 %neg = fsub float -0.000000e+00, %x
13581358 ret float %neg
13601360
13611361 define double @test_fneg_f64(double %x) {
13621362 ; CHECK-LABEL: name: test_fneg_f64
1363 ; CHECK: [[ARG:%[0-9]+]](s64) = COPY %d0
1364 ; CHECK: [[RES:%[0-9]+]](s64) = G_FNEG [[ARG]]
1363 ; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY %d0
1364 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FNEG [[ARG]]
13651365 ; CHECK: %d0 = COPY [[RES]](s64)
13661366 %neg = fsub double -0.000000e+00, %x
13671367 ret double %neg
13781378
13791379 define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){
13801380 ; CHECK-LABEL: name: test_insertelement
1381 ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = COPY %d0
1382 ; CHECK: [[ELT:%[0-9]+]](s32) = COPY %w0
1383 ; CHECK: [[IDX:%[0-9]+]](s32) = COPY %w1
1384 ; CHECK: [[RES:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX]](s32)
1381 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1382 ; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY %w0
1383 ; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY %w1
1384 ; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX]](s32)
13851385 ; CHECK: %d0 = COPY [[RES]](<2 x s32>)
13861386 %res = insertelement <2 x i32> %vec, i32 %elt, i32 %idx
13871387 ret <2 x i32> %res
13891389
13901390 define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) {
13911391 ; CHECK-LABEL: name: test_extractelement
1392 ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = COPY %d0
1393 ; CHECK: [[IDX:%[0-9]+]](s32) = COPY %w0
1394 ; CHECK: [[RES:%[0-9]+]](s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s32)
1392 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1393 ; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY %w0
1394 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s32)
13951395 ; CHECK: %w0 = COPY [[RES]](s32)
13961396 %res = extractelement <2 x i32> %vec, i32 %idx
13971397 ret i32 %res
13991399
14001400 define i32 @test_singleelementvector(i32 %elt){
14011401 ; CHECK-LABEL: name: test_singleelementvector
1402 ; CHECK: [[ELT:%[0-9]+]](s32) = COPY %w0
1402 ; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY %w0
14031403 ; CHECK-NOT: G_INSERT_VECTOR_ELT
14041404 ; CHECK-NOT: G_EXTRACT_VECTOR_ELT
14051405 ; CHECK: %w0 = COPY [[ELT]](s32)
14101410
14111411 define <2 x i32> @test_constantaggzerovector_v2i32() {
14121412 ; CHECK-LABEL: name: test_constantaggzerovector_v2i32
1413 ; CHECK: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1414 ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
1413 ; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
1414 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
14151415 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
14161416 ret <2 x i32> zeroinitializer
14171417 }
14181418
14191419 define <2 x float> @test_constantaggzerovector_v2f32() {
14201420 ; CHECK-LABEL: name: test_constantaggzerovector_v2f32
1421 ; CHECK: [[ZERO:%[0-9]+]](s32) = G_FCONSTANT float 0.000000e+00
1422 ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
1421 ; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
1422 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
14231423 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
14241424 ret <2 x float> zeroinitializer
14251425 }
14261426
14271427 define i32 @test_constantaggzerovector_v3i32() {
14281428 ; CHECK-LABEL: name: test_constantaggzerovector_v3i32
1429 ; CHECK: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1430 ; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32), [[ZERO]](s32)
1429 ; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
1430 ; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32), [[ZERO]](s32)
14311431 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
14321432 %elt = extractelement <3 x i32> zeroinitializer, i32 1
14331433 ret i32 %elt
14351435
14361436 define <2 x i32> @test_constantdatavector_v2i32() {
14371437 ; CHECK-LABEL: name: test_constantdatavector_v2i32
1438 ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1439 ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
1440 ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
1438 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1439 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1440 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
14411441 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
14421442 ret <2 x i32>
14431443 }
14441444
14451445 define i32 @test_constantdatavector_v3i32() {
14461446 ; CHECK-LABEL: name: test_constantdatavector_v3i32
1447 ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1448 ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
1449 ; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
1450 ; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32)
1447 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1448 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1449 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
1450 ; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32)
14511451 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
14521452 %elt = extractelement <3 x i32> , i32 1
14531453 ret i32 %elt
14551455
14561456 define <4 x i32> @test_constantdatavector_v4i32() {
14571457 ; CHECK-LABEL: name: test_constantdatavector_v4i32
1458 ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1459 ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
1460 ; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
1461 ; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
1462 ; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
1458 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1459 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1460 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
1461 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
1462 ; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
14631463 ; CHECK: %q0 = COPY [[VEC]](<4 x s32>)
14641464 ret <4 x i32>
14651465 }
14661466
14671467 define <2 x double> @test_constantdatavector_v2f64() {
14681468 ; CHECK-LABEL: name: test_constantdatavector_v2f64
1469 ; CHECK: [[FC1:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00
1470 ; CHECK: [[FC2:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
1471 ; CHECK: [[VEC:%[0-9]+]](<2 x s64>) = G_MERGE_VALUES [[FC1]](s64), [[FC2]](s64)
1469 ; CHECK: [[FC1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
1470 ; CHECK: [[FC2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
1471 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s64>) = G_MERGE_VALUES [[FC1]](s64), [[FC2]](s64)
14721472 ; CHECK: %q0 = COPY [[VEC]](<2 x s64>)
14731473 ret <2 x double>
14741474 }
14751475
14761476 define i32 @test_constantaggzerovector_v1s32(i32 %arg){
14771477 ; CHECK-LABEL: name: test_constantaggzerovector_v1s32
1478 ; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
1479 ; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1478 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
1479 ; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
14801480 ; CHECK-NOT: G_MERGE_VALUES
14811481 ; CHECK: G_ADD [[ARG]], [[C0]]
14821482 %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
14871487
14881488 define i32 @test_constantdatavector_v1s32(i32 %arg){
14891489 ; CHECK-LABEL: name: test_constantdatavector_v1s32
1490 ; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
1491 ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1490 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
1491 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
14921492 ; CHECK-NOT: G_MERGE_VALUES
14931493 ; CHECK: G_ADD [[ARG]], [[C1]]
14941494 %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
15001500 declare ghccc float @different_call_conv_target(float %x)
15011501 define float @test_different_call_conv_target(float %x) {
15021502 ; CHECK-LABEL: name: test_different_call_conv
1503 ; CHECK: [[X:%[0-9]+]](s32) = COPY %s0
1503 ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0
15041504 ; CHECK: %s8 = COPY [[X]]
15051505 ; CHECK: BL @different_call_conv_target, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s8, implicit-def %s0
15061506 %res = call ghccc float @different_call_conv_target(float %x)
15091509
15101510 define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
15111511 ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
1512 ; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
1513 ; CHECK-DAG: [[UNDEF:%[0-9]+]](s32) = G_IMPLICIT_DEF
1514 ; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1515 ; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
1516 ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
1512 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
1513 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
1514 ; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
1515 ; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
1516 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
15171517 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
15181518 %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
15191519 %res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
15221522
15231523 define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
15241524 ; CHECK-LABEL: name: test_shufflevector_v2s32_s32
1525 ; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
1526 ; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
1527 ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1528 ; CHECK: [[RES:%[0-9]+]](s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32)
1525 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1526 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
1527 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1528 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32)
15291529 ; CHECK: %w0 = COPY [[RES]](s32)
15301530 %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32>
15311531 %res = extractelement <1 x i32> %vec, i32 0
15341534
15351535 define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) {
15361536 ; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32
1537 ; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
1538 ; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
1539 ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1540 ; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1541 ; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32)
1542 ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
1537 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1538 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
1539 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1540 ; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
1541 ; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32)
1542 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
15431543 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
15441544 %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32>
15451545 ret <2 x i32> %res
15471547
15481548 define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
15491549 ; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
1550 ; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
1551 ; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
1552 ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1553 ; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1554 ; CHECK-DAG: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
1555 ; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
1550 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1551 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
1552 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1553 ; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
1554 ; CHECK-DAG: [[MASK:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
1555 ; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
15561556 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
15571557 %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <3 x i32>
15581558 %res = extractelement <3 x i32> %vec, i32 0
15611561
15621562 define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) {
15631563 ; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
1564 ; CHECK: [[ARG1:%[0-9]+]](<2 x s32>) = COPY %d0
1565 ; CHECK: [[ARG2:%[0-9]+]](<2 x s32>) = COPY %d1
1566 ; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1567 ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1568 ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
1569 ; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
1570 ; CHECK: [[MASK:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
1571 ; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>)
1564 ; CHECK: [[ARG1:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1565 ; CHECK: [[ARG2:%[0-9]+]]:_(<2 x s32>) = COPY %d1
1566 ; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
1567 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1568 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1569 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
1570 ; CHECK: [[MASK:%[0-9]+]]:_(<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
1571 ; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>)
15721572 ; CHECK: %q0 = COPY [[VEC]](<4 x s32>)
15731573 %res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32>
15741574 ret <4 x i32> %res
15761576
15771577 define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
15781578 ; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
1579 ; CHECK: [[ARG:%[0-9]+]](<4 x s32>) = COPY %q0
1580 ; CHECK-DAG: [[UNDEF:%[0-9]+]](<4 x s32>) = G_IMPLICIT_DEF
1581 ; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1582 ; CHECK-DAG: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
1583 ; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
1584 ; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
1579 ; CHECK: [[ARG:%[0-9]+]]:_(<4 x s32>) = COPY %q0
1580 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
1581 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1582 ; CHECK-DAG: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
1583 ; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
1584 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
15851585 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
15861586 %res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32>
15871587 ret <2 x i32> %res
15901590
15911591 define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) {
15921592 ; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8
1593 ; CHECK: [[ARG1:%[0-9]+]](<8 x s8>) = COPY %d0
1594 ; CHECK: [[ARG2:%[0-9]+]](<8 x s8>) = COPY %d1
1595 ; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1596 ; CHECK: [[C8:%[0-9]+]](s32) = G_CONSTANT i32 8
1597 ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1598 ; CHECK: [[C9:%[0-9]+]](s32) = G_CONSTANT i32 9
1599 ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
1600 ; CHECK: [[C10:%[0-9]+]](s32) = G_CONSTANT i32 10
1601 ; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
1602 ; CHECK: [[C11:%[0-9]+]](s32) = G_CONSTANT i32 11
1603 ; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
1604 ; CHECK: [[C12:%[0-9]+]](s32) = G_CONSTANT i32 12
1605 ; CHECK: [[C5:%[0-9]+]](s32) = G_CONSTANT i32 5
1606 ; CHECK: [[C13:%[0-9]+]](s32) = G_CONSTANT i32 13
1607 ; CHECK: [[C6:%[0-9]+]](s32) = G_CONSTANT i32 6
1608 ; CHECK: [[C14:%[0-9]+]](s32) = G_CONSTANT i32 14
1609 ; CHECK: [[C7:%[0-9]+]](s32) = G_CONSTANT i32 7
1610 ; CHECK: [[C15:%[0-9]+]](s32) = G_CONSTANT i32 15
1611 ; CHECK: [[MASK:%[0-9]+]](<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)
1612 ; CHECK: [[VEC:%[0-9]+]](<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)
1593 ; CHECK: [[ARG1:%[0-9]+]]:_(<8 x s8>) = COPY %d0
1594 ; CHECK: [[ARG2:%[0-9]+]]:_(<8 x s8>) = COPY %d1
1595 ; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
1596 ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
1597 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1598 ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
1599 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1600 ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
1601 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
1602 ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
1603 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
1604 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
1605 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
1606 ; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
1607 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
1608 ; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
1609 ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
1610 ; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
1611 ; CHECK: [[MASK:%[0-9]+]]:_(<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)
1612 ; CHECK: [[VEC:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)
16131613 ; CHECK: %q0 = COPY [[VEC]](<16 x s8>)
16141614 %res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32>
16151615 ret <16 x i8> %res
16161616 }
16171617
16181618 ; CHECK-LABEL: test_constant_vector
1619 ; CHECK: [[UNDEF:%[0-9]+]](s16) = G_IMPLICIT_DEF
1620 ; CHECK: [[F:%[0-9]+]](s16) = G_FCONSTANT half 0xH3C00
1621 ; CHECK: [[M:%[0-9]+]](<4 x s16>) = G_MERGE_VALUES [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
1619 ; CHECK: [[UNDEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
1620 ; CHECK: [[F:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
1621 ; CHECK: [[M:%[0-9]+]]:_(<4 x s16>) = G_MERGE_VALUES [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
16221622 ; CHECK: %d0 = COPY [[M]](<4 x s16>)
16231623 define <4 x half> @test_constant_vector() {
16241624 ret <4 x half>
16261626
16271627 define i32 @test_target_mem_intrinsic(i32* %addr) {
16281628 ; CHECK-LABEL: name: test_target_mem_intrinsic
1629 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
1630 ; CHECK: [[VAL:%[0-9]+]](s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load 4 from %ir.addr)
1629 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1630 ; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load 4 from %ir.addr)
16311631 ; CHECK: G_TRUNC [[VAL]](s64)
16321632 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
16331633 %trunc = trunc i64 %val to i32
9898 # Based on the type i32, this should be gpr.
9999 name: defaultMapping
100100 legalized: true
101 # CHECK-LABEL: name: defaultMapping
102 # CHECK: registers:
103 # CHECK: - { id: 0, class: gpr, preferred-register: '' }
104 # CHECK: - { id: 1, class: gpr, preferred-register: '' }
105101 registers:
106102 - { id: 0, class: _ }
107103 - { id: 1, class: _ }
108104 body: |
109105 bb.0.entry:
110106 liveins: %x0
111 ; CHECK: %1(s32) = G_ADD %0
107 ; CHECK-LABEL: name: defaultMapping
108 ; CHECK: %1:gpr(s32) = G_ADD %0
112109 %0(s32) = COPY %w0
113110 %1(s32) = G_ADD %0, %0
114111 ...
119116 # FPR is used for both floating point and vector registers.
120117 name: defaultMappingVector
121118 legalized: true
122 # CHECK-LABEL: name: defaultMappingVector
123 # CHECK: registers:
124 # CHECK: - { id: 0, class: fpr, preferred-register: '' }
125 # CHECK: - { id: 1, class: fpr, preferred-register: '' }
126119 registers:
127120 - { id: 0, class: _ }
128121 - { id: 1, class: _ }
129122 body: |
130123 bb.0.entry:
131124 liveins: %d0
132 ; CHECK: %0(<2 x s32>) = COPY %d0
133 ; CHECK: %1(<2 x s32>) = G_ADD %0
125 ; CHECK-LABEL: name: defaultMappingVector
126 ; CHECK: %0:fpr(<2 x s32>) = COPY %d0
127 ; CHECK: %1:fpr(<2 x s32>) = G_ADD %0
134128 %0(<2 x s32>) = COPY %d0
135129 %1(<2 x s32>) = G_ADD %0, %0
136130 ...
141135 # in FPR, but at the use, it should be GPR.
142136 name: defaultMapping1Repair
143137 legalized: true
144 # CHECK-LABEL: name: defaultMapping1Repair
145 # CHECK: registers:
146 # CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
147 # CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
148 # CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
149 # CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
150138 registers:
151139 - { id: 0, class: _ }
152140 - { id: 1, class: _ }
154142 body: |
155143 bb.0.entry:
156144 liveins: %s0, %x0
157 ; CHECK: %0(s32) = COPY %s0
158 ; CHECK-NEXT: %1(s32) = COPY %w0
159 ; CHECK-NEXT: %3(s32) = COPY %0
160 ; CHECK-NEXT: %2(s32) = G_ADD %3, %1
145 ; CHECK-LABEL: name: defaultMapping1Repair
146 ; CHECK: %0:fpr(s32) = COPY %s0
147 ; CHECK-NEXT: %1:gpr(s32) = COPY %w0
148 ; CHECK-NEXT: %3:gpr(s32) = COPY %0
149 ; CHECK-NEXT: %2:gpr(s32) = G_ADD %3, %1
161150 %0(s32) = COPY %s0
162151 %1(s32) = COPY %w0
163152 %2(s32) = G_ADD %0, %1
166155 # Check that we repair the assignment for %0 differently for both uses.
167156 name: defaultMapping2Repairs
168157 legalized: true
169 # CHECK-LABEL: name: defaultMapping2Repairs
170 # CHECK: registers:
171 # CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
172 # CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
173 # CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
174 # CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
175158 registers:
176159 - { id: 0, class: _ }
177160 - { id: 1, class: _ }
178161 body: |
179162 bb.0.entry:
180163 liveins: %s0, %x0
181 ; CHECK: %0(s32) = COPY %s0
182 ; CHECK-NEXT: %2(s32) = COPY %0
183 ; CHECK-NEXT: %3(s32) = COPY %0
184 ; CHECK-NEXT: %1(s32) = G_ADD %2, %3
164 ; CHECK-LABEL: name: defaultMapping2Repairs
165 ; CHECK: %0:fpr(s32) = COPY %s0
166 ; CHECK-NEXT: %2:gpr(s32) = COPY %0
167 ; CHECK-NEXT: %3:gpr(s32) = COPY %0
168 ; CHECK-NEXT: %1:gpr(s32) = G_ADD %2, %3
185169 %0(s32) = COPY %s0
186170 %1(s32) = G_ADD %0, %0
187171 ...
193177 # fixes that.
194178 name: defaultMappingDefRepair
195179 legalized: true
196 # CHECK-LABEL: name: defaultMappingDefRepair
197 # CHECK: registers:
198 # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
199 # CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '' }
200 # CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
201180 registers:
202181 - { id: 0, class: _ }
203182 - { id: 1, class: fpr }
204183 body: |
205184 bb.0.entry:
206185 liveins: %w0
207 ; CHECK: %0(s32) = COPY %w0
208 ; CHECK-NEXT: %2(s32) = G_ADD %0, %0
209 ; CHECK-NEXT: %1(s32) = COPY %2
186 ; CHECK-LABEL: name: defaultMappingDefRepair
187 ; CHECK: %0:gpr(s32) = COPY %w0
188 ; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %0
189 ; CHECK-NEXT: %1:fpr(s32) = COPY %2
210190 %0(s32) = COPY %w0
211191 %1(s32) = G_ADD %0, %0
212192 ...
254234 # Make sure we can repair physical register uses as well.
255235 name: defaultMappingUseRepairPhysReg
256236 legalized: true
257 # CHECK-LABEL: name: defaultMappingUseRepairPhysReg
258 # CHECK: registers:
259 # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
260 # CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '' }
261 # CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
262 # CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
263237 registers:
264238 - { id: 0, class: _ }
265239 - { id: 1, class: _ }
267241 body: |
268242 bb.0.entry:
269243 liveins: %w0, %s0
270 ; CHECK: %0(s32) = COPY %w0
271 ; CHECK-NEXT: %1(s32) = COPY %s0
272 ; CHECK-NEXT: %3(s32) = COPY %1
273 ; CHECK-NEXT: %2(s32) = G_ADD %0, %3
244 ; CHECK-LABEL: name: defaultMappingUseRepairPhysReg
245 ; CHECK: %0:gpr(s32) = COPY %w0
246 ; CHECK-NEXT: %1:fpr(s32) = COPY %s0
247 ; CHECK-NEXT: %3:gpr(s32) = COPY %1
248 ; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %3
274249 %0(s32) = COPY %w0
275250 %1(s32) = COPY %s0
276251 %2(s32) = G_ADD %0, %1
280255 # Make sure we can repair physical register defs.
281256 name: defaultMappingDefRepairPhysReg
282257 legalized: true
283 # CHECK-LABEL: name: defaultMappingDefRepairPhysReg
284 # CHECK: registers:
285 # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
286 # CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
287258 registers:
288259 - { id: 0, class: _ }
289260 - { id: 1, class: _ }
290261 body: |
291262 bb.0.entry:
292263 liveins: %w0
293 ; CHECK: %0(s32) = COPY %w0
294 ; CHECK-NEXT: %1(s32) = G_ADD %0, %0
264 ; CHECK-LABEL: name: defaultMappingDefRepairPhysReg
265 ; CHECK: %0:gpr(s32) = COPY %w0
266 ; CHECK-NEXT: %1:gpr(s32) = G_ADD %0, %0
295267 ; CHECK-NEXT: %s0 = COPY %1
296268 %0(s32) = COPY %w0
297269 %1(s32) = G_ADD %0, %0
303275 # G_OR instruction from fpr to gpr.
304276 name: greedyMappingOr
305277 legalized: true
306 # CHECK-LABEL: name: greedyMappingOr
307 # CHECK: registers:
308 # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
309 # CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
310
311 # Fast mode maps vector instruction on FPR.
312 # FAST-NEXT: - { id: 2, class: fpr, preferred-register: '' }
313 # Fast mode needs two extra copies.
314 # FAST-NEXT: - { id: 3, class: fpr, preferred-register: '' }
315 # FAST-NEXT: - { id: 4, class: fpr, preferred-register: '' }
316
317 # Greedy mode coalesce the computation on the GPR register
318 # because it is the cheapest.
319 # GREEDY-NEXT: - { id: 2, class: gpr, preferred-register: '' }
320
321278 registers:
322279 - { id: 0, class: _ }
323280 - { id: 1, class: _ }
325282 body: |
326283 bb.0.entry:
327284 liveins: %x0, %x1
328 ; CHECK: %0(<2 x s32>) = COPY %x0
329 ; CHECK-NEXT: %1(<2 x s32>) = COPY %x1
330
285 ; CHECK: %0:gpr(<2 x s32>) = COPY %x0
286 ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY %x1
331287
332288 ; Fast mode tries to reuse the source of the copy for the destination.
333289 ; Now, the default mapping says that %0 and %1 need to be in FPR.
334290 ; The repairing code insert two copies to materialize that.
335 ; FAST-NEXT: %3(<2 x s32>) = COPY %0
336 ; FAST-NEXT: %4(<2 x s32>) = COPY %1
291 ; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0
292 ; FAST-NEXT: %4:fpr(<2 x s32>) = COPY %1
337293 ; The mapping of G_OR is on FPR.
338 ; FAST-NEXT: %2(<2 x s32>) = G_OR %3, %4
294 ; FAST-NEXT: %2:fpr(<2 x s32>) = G_OR %3, %4
339295
340296 ; Greedy mode remapped the instruction on the GPR bank.
341 ; GREEDY-NEXT: %2(<2 x s32>) = G_OR %0, %1
297 ; GREEDY-NEXT: %2:gpr(<2 x s32>) = G_OR %0, %1
342298 %0(<2 x s32>) = COPY %x0
343299 %1(<2 x s32>) = COPY %x1
344300 %2(<2 x s32>) = G_OR %0, %1
350306 # %2 constraint.
351307 name: greedyMappingOrWithConstraints
352308 legalized: true
353 # CHECK-LABEL: name: greedyMappingOrWithConstraints
354 # CHECK: registers:
355 # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
356 # CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
357 # CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
358
359 # Fast mode maps vector instruction on FPR.
360 # Fast mode needs two extra copies.
361 # FAST-NEXT: - { id: 3, class: fpr, preferred-register: '' }
362 # FAST-NEXT: - { id: 4, class: fpr, preferred-register: '' }
363
364 # Greedy mode coalesce the computation on the GPR register because it
365 # is the cheapest, but will need one extra copy to materialize %2 into a FPR.
366 # GREEDY-NEXT: - { id: 3, class: gpr, preferred-register: '' }
367
368309 registers:
369310 - { id: 0, class: _ }
370311 - { id: 1, class: _ }
372313 body: |
373314 bb.0.entry:
374315 liveins: %x0, %x1
375 ; CHECK: %0(<2 x s32>) = COPY %x0
376 ; CHECK-NEXT: %1(<2 x s32>) = COPY %x1
377
316 ; CHECK-LABEL: name: greedyMappingOrWithConstraints
317
318 ; CHECK: %0:gpr(<2 x s32>) = COPY %x0
319 ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY %x1
378320
379321 ; Fast mode tries to reuse the source of the copy for the destination.
380322 ; Now, the default mapping says that %0 and %1 need to be in FPR.
381323 ; The repairing code insert two copies to materialize that.
382 ; FAST-NEXT: %3(<2 x s32>) = COPY %0
383 ; FAST-NEXT: %4(<2 x s32>) = COPY %1
324 ; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0
325 ; FAST-NEXT: %4:fpr(<2 x s32>) = COPY %1
384326 ; The mapping of G_OR is on FPR.
385 ; FAST-NEXT: %2(<2 x s32>) = G_OR %3, %4
327 ; FAST-NEXT: %2:fpr(<2 x s32>) = G_OR %3, %4
386328
387329 ; Greedy mode remapped the instruction on the GPR bank.
388 ; GREEDY-NEXT: %3(<2 x s32>) = G_OR %0, %1
330 ; GREEDY-NEXT: %3:gpr(<2 x s32>) = G_OR %0, %1
389331 ; We need to keep %2 into FPR because we do not know anything about it.
390 ; GREEDY-NEXT: %2(<2 x s32>) = COPY %3
332 ; GREEDY-NEXT: %2:fpr(<2 x s32>) = COPY %3
391333 %0(<2 x s32>) = COPY %x0
392334 %1(<2 x s32>) = COPY %x1
393335 %2(<2 x s32>) = G_OR %0, %1
407349 bb.0:
408350 liveins: %x0
409351
410 ; CHECK: %0 = COPY %x0
411 ; CHECK-NEXT: %1 = ADDXrr %0, %0
352 ; CHECK: %0:gpr64 = COPY %x0
353 ; CHECK-NEXT: %1:gpr64 = ADDXrr %0, %0
412354 ; CHECK-NEXT: %x0 = COPY %1
413355 ; CHECK-NEXT: RET_ReallyLR implicit %x0
414356
443385 - { id: 1, class: _ }
444386
445387 # CHECK: body:
446 # CHECK: %0(s32) = COPY %w0
447 # CHECK: %1(s32) = G_BITCAST %0
388 # CHECK: %0:gpr(s32) = COPY %w0
389 # CHECK: %1:gpr(s32) = G_BITCAST %0
448390 body: |
449391 bb.0:
450392 liveins: %w0
466408 - { id: 1, class: _ }
467409
468410 # CHECK: body:
469 # CHECK: %0(<2 x s16>) = COPY %s0
470 # CHECK: %1(<2 x s16>) = G_BITCAST %0
411 # CHECK: %0:fpr(<2 x s16>) = COPY %s0
412 # CHECK: %1:fpr(<2 x s16>) = G_BITCAST %0
471413 body: |
472414 bb.0:
473415 liveins: %s0
490432 - { id: 1, class: _ }
491433
492434 # CHECK: body:
493 # CHECK: %0(s32) = COPY %w0
494 # CHECK: %1(<2 x s16>) = G_BITCAST %0
435 # CHECK: %0:gpr(s32) = COPY %w0
436 # FAST: %1:fpr(<2 x s16>) = G_BITCAST %0
437 # GREEDY: %1:gpr(<2 x s16>) = G_BITCAST %0
495438 body: |
496439 bb.0:
497440 liveins: %w0
504447 # CHECK-LABEL: name: bitcast_s32_fpr_gpr
505448 name: bitcast_s32_fpr_gpr
506449 legalized: true
507
508 # CHECK: registers:
509 # CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
510 # FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' }
511 # GREEDY-NEXT: - { id: 1, class: fpr, preferred-register: '' }
512 registers:
513 - { id: 0, class: _ }
514 - { id: 1, class: _ }
515
450 registers:
451 - { id: 0, class: _ }
452 - { id: 1, class: _ }
516453 # CHECK: body:
517 # CHECK: %0(<2 x s16>) = COPY %s0
518 # CHECK: %1(s32) = G_BITCAST %0
454 # CHECK: %0:fpr(<2 x s16>) = COPY %s0
455 # FAST: %1:gpr(s32) = G_BITCAST %0
456 # GREEDY: %1:fpr(s32) = G_BITCAST %0
519457 body: |
520458 bb.0:
521459 liveins: %s0
528466 # CHECK-LABEL: name: bitcast_s64_gpr
529467 name: bitcast_s64_gpr
530468 legalized: true
531
532 # CHECK: registers:
533 # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
534 # CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
535 registers:
536 - { id: 0, class: _ }
537 - { id: 1, class: _ }
538
469 registers:
470 - { id: 0, class: _ }
471 - { id: 1, class: _ }
539472 # CHECK: body:
540 # CHECK: %0(s64) = COPY %x0
541 # CHECK: %1(s64) = G_BITCAST %0
473 # CHECK: %0:gpr(s64) = COPY %x0
474 # CHECK: %1:gpr(s64) = G_BITCAST %0
542475 body: |
543476 bb.0:
544477 liveins: %x0
551484 # CHECK-LABEL: name: bitcast_s64_fpr
552485 name: bitcast_s64_fpr
553486 legalized: true
554
555 # CHECK: registers:
556 # CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
557 # CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '' }
558 registers:
559 - { id: 0, class: _ }
560 - { id: 1, class: _ }
561
487 registers:
488 - { id: 0, class: _ }
489 - { id: 1, class: _ }
562490 # CHECK: body:
563 # CHECK: %0(<2 x s32>) = COPY %d0
564 # CHECK: %1(<2 x s32>) = G_BITCAST %0
491 # CHECK: %0:fpr(<2 x s32>) = COPY %d0
492 # CHECK: %1:fpr(<2 x s32>) = G_BITCAST %0
565493 body: |
566494 bb.0:
567495 liveins: %d0
574502 # CHECK-LABEL: name: bitcast_s64_gpr_fpr
575503 name: bitcast_s64_gpr_fpr
576504 legalized: true
577
578 # CHECK: registers:
579 # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
580 # FAST-NEXT: - { id: 1, class: fpr, preferred-register: '' }
581 # GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
582505 registers:
583506 - { id: 0, class: _ }
584507 - { id: 1, class: _ }
585508 # CHECK: body:
586 # CHECK: %0(s64) = COPY %x0
587 # CHECK: %1(<2 x s32>) = G_BITCAST %0
509 # CHECK: %0:gpr(s64) = COPY %x0
510 # FAST: %1:fpr(<2 x s32>) = G_BITCAST %0
511 # GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0
588512 body: |
589513 bb.0:
590514 liveins: %x0
597521 # CHECK-LABEL: name: bitcast_s64_fpr_gpr
598522 name: bitcast_s64_fpr_gpr
599523 legalized: true
600
601 # CHECK: registers:
602 # CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
603 # FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' }
604 # GREEDY-NEXT: - { id: 1, class: fpr, preferred-register: '' }
605 registers:
606 - { id: 0, class: _ }
607 - { id: 1, class: _ }
608
524 registers:
525 - { id: 0, class: _ }
526 - { id: 1, class: _ }
609527 # CHECK: body:
610 # CHECK: %0(<2 x s32>) = COPY %d0
611 # CHECK: %1(s64) = G_BITCAST %0
528 # CHECK: %0:fpr(<2 x s32>) = COPY %d0
529 # FAST: %1:gpr(s64) = G_BITCAST %0
530 # GREEDY: %1:fpr(s64) = G_BITCAST %0
612531 body: |
613532 bb.0:
614533 liveins: %d0
627546 - { id: 1, class: _}
628547 - { id: 2, class: _}
629548 - { id: 3, class: _}
630 # CHECK: registers:
631 # CHECK: - { id: 2, class: fpr, preferred-register: '' }
632 # CHECK: - { id: 3, class: fpr, preferred-register: '' }
633 # CHECK: %2(<2 x s64>) = G_BITCAST %3(s128)
549 # CHECK: %3:fpr(s128) = G_MERGE_VALUES
550 # CHECK: %2:fpr(<2 x s64>) = G_BITCAST %3(s128)
634551 body: |
635552 bb.1:
636553 liveins: %x0, %x1
657574 - { id: 2, class: _}
658575 - { id: 3, class: _}
659576 - { id: 4, class: _}
660 # CHECK: registers:
661 # CHECK: - { id: 2, class: fpr, preferred-register: '' }
662 # CHECK: - { id: 3, class: fpr, preferred-register: '' }
663 # CHECK: - { id: 4, class: fpr, preferred-register: '' }
664 # CHECK: %4(s128) = COPY %3(s128)
665 # CHECK-NEXT: %2(<2 x s64>) = G_BITCAST %4(s128)
577 # CHECK: %3:fpr(s128) = G_MERGE_VALUES
578 # CHECK: %4:fpr(s128) = COPY %3(s128)
579 # CHECK-NEXT: %2:fpr(<2 x s64>) = G_BITCAST %4(s128)
666580 body: |
667581 bb.1:
668582 liveins: %x0, %x1
694608 # CHECK: registers:
695609 # CHECK: - { id: 0, class: fpr128, preferred-register: '' }
696610 # CHECK: - { id: 1, class: fpr, preferred-register: '' }
697 # CHECK: %1(s128) = COPY %0
611 # CHECK: %1:fpr(s128) = COPY %0
698612 body: |
699613 bb.1:
700614 liveins: %x0
713627 # CHECK-LABEL: name: greedyWithChainOfComputation
714628 name: greedyWithChainOfComputation
715629 legalized: true
716
717 # CHECK: registers:
718 # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
719 # CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
720 # FAST-NEXT: - { id: 2, class: fpr, preferred-register: '' }
721 # FAST-NEXT: - { id: 3, class: fpr, preferred-register: '' }
722 # FAST-NEXT: - { id: 4, class: fpr, preferred-register: '' }
723 # GREEDY-NEXT: - { id: 2, class: gpr, preferred-register: '' }
724 # GREEDY-NEXT: - { id: 3, class: gpr, preferred-register: '' }
725 # GREEDY-NEXT: - { id: 4, class: gpr, preferred-register: '' }
726 # CHECK-NEXT: - { id: 5, class: gpr, preferred-register: '' }
727630 registers:
728631 - { id: 0, class: _ }
729632 - { id: 1, class: _ }
731634 - { id: 3, class: _ }
732635 - { id: 4, class: _ }
733636 - { id: 5, class: _ }
734
735637 # No repairing should be necessary for both modes.
736 # CHECK: %0(s64) = COPY %x0
737 # CHECK-NEXT: %1(p0) = COPY %x1
738 # CHECK-NEXT: %2(<2 x s32>) = G_BITCAST %0(s64)
739 # CHECK-NEXT: %3(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
740 # CHECK-NEXT: %4(<2 x s32>) = G_OR %2, %3
741 # CHECK-NEXT: %5(s64) = G_BITCAST %4(<2 x s32>)
638 # CHECK: %0:gpr(s64) = COPY %x0
639 # CHECK-NEXT: %1:gpr(p0) = COPY %x1
640 # FAST-NEXT: %2:fpr(<2 x s32>) = G_BITCAST %0(s64)
641 # FAST-NEXT: %3:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
642 # FAST-NEXT: %4:fpr(<2 x s32>) = G_OR %2, %3
643 # GREEDY-NEXT: %2:gpr(<2 x s32>) = G_BITCAST %0(s64)
644 # GREEDY-NEXT: %3:gpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
645 # GREEDY-NEXT: %4:gpr(<2 x s32>) = G_OR %2, %3
646 # CHECK-NEXT: %5:gpr(s64) = G_BITCAST %4(<2 x s32>)
742647 # CHECK-NEXT: %x0 = COPY %5(s64)
743648 # CHECK-NEXT: RET_ReallyLR implicit %x0
744
745649 body: |
746650 bb.0:
747651 liveins: %x0, %x1
777681 - { id: 3, class: _ }
778682
779683 # No repairing should be necessary for both modes.
780 # CHECK: %0(s64) = COPY %x0
781 # CHECK-NEXT: %1(p0) = COPY %x1
782 # CHECK-NEXT: %2(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
684 # CHECK: %0:gpr(s64) = COPY %x0
685 # CHECK-NEXT: %1:gpr(p0) = COPY %x1
686 # CHECK-NEXT: %2:fpr(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
783687 # %0 has been mapped to GPR, we need to repair to match FPR.
784 # CHECK-NEXT: %4(s64) = COPY %0
785 # CHECK-NEXT: %3(s64) = G_FADD %4, %2
688 # CHECK-NEXT: %4:fpr(s64) = COPY %0
689 # CHECK-NEXT: %3:fpr(s64) = G_FADD %4, %2
786690 # CHECK-NEXT: %x0 = COPY %3(s64)
787691 # CHECK-NEXT: RET_ReallyLR implicit %x0
788692
817721 - { id: 1, class: _ }
818722 - { id: 2, class: _ }
819723
820 # CHECK: %0(s64) = COPY %x0
821 # CHECK-NEXT: %1(p0) = COPY %x1
724 # CHECK: %0:gpr(s64) = COPY %x0
725 # CHECK-NEXT: %1:gpr(p0) = COPY %x1
822726 # %0 has been mapped to GPR, we need to repair to match FPR.
823 # CHECK-NEXT: %3(s64) = COPY %0
824 # CHECK-NEXT: %4(s64) = COPY %0
825 # CHECK-NEXT: %2(s64) = G_FADD %3, %4
727 # CHECK-NEXT: %3:fpr(s64) = COPY %0
728 # CHECK-NEXT: %4:fpr(s64) = COPY %0
729 # CHECK-NEXT: %2:fpr(s64) = G_FADD %3, %4
826730 # CHECK-NEXT: G_STORE %2(s64), %1(p0) :: (store 8 into %ir.addr)
827731 # CHECK-NEXT: RET_ReallyLR
828732
44 ; CHECK: fixedStack:
55 ; CHECK-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1,
66 ; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1,
7 ; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
8 ; CHECK: [[LHS:%[0-9]+]](s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
9 ; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
10 ; CHECK: [[RHS:%[0-9]+]](s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
11 ; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[LHS]], [[RHS]]
12 ; CHECK: [[SUM32:%[0-9]+]](s32) = G_SEXT [[SUM]](s8)
7 ; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
8 ; CHECK: [[LHS:%[0-9]+]]:_(s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
9 ; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
10 ; CHECK: [[RHS:%[0-9]+]]:_(s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
11 ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[LHS]], [[RHS]]
12 ; CHECK: [[SUM32:%[0-9]+]]:_(s32) = G_SEXT [[SUM]](s8)
1313 ; CHECK: %w0 = COPY [[SUM32]](s32)
1414 define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) {
1515 %sum = add i8 %lhs, %rhs
1717 }
1818
1919 ; CHECK-LABEL: name: test_call_stack
20 ; CHECK: [[C42:%[0-9]+]](s8) = G_CONSTANT i8 42
21 ; CHECK: [[C12:%[0-9]+]](s8) = G_CONSTANT i8 12
22 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
23 ; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
24 ; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
20 ; CHECK: [[C42:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
21 ; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 12
22 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
23 ; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
24 ; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
2525 ; CHECK: G_STORE [[C42]](s8), [[C42_LOC]](p0) :: (store 1 into stack, align 0)
26 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
27 ; CHECK: [[C12_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 1
28 ; CHECK: [[C12_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
26 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
27 ; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
28 ; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
2929 ; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store 1 into stack + 1, align 0)
3030 ; CHECK: BL @test_stack_slots
3131 define void @test_call_stack() {
4545 }
4646
4747 ; CHECK-LABEL: name: take_128bit_struct
48 ; CHECK: {{%.*}}(p0) = COPY %x0
49 ; CHECK: {{%.*}}(s64) = COPY %x1
50 ; CHECK: {{%.*}}(s64) = COPY %x2
48 ; CHECK: {{%.*}}:_(p0) = COPY %x0
49 ; CHECK: {{%.*}}:_(s64) = COPY %x1
50 ; CHECK: {{%.*}}:_(s64) = COPY %x2
5151 define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
5252 store [2 x i64] %in, [2 x i64]* %ptr
5353 ret void
5454 }
5555
5656 ; CHECK-LABEL: name: test_split_struct
57 ; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD {{.*}}(p0)
58 ; CHECK: [[LO:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 0
59 ; CHECK: [[HI:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 64
57 ; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD {{.*}}(p0)
58 ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 0
59 ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 64
6060
61 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
62 ; CHECK: [[OFF:%[0-9]+]](s64) = G_CONSTANT i64 0
63 ; CHECK: [[ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF]]
61 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
62 ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
63 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
6464 ; CHECK: G_STORE [[LO]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0)
6565
66 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
67 ; CHECK: [[OFF:%[0-9]+]](s64) = G_CONSTANT i64 8
68 ; CHECK: [[ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF]]
66 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
67 ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
68 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
6969 ; CHECK: G_STORE [[HI]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0)
7070 define void @test_split_struct([2 x i64]* %ptr) {
7171 %struct = load [2 x i64], [2 x i64]* %ptr
8080 ; CHECK-DAG: - { id: [[LO_FRAME:[0-9]+]], type: default, offset: 0, size: 8
8181 ; CHECK-DAG: - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8
8282
83 ; CHECK: [[LOPTR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
84 ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0)
83 ; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
84 ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0)
8585
86 ; CHECK: [[HIPTR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
87 ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0)
86 ; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
87 ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0)
8888 define void @take_split_struct([2 x i64]* %ptr, i64, i64, i64,
8989 i64, i64, i64,
9090 [2 x i64] %in) {
1111
1212 ; CHECK-LABEL: name: test_simple_return
1313 ; CHECK: BL @simple_return_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit-def %x0
14 ; CHECK: [[RES:%[0-9]+]](s64) = COPY %x0
14 ; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY %x0
1515 ; CHECK: %x0 = COPY [[RES]]
1616 ; CHECK: RET_ReallyLR implicit %x0
1717 declare i64 @simple_return_callee()
2121 }
2222
2323 ; CHECK-LABEL: name: test_simple_arg
24 ; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
24 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
2525 ; CHECK: %w0 = COPY [[IN]]
2626 ; CHECK: BL @simple_arg_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
2727 ; CHECK: RET_ReallyLR
3535 ; CHECK: registers:
3636 ; Make sure the register feeding the indirect call is properly constrained.
3737 ; CHECK: - { id: [[FUNC:[0-9]+]], class: gpr64, preferred-register: '' }
38 ; CHECK: %[[FUNC]](p0) = COPY %x0
38 ; CHECK: %[[FUNC]]:gpr64(p0) = COPY %x0
3939 ; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def %lr, implicit %sp
4040 ; CHECK: RET_ReallyLR
4141 define void @test_indirect_call(void()* %func) {
4444 }
4545
4646 ; CHECK-LABEL: name: test_multiple_args
47 ; CHECK: [[IN:%[0-9]+]](s64) = COPY %x0
48 ; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
47 ; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %x0
48 ; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
4949 ; CHECK: %w0 = COPY [[ANSWER]]
5050 ; CHECK: %x1 = COPY [[IN]]
5151 ; CHECK: BL @multiple_args_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit %x1
5858
5959
6060 ; CHECK-LABEL: name: test_struct_formal
61 ; CHECK: [[DBL:%[0-9]+]](s64) = COPY %d0
62 ; CHECK: [[I64:%[0-9]+]](s64) = COPY %x0
63 ; CHECK: [[I8_C:%[0-9]+]](s32) = COPY %w1
64 ; CHECK: [[I8:%[0-9]+]](s8) = G_TRUNC [[I8_C]]
65 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
66
67 ; CHECK: [[UNDEF:%[0-9]+]](s192) = G_IMPLICIT_DEF
68 ; CHECK: [[ARG0:%[0-9]+]](s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0
69 ; CHECK: [[ARG1:%[0-9]+]](s192) = G_INSERT [[ARG0]], [[I64]](s64), 64
70 ; CHECK: [[ARG2:%[0-9]+]](s192) = G_INSERT [[ARG1]], [[I8]](s8), 128
71 ; CHECK: [[ARG:%[0-9]+]](s192) = COPY [[ARG2]]
61 ; CHECK: [[DBL:%[0-9]+]]:_(s64) = COPY %d0
62 ; CHECK: [[I64:%[0-9]+]]:_(s64) = COPY %x0
63 ; CHECK: [[I8_C:%[0-9]+]]:_(s32) = COPY %w1
64 ; CHECK: [[I8:%[0-9]+]]:_(s8) = G_TRUNC [[I8_C]]
65 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
66
67 ; CHECK: [[UNDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
68 ; CHECK: [[ARG0:%[0-9]+]]:_(s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0
69 ; CHECK: [[ARG1:%[0-9]+]]:_(s192) = G_INSERT [[ARG0]], [[I64]](s64), 64
70 ; CHECK: [[ARG2:%[0-9]+]]:_(s192) = G_INSERT [[ARG1]], [[I8]](s8), 128
71 ; CHECK: [[ARG:%[0-9]+]]:_(s192) = COPY [[ARG2]]
7272
7373 ; CHECK: G_STORE [[ARG]](s192), [[ADDR]](p0)
7474 ; CHECK: RET_ReallyLR
7979
8080
8181 ; CHECK-LABEL: name: test_struct_return
82 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
83 ; CHECK: [[VAL:%[0-9]+]](s192) = G_LOAD [[ADDR]](p0)
84
85 ; CHECK: [[DBL:%[0-9]+]](s64) = G_EXTRACT [[VAL]](s192), 0
86 ; CHECK: [[I64:%[0-9]+]](s64) = G_EXTRACT [[VAL]](s192), 64
87 ; CHECK: [[I32:%[0-9]+]](s32) = G_EXTRACT [[VAL]](s192), 128
82 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
83 ; CHECK: [[VAL:%[0-9]+]]:_(s192) = G_LOAD [[ADDR]](p0)
84
85 ; CHECK: [[DBL:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 0
86 ; CHECK: [[I64:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 64
87 ; CHECK: [[I32:%[0-9]+]]:_(s32) = G_EXTRACT [[VAL]](s192), 128
8888
8989 ; CHECK: %d0 = COPY [[DBL]](s64)
9090 ; CHECK: %x0 = COPY [[I64]](s64)
9797
9898 ; CHECK-LABEL: name: test_arr_call
9999 ; CHECK: hasCalls: true
100 ; CHECK: [[ARG:%[0-9]+]](s256) = G_LOAD
101
102 ; CHECK: [[E0:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 0
103 ; CHECK: [[E1:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 64
104 ; CHECK: [[E2:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 128
105 ; CHECK: [[E3:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 192
100 ; CHECK: [[ARG:%[0-9]+]]:_(s256) = G_LOAD
101
102 ; CHECK: [[E0:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 0
103 ; CHECK: [[E1:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 64
104 ; CHECK: [[E2:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 128
105 ; CHECK: [[E3:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 192
106106
107107 ; CHECK: %x0 = COPY [[E0]](s64)
108108 ; CHECK: %x1 = COPY [[E1]](s64)
109109 ; CHECK: %x2 = COPY [[E2]](s64)
110110 ; CHECK: %x3 = COPY [[E3]](s64)
111111 ; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2, implicit %x3, implicit-def %x0, implicit-def %x1, implicit-def %x2, implicit-def %x3
112 ; CHECK: [[E0:%[0-9]+]](s64) = COPY %x0
113 ; CHECK: [[E1:%[0-9]+]](s64) = COPY %x1
114 ; CHECK: [[E2:%[0-9]+]](s64) = COPY %x2
115 ; CHECK: [[E3:%[0-9]+]](s64) = COPY %x3
116 ; CHECK: [[RES:%[0-9]+]](s256) = G_MERGE_VALUES [[E0]](s64), [[E1]](s64), [[E2]](s64), [[E3]](s64)
112 ; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY %x0
113 ; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY %x1
114 ; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY %x2
115 ; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY %x3
116 ; CHECK: [[RES:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[E0]](s64), [[E1]](s64), [[E2]](s64), [[E3]](s64)
117117 ; CHECK: G_EXTRACT [[RES]](s256), 64
118118 declare [4 x i64] @arr_callee([4 x i64])
119119 define i64 @test_arr_call([4 x i64]* %addr) {
125125
126126
127127 ; CHECK-LABEL: name: test_abi_exts_call
128 ; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD
129 ; CHECK: [[VAL_TMP:%[0-9]+]](s32) = G_ANYEXT [[VAL]]
128 ; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
129 ; CHECK: [[VAL_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[VAL]]
130130 ; CHECK: %w0 = COPY [[VAL_TMP]]
131131 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
132 ; CHECK: [[SVAL:%[0-9]+]](s32) = G_SEXT [[VAL]](s8)
132 ; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
133133 ; CHECK: %w0 = COPY [[SVAL]](s32)
134134 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
135 ; CHECK: [[ZVAL:%[0-9]+]](s32) = G_ZEXT [[VAL]](s8)
135 ; CHECK: [[ZVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
136136 ; CHECK: %w0 = COPY [[ZVAL]](s32)
137137 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
138138 declare void @take_char(i8)
145145 }
146146
147147 ; CHECK-LABEL: name: test_abi_sext_ret
148 ; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD
149 ; CHECK: [[SVAL:%[0-9]+]](s32) = G_SEXT [[VAL]](s8)
148 ; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
149 ; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
150150 ; CHECK: %w0 = COPY [[SVAL]](s32)
151151 ; CHECK: RET_ReallyLR implicit %w0
152152 define signext i8 @test_abi_sext_ret(i8* %addr) {
155155 }
156156
157157 ; CHECK-LABEL: name: test_abi_zext_ret
158 ; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD
159 ; CHECK: [[SVAL:%[0-9]+]](s32) = G_ZEXT [[VAL]](s8)
158 ; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
159 ; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
160160 ; CHECK: %w0 = COPY [[SVAL]](s32)
161161 ; CHECK: RET_ReallyLR implicit %w0
162162 define zeroext i8 @test_abi_zext_ret(i8* %addr) {
169169 ; CHECK-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8,
170170 ; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8,
171171 ; CHECK-DAG: - { id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 8,
172 ; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
173 ; CHECK: [[LHS:%[0-9]+]](s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
174 ; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
175 ; CHECK: [[RHS:%[0-9]+]](s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
176 ; CHECK: [[ADDR_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
177 ; CHECK: [[ADDR:%[0-9]+]](p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK16]], align 0)
178 ; CHECK: [[SUM:%[0-9]+]](s64) = G_ADD [[LHS]], [[RHS]]
172 ; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
173 ; CHECK: [[LHS:%[0-9]+]]:_(s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
174 ; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
175 ; CHECK: [[RHS:%[0-9]+]]:_(s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
176 ; CHECK: [[ADDR_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
177 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK16]], align 0)
178 ; CHECK: [[SUM:%[0-9]+]]:_(s64) = G_ADD [[LHS]], [[RHS]]
179179 ; CHECK: G_STORE [[SUM]](s64), [[ADDR]](p0)
180180 define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
181181 %sum = add i64 %lhs, %rhs
184184 }
185185
186186 ; CHECK-LABEL: name: test_call_stack
187 ; CHECK: [[C42:%[0-9]+]](s64) = G_CONSTANT i64 42
188 ; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
189 ; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
187 ; CHECK: [[C42:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
188 ; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
189 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
190190 ; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def %sp, implicit %sp
191 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
192 ; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
193 ; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
191 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
192 ; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
193 ; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
194194 ; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store 8 into stack, align 0)
195 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
196 ; CHECK: [[C12_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 8
197 ; CHECK: [[C12_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
195 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
196 ; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
197 ; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
198198 ; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store 8 into stack + 8, align 0)
199 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
200 ; CHECK: [[PTR_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 16
201 ; CHECK: [[PTR_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[PTR_OFFS]](s64)
199 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
200 ; CHECK: [[PTR_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
201 ; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[PTR_OFFS]](s64)
202202 ; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store 8 into stack + 16, align 0)
203203 ; CHECK: BL @test_stack_slots
204204 ; CHECK: ADJCALLSTACKUP 24, 0, implicit-def %sp, implicit %sp
211211 ; CHECK: fixedStack:
212212 ; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, stack-id: 0,
213213 ; CHECK-NEXT: isImmutable: true,
214 ; CHECK: [[ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
215 ; CHECK: {{%[0-9]+}}(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0)
214 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
215 ; CHECK: {{%[0-9]+}}:_(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0)
216216 define void @test_mem_i1([8 x i64], i1 %in) {
217217 ret void
218218 }
229229 }
230230
231231 ; CHECK-LABEL: name: take_128bit_struct
232 ; CHECK: {{%.*}}(p0) = COPY %x0
233 ; CHECK: {{%.*}}(s64) = COPY %x1
234 ; CHECK: {{%.*}}(s64) = COPY %x2
232 ; CHECK: {{%.*}}:_(p0) = COPY %x0
233 ; CHECK: {{%.*}}:_(s64) = COPY %x1
234 ; CHECK: {{%.*}}:_(s64) = COPY %x2
235235 define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
236236 store [2 x i64] %in, [2 x i64]* %ptr
237237 ret void
238238 }
239239
240240 ; CHECK-LABEL: name: test_split_struct
241 ; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD {{.*}}(p0)
242 ; CHECK: [[LO:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 0
243 ; CHECK: [[HI:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 64
244
245 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
246 ; CHECK: [[OFF:%[0-9]+]](s64) = G_CONSTANT i64 0
247 ; CHECK: [[ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF]]
241 ; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD {{.*}}(p0)
242 ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 0
243 ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 64
244
245 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
246 ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
247 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
248248 ; CHECK: G_STORE [[LO]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0)
249249
250 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
251 ; CHECK: [[OFF:%[0-9]+]](s64) = G_CONSTANT i64 8
252 ; CHECK: [[ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF]]
250 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
251 ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
252 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
253253 ; CHECK: G_STORE [[HI]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0)
254254 define void @test_split_struct([2 x i64]* %ptr) {
255255 %struct = load [2 x i64], [2 x i64]* %ptr
264264 ; CHECK-DAG: - { id: [[LO_FRAME:[0-9]+]], type: default, offset: 0, size: 8
265265 ; CHECK-DAG: - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8
266266
267 ; CHECK: [[LOPTR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
268 ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0)
269
270 ; CHECK: [[HIPTR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
271 ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0)
267 ; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
268 ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0)
269
270 ; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
271 ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0)
272272 define void @take_split_struct([2 x i64]* %ptr, i64, i64, i64,
273273 i64, i64, i64,
274274 [2 x i64] %in) {
22
33 ; CHECK-LABEL: name: debug_declare
44 ; CHECK: stack:
5 ; CHECK: - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
5 ; CHECK: - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
66 ; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true,
77 ; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()',
88 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !DIExpression(), debug-location !12
2525 }
2626
2727 ; CHECK-LABEL: name: debug_value
28 ; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
28 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
2929 define void @debug_value(i32 %in) #0 !dbg !16 {
3030 %addr = alloca i32
3131 ; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use _, !17, !DIExpression(), debug-location !18
0 ; RUN: llc -mtriple=aarch64 -global-isel %s -o - -stop-after=irtranslator | FileCheck %s
11
22 ; CHECK-LABEL: name: test_simple_alloca
3 ; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0
4 ; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -1
5 ; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32)
6 ; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
7 ; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp
8 ; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
9 ; CHECK: [[ALIGNED_ALLOC:%[0-9]+]](p0) = G_PTR_MASK [[ALLOC]], 4
3 ; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
4 ; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
5 ; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
6 ; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
7 ; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
8 ; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
9 ; CHECK: [[ALIGNED_ALLOC:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALLOC]], 4
1010 ; CHECK: %sp = COPY [[ALIGNED_ALLOC]]
11 ; CHECK: [[ALLOC:%[0-9]+]](p0) = COPY [[ALIGNED_ALLOC]]
11 ; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = COPY [[ALIGNED_ALLOC]]
1212 ; CHECK: %x0 = COPY [[ALLOC]]
1313 define i8* @test_simple_alloca(i32 %numelts) {
1414 %addr = alloca i8, i32 %numelts
1616 }
1717
1818 ; CHECK-LABEL: name: test_aligned_alloca
19 ; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0
20 ; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -1
21 ; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32)
22 ; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
23 ; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp
24 ; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
25 ; CHECK: [[ALIGNED_ALLOC:%[0-9]+]](p0) = G_PTR_MASK [[ALLOC]], 5
19 ; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
20 ; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
21 ; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
22 ; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
23 ; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
24 ; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
25 ; CHECK: [[ALIGNED_ALLOC:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALLOC]], 5
2626 ; CHECK: %sp = COPY [[ALIGNED_ALLOC]]
27 ; CHECK: [[ALLOC:%[0-9]+]](p0) = COPY [[ALIGNED_ALLOC]]
27 ; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = COPY [[ALIGNED_ALLOC]]
2828 ; CHECK: %x0 = COPY [[ALLOC]]
2929 define i8* @test_aligned_alloca(i32 %numelts) {
3030 %addr = alloca i8, i32 %numelts, align 32
3232 }
3333
3434 ; CHECK-LABEL: name: test_natural_alloca
35 ; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0
36 ; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -16
37 ; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32)
38 ; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
39 ; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp
40 ; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
35 ; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
36 ; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
37 ; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
38 ; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
39 ; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
40 ; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
4141 ; CHECK: %sp = COPY [[ALLOC]]
42 ; CHECK: [[ALLOC_TMP:%[0-9]+]](p0) = COPY [[ALLOC]]
42 ; CHECK: [[ALLOC_TMP:%[0-9]+]]:_(p0) = COPY [[ALLOC]]
4343 ; CHECK: %x0 = COPY [[ALLOC_TMP]]
4444 define i128* @test_natural_alloca(i32 %numelts) {
4545 %addr = alloca i128, i32 %numelts
2222 %tmp15 = add i32 30, 30
2323
2424 ; At this point we mapped 46 values. The 'i32 100' constant will grow the map.
25 ; CHECK: %46(s32) = G_CONSTANT i32 100
25 ; CHECK: %46:_(s32) = G_CONSTANT i32 100
2626 ; CHECK: %w0 = COPY %46(s32)
2727 %res = bitcast i32 100 to i32
2828 ret i32 %res
1212 ; CHECK: EH_LABEL
1313 ; CHECK: %w0 = COPY
1414 ; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
15 ; CHECK: {{%[0-9]+}}(s32) = COPY %w0
15 ; CHECK: {{%[0-9]+}}:_(s32) = COPY %w0
1616 ; CHECK: EH_LABEL
1717 ; CHECK: G_BR %[[GOOD]]
1818
1919 ; CHECK: [[BAD]] (landing-pad):
2020 ; CHECK: EH_LABEL
21 ; CHECK: [[UNDEF:%[0-9]+]](s128) = G_IMPLICIT_DEF
22 ; CHECK: [[PTR:%[0-9]+]](p0) = COPY %x0
23 ; CHECK: [[VAL_WITH_PTR:%[0-9]+]](s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0
24 ; CHECK: [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
25 ; CHECK: [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]]
26 ; CHECK: [[PTR_SEL:%[0-9]+]](s128) = G_INSERT [[VAL_WITH_PTR]], [[SEL]](s32), 64
27 ; CHECK: [[PTR_RET:%[0-9]+]](s64) = G_EXTRACT [[PTR_SEL]](s128), 0
28 ; CHECK: [[SEL_RET:%[0-9]+]](s32) = G_EXTRACT [[PTR_SEL]](s128), 64
21 ; CHECK: [[UNDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
22 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0
23 ; CHECK: [[VAL_WITH_PTR:%[0-9]+]]:_(s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0
24 ; CHECK: [[SEL_PTR:%[0-9]+]]:_(p0) = COPY %x1
25 ; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
26 ; CHECK: [[PTR_SEL:%[0-9]+]]:_(s128) = G_INSERT [[VAL_WITH_PTR]], [[SEL]](s32), 64
27 ; CHECK: [[PTR_RET:%[0-9]+]]:_(s64) = G_EXTRACT [[PTR_SEL]](s128), 0
28 ; CHECK: [[SEL_RET:%[0-9]+]]:_(s32) = G_EXTRACT [[PTR_SEL]](s128), 64
2929 ; CHECK: %x0 = COPY [[PTR_RET]]
3030 ; CHECK: %w1 = COPY [[SEL_RET]]
3131
3232 ; CHECK: [[GOOD]]:
33 ; CHECK: [[SEL:%[0-9]+]](s32) = G_CONSTANT i32 1
34 ; CHECK: {{%[0-9]+}}(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64
33 ; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
34 ; CHECK: {{%[0-9]+}}:_(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64
3535
3636 define { i8*, i32 } @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
3737 %res32 = invoke i32 @foo(i32 42) to label %continue unwind label %broken
4848 }
4949
5050 ; CHECK-LABEL: name: test_invoke_indirect
51 ; CHECK: [[CALLEE:%[0-9]+]](p0) = COPY %x0
51 ; CHECK: [[CALLEE:%[0-9]+]]:gpr64(p0) = COPY %x0
5252 ; CHECK: BLR [[CALLEE]]
5353 define void @test_invoke_indirect(void()* %callee) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
5454 invoke void %callee() to label %continue unwind label %broken
6363
6464 ; CHECK-LABEL: name: test_invoke_varargs
6565
66 ; CHECK: [[NULL:%[0-9]+]](p0) = G_CONSTANT i64 0
67 ; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
68 ; CHECK: [[ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.0
66 ; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
67 ; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
68 ; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.0
6969
7070 ; CHECK: %x0 = COPY [[NULL]]
7171
72 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
73 ; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 0
74 ; CHECK: [[SLOT:%[0-9]+]](p0) = G_GEP [[SP]], [[OFFSET]](s64)
72 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
73 ; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
74 ; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFFSET]](s64)
7575 ; CHECK: G_STORE [[ANSWER]](s32), [[SLOT]]
7676
77 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
78 ; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 8
79 ; CHECK: [[SLOT:%[0-9]+]](p0) = G_GEP [[SP]], [[OFFSET]](s64)
77 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
78 ; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
79 ; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFFSET]](s64)
8080 ; CHECK: G_STORE [[ONE]](s32), [[SLOT]]
8181
8282 ; CHECK: BL @printf
3434 liveins: %x0, %x1, %x2, %x3
3535
3636 ; CHECK-LABEL: name: test_scalar_add_big
37 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
38 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
39 ; CHECK: [[COPY2:%[0-9]+]](s64) = COPY %x2
40 ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY %x3
41 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
42 ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[C]](s32)
43 ; CHECK: [[UADDE:%[0-9]+]](s64), [[UADDE1:%[0-9]+]](s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
44 ; CHECK: [[UADDE2:%[0-9]+]](s64), [[UADDE3:%[0-9]+]](s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
37 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
38 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
39 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %x2
40 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY %x3
41 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
42 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
43 ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
44 ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
4545 ; CHECK: %x0 = COPY [[UADDE]](s64)
4646 ; CHECK: %x1 = COPY [[UADDE2]](s64)
4747 %0(s64) = COPY %x0
7070 liveins: %x0, %x1, %x2, %x3
7171
7272 ; CHECK-LABEL: name: test_scalar_add_small
73 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
74 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
75 ; CHECK: [[TRUNC:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
76 ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
77 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[TRUNC]], [[TRUNC1]]
78 ; CHECK: [[TRUNC2:%[0-9]+]](s8) = G_TRUNC [[ADD]](s32)
79 ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC2]](s8)
73 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
74 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
75 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
76 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
77 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
78 ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]](s32)
79 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
8080 ; CHECK: %x0 = COPY [[ANYEXT]](s64)
8181 %0(s64) = COPY %x0
8282 %1(s64) = COPY %x1
104104 liveins: %q0, %q1, %q2, %q3
105105
106106 ; CHECK-LABEL: name: test_vector_add
107 ; CHECK: [[COPY:%[0-9]+]](<2 x s64>) = COPY %q0
108 ; CHECK: [[COPY1:%[0-9]+]](<2 x s64>) = COPY %q1
109 ; CHECK: [[COPY2:%[0-9]+]](<2 x s64>) = COPY %q2
110 ; CHECK: [[COPY3:%[0-9]+]](<2 x s64>) = COPY %q3
111 ; CHECK: [[ADD:%[0-9]+]](<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
112 ; CHECK: [[ADD1:%[0-9]+]](<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
107 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY %q0
108 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY %q1
109 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY %q2
110 ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY %q3
111 ; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
112 ; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
113113 ; CHECK: %q0 = COPY [[ADD]](<2 x s64>)
114114 ; CHECK: %q1 = COPY [[ADD1]](<2 x s64>)
115115 %0(<2 x s64>) = COPY %q0
2323 liveins: %x0, %x1, %x2, %x3
2424
2525 ; CHECK-LABEL: name: test_scalar_and_small
26 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
27 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
28 ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s64)
29 ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
30 ; CHECK: [[TRUNC2:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
31 ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[TRUNC1]], [[TRUNC2]]
32 ; CHECK: [[TRUNC3:%[0-9]+]](s8) = G_TRUNC [[AND]](s32)
33 ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC]](s8)
26 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
27 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
28 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
29 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
30 ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
31 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[TRUNC2]]
32 ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[AND]](s32)
33 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s8)
3434 ; CHECK: %x0 = COPY [[ANYEXT]](s64)
3535 %0(s64) = COPY %x0
3636 %1(s64) = COPY %x1
3131 %2(s8) = G_TRUNC %0
3232 %3(s8) = G_TRUNC %1
3333
34 ; CHECK: [[CMP1:%[0-9]+]](s32) = G_ICMP intpred(sge), %0(s64), %1
35 ; CHECK: [[CMP_T1:%[0-9]+]](s1) = G_TRUNC [[CMP1]]
34 ; CHECK: [[CMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %0(s64), %1
35 ; CHECK: [[CMP_T1:%[0-9]+]]:_(s1) = G_TRUNC [[CMP1]]
3636 %4(s1) = G_ICMP intpred(sge), %0, %1
3737
38 ; CHECK: [[CSTMASK1:%[0-9]+]](s32) = G_CONSTANT i32 255
39 ; CHECK: [[T1:%[0-9]+]](s32) = G_TRUNC %0(s64)
40 ; CHECK: [[AND1:%[0-9]+]](s32) = G_AND [[T1]], [[CSTMASK1]]
41 ; CHECK: [[CSTMASK2:%[0-9]+]](s32) = G_CONSTANT i32 255
42 ; CHECK: [[T2:%[0-9]+]](s32) = G_TRUNC %1(s64)
43 ; CHECK: [[AND2:%[0-9]+]](s32) = G_AND [[T2]], [[CSTMASK2]]
44 ; CHECK: [[CMP2:%[0-9]+]](s32) = G_ICMP intpred(ult), [[AND1]](s32), [[AND2]]
45 ; CHECK: [[CMP_T2:%[0-9]+]](s1) = G_TRUNC [[CMP2]]
38 ; CHECK: [[CSTMASK1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
39 ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_TRUNC %0(s64)
40 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[T1]], [[CSTMASK1]]
41 ; CHECK: [[CSTMASK2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
42 ; CHECK: [[T2:%[0-9]+]]:_(s32) = G_TRUNC %1(s64)
43 ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[T2]], [[CSTMASK2]]
44 ; CHECK: [[CMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[AND2]]
45 ; CHECK: [[CMP_T2:%[0-9]+]]:_(s1) = G_TRUNC [[CMP2]]
4646 %8(s1) = G_ICMP intpred(ult), %2, %3
4747
4848 %9(p0) = G_INTTOPTR %0(s64)
1818
1919 ; Here the types don't match.
2020 ; CHECK-LABEL: name: test_combines_2
21 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
22 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
23 ; CHECK: [[MV:%[0-9]+]](s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
24 ; CHECK: [[EXTRACT:%[0-9]+]](s1) = G_EXTRACT [[MV]](s64), 0
25 ; CHECK: [[EXTRACT1:%[0-9]+]](s64) = G_EXTRACT [[MV]](s64), 0
21 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
22 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
23 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
24 ; CHECK: [[EXTRACT:%[0-9]+]]:_(s1) = G_EXTRACT [[MV]](s64), 0
25 ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[MV]](s64), 0
2626 %0:_(s32) = COPY %w0
2727
2828 %1:_(s32) = G_ADD %0, %0
3838 liveins: %w0
3939
4040 ; CHECK-LABEL: name: test_combines_3
41 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
42 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
43 ; CHECK: [[ADD1:%[0-9]+]](s32) = G_ADD [[COPY]], [[ADD]]
41 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
42 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
43 ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
4444 %0:_(s32) = COPY %w0
4545
4646 %1:_(s32) = G_ADD %0, %0
5656 liveins: %x0
5757
5858 ; CHECK-LABEL: name: test_combines_4
59 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
60 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY [[COPY]](s64)
61 ; CHECK: [[ADD:%[0-9]+]](s64) = G_ADD [[COPY1]], [[COPY1]]
59 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
60 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
61 ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[COPY1]]
6262 %0:_(s64) = COPY %x0
6363
6464 %1:_(s128) = G_MERGE_VALUES %0, %0
7373 liveins: %w0
7474
7575 ; CHECK-LABEL: name: test_combines_5
76 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
77 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
78 ; CHECK: [[ADD1:%[0-9]+]](s32) = G_ADD [[COPY]], [[ADD]]
76 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
77 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
78 ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
7979 %0:_(s32) = COPY %w0
8080
8181 %1:_(s32) = G_ADD %0, %0
9292
9393 ; Check that we replace all the uses of a G_EXTRACT.
9494 ; CHECK-LABEL: name: test_combines_6
95 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
96 ; CHECK: [[MUL:%[0-9]+]](s32) = G_MUL [[COPY]], [[COPY]]
97 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[MUL]]
95 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
96 ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY]]
97 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[MUL]]
9898 %0:_(s32) = COPY %w0
9999
100100 %1:_(s32) = G_MERGE_VALUES %0
2828 bb.0.entry:
2929
3030 ; CHECK-LABEL: name: test_constant
31 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
32 ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[C]](s32)
33 ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 42
34 ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[C1]](s32)
35 ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 -1
36 ; CHECK: [[TRUNC2:%[0-9]+]](s16) = G_TRUNC [[C2]](s32)
37 ; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 -1
38 ; CHECK: [[C4:%[0-9]+]](s64) = G_CONSTANT i64 1
39 ; CHECK: [[C5:%[0-9]+]](s64) = G_CONSTANT i64 0
31 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
32 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
33 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
34 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C1]](s32)
35 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
36 ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
37 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
38 ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
39 ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
4040 %0(s1) = G_CONSTANT i1 0
4141 %1(s8) = G_CONSTANT i8 42
4242 %2(s16) = G_CONSTANT i16 65535
5555 bb.0.entry:
5656
5757 ; CHECK-LABEL: name: test_fconstant
58 ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
59 ; CHECK: [[C1:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
60 ; CHECK: [[C2:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000
61 ; CHECK: [[FPTRUNC:%[0-9]+]](s16) = G_FPTRUNC [[C2]](s32)
58 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
59 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
60 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT half 0xH0000
61 ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C2]](s32)
6262 %0(s32) = G_FCONSTANT float 1.0
6363 %1(s64) = G_FCONSTANT double 2.0
6464 %2(s16) = G_FCONSTANT half 0.0
7272 bb.0:
7373
7474 ; CHECK-LABEL: name: test_global
75 ; CHECK: [[GV:%[0-9]+]](p0) = G_GLOBAL_VALUE @var
75 ; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var
7676 %0(p0) = G_GLOBAL_VALUE @var
7777 ...
2525 %2(s8) = G_TRUNC %0
2626 %3(s8) = G_TRUNC %1
2727
28 ; CHECK: [[A:%.*]](s64) = COPY %x0
29 ; CHECK: [[B:%.*]](s64) = COPY %x1
30 ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 24
31 ; CHECK: [[S1:%.*]](s32) = G_TRUNC [[A]]
32 ; CHECK: [[SHL1:%.*]](s32) = G_SHL [[S1]], [[C1]]
33 ; CHECK: [[SEXT1:%.*]](s32) = G_ASHR [[SHL1]], [[C1]]
34 ; CHECK: [[C2:%.*]](s32) = G_CONSTANT i32 24
35 ; CHECK: [[S2:%.*]](s32) = G_TRUNC [[B]]
36 ; CHECK: [[SHL2:%.*]](s32) = G_SHL [[S2]], [[C2]]
37 ; CHECK: [[SEXT2:%.*]](s32) = G_ASHR [[SHL2]], [[C2]]
38 ; CHECK: [[DIV:%.*]](s32) = G_SDIV [[SEXT1]], [[SEXT2]]
39 ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[DIV]]
28 ; CHECK: [[A:%.*]]:_(s64) = COPY %x0
29 ; CHECK: [[B:%.*]]:_(s64) = COPY %x1
30 ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 24
31 ; CHECK: [[S1:%.*]]:_(s32) = G_TRUNC [[A]]
32 ; CHECK: [[SHL1:%.*]]:_(s32) = G_SHL [[S1]], [[C1]]
33 ; CHECK: [[SEXT1:%.*]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
34 ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 24
35 ; CHECK: [[S2:%.*]]:_(s32) = G_TRUNC [[B]]
36 ; CHECK: [[SHL2:%.*]]:_(s32) = G_SHL [[S2]], [[C2]]
37 ; CHECK: [[SEXT2:%.*]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
38 ; CHECK: [[DIV:%.*]]:_(s32) = G_SDIV [[SEXT1]], [[SEXT2]]
39 ; CHECK: [[RES:%.*]]:_(s8) = G_TRUNC [[DIV]]
4040
4141 %4(s8) = G_SDIV %2, %3
4242
4343
44 ; CHECK: [[CMASK1:%.*]](s32) = G_CONSTANT i32 255
45 ; CHECK: [[T1:%.*]](s32) = G_TRUNC [[A]]
46 ; CHECK: [[LHS32:%.*]](s32) = G_AND [[T1]], [[CMASK1]]
47 ; CHECK: [[CMASK2:%.*]](s32) = G_CONSTANT i32 255
48 ; CHECK: [[T2:%.*]](s32) = G_TRUNC [[B]]
49 ; CHECK: [[RHS32:%.*]](s32) = G_AND [[T2]], [[CMASK2]]
50 ; CHECK: [[QUOT32:%[0-9]+]](s32) = G_UDIV [[LHS32]], [[RHS32]]
51 ; CHECK: [[RES:%[0-9]+]](s8) = G_TRUNC [[QUOT32]]
44 ; CHECK: [[CMASK1:%.*]]:_(s32) = G_CONSTANT i32 255
45 ; CHECK: [[T1:%.*]]:_(s32) = G_TRUNC [[A]]
46 ; CHECK: [[LHS32:%.*]]:_(s32) = G_AND [[T1]], [[CMASK1]]
47 ; CHECK: [[CMASK2:%.*]]:_(s32) = G_CONSTANT i32 255
48 ; CHECK: [[T2:%.*]]:_(s32) = G_TRUNC [[B]]
49 ; CHECK: [[RHS32:%.*]]:_(s32) = G_AND [[T2]], [[CMASK2]]
50 ; CHECK: [[QUOT32:%[0-9]+]]:_(s32) = G_UDIV [[LHS32]], [[RHS32]]
51 ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_TRUNC [[QUOT32]]
5252 %5(s8) = G_UDIV %2, %3
5353
5454 ...
1414 ; CHECK: [[LP]] (landing-pad):
1515 ; CHECK: EH_LABEL
1616
17 ; CHECK: [[PTR:%[0-9]+]](p0) = COPY %x0
18 ; CHECK: [[STRUCT_PTR:%[0-9]+]](s64) = G_PTRTOINT [[PTR]](p0)
17 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0
18 ; CHECK: [[STRUCT_PTR:%[0-9]+]]:_(s64) = G_PTRTOINT [[PTR]](p0)
1919
20 ; CHECK: [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
21 ; CHECK: [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]]
22 ; CHECK: [[STRUCT_SEL:%[0-9]+]](s64) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 0
20 ; CHECK: [[SEL_PTR:%[0-9]+]]:_(p0) = COPY %x1
21 ; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
22 ; CHECK: [[STRUCT_SEL:%[0-9]+]]:_(s64) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 0
2323
24 ; CHECK: [[PTR:%[0-9]+]](p0) = G_INTTOPTR [[STRUCT_PTR]](s64)
24 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[STRUCT_PTR]](s64)
2525 ; CHECK: G_STORE [[PTR]](p0), {{%[0-9]+}}(p0)
2626
27 ; CHECK: [[SEL_TMP:%[0-9]+]](s32) = G_EXTRACT [[STRUCT_SEL]](s64), 0
28 ; CHECK: [[SEL:%[0-9]+]](s32) = COPY [[SEL_TMP]]
27 ; CHECK: [[SEL_TMP:%[0-9]+]]:_(s32) = G_EXTRACT [[STRUCT_SEL]](s64), 0
28 ; CHECK: [[SEL:%[0-9]+]]:_(s32) = COPY [[SEL_TMP]]
2929 ; CHECK: G_STORE [[SEL]](s32), {{%[0-9]+}}(p0)
3030
3131 define void @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
3535 liveins: %x0, %x1, %x2, %x3
3636 %0(s64) = COPY %x0
3737
38 ; CHECK: %1(s1) = G_TRUNC %0
39 ; CHECK: %2(s8) = G_TRUNC %0
40 ; CHECK: %3(s16) = G_TRUNC %0
41 ; CHECK: %4(s32) = G_TRUNC %0
38 ; CHECK: %1:_(s1) = G_TRUNC %0
39 ; CHECK: %2:_(s8) = G_TRUNC %0
40 ; CHECK: %3:_(s16) = G_TRUNC %0
41 ; CHECK: %4:_(s32) = G_TRUNC %0
4242 %1(s1) = G_TRUNC %0
4343 %2(s8) = G_TRUNC %0
4444 %3(s16) = G_TRUNC %0
4545 %4(s32) = G_TRUNC %0
4646
47 ; CHECK: %5(s64) = G_ANYEXT %1
48 ; CHECK: %6(s64) = G_ZEXT %2
49 ; CHECK: %7(s64) = G_ANYEXT %3
50 ; CHECK: %8(s64) = G_SEXT %4
47 ; CHECK: %5:_(s64) = G_ANYEXT %1
48 ; CHECK: %6:_(s64) = G_ZEXT %2
49 ; CHECK: %7:_(s64) = G_ANYEXT %3
50 ; CHECK: %8:_(s64) = G_SEXT %4
5151 %5(s64) = G_ANYEXT %1
5252 %6(s64) = G_ZEXT %2
5353 %7(s64) = G_ANYEXT %3
5454 %8(s64) = G_SEXT %4
5555
56 ; CHECK: %9(s32) = G_SEXT %1
57 ; CHECK: %10(s32) = G_ZEXT %2
58 ; CHECK: %11(s32) = G_ANYEXT %3
56 ; CHECK: %9:_(s32) = G_SEXT %1
57 ; CHECK: %10:_(s32) = G_ZEXT %2
58 ; CHECK: %11:_(s32) = G_ANYEXT %3
5959 %9(s32) = G_SEXT %1
6060 %10(s32) = G_ZEXT %2
6161 %11(s32) = G_ANYEXT %3
6262
63 ; CHECK: %12(s32) = G_ZEXT %1
64 ; CHECK: %13(s32) = G_ANYEXT %2
65 ; CHECK: %14(s32) = G_SEXT %3
63 ; CHECK: %12:_(s32) = G_ZEXT %1
64 ; CHECK: %13:_(s32) = G_ANYEXT %2
65 ; CHECK: %14:_(s32) = G_SEXT %3
6666 %12(s32) = G_ZEXT %1
6767 %13(s32) = G_ANYEXT %2
6868 %14(s32) = G_SEXT %3
6969
70 ; CHECK: %15(s8) = G_ZEXT %1
71 ; CHECK: %16(s16) = G_ANYEXT %2
70 ; CHECK: %15:_(s8) = G_ZEXT %1
71 ; CHECK: %16:_(s16) = G_ANYEXT %2
7272 %15(s8) = G_ZEXT %1
7373 %16(s16) = G_ANYEXT %2
7474
75 ; CHECK: %18(s64) = G_FPEXT %17
75 ; CHECK: %18:_(s64) = G_FPEXT %17
7676 %17(s32) = G_TRUNC %0
7777 %18(s64) = G_FPEXT %17
7878 ...