llvm.org GIT mirror llvm / ed74482
Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot target all GR8 registers, only those in GR8_NOREX. TO enforce this, we ensure that all instructions using the EXTRACT_SUBREG are GR8_NOREX constrained. This fixes PR11088. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141499 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
4 changed file(s) with 54 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
21722172 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
21732173 MVT::i8, Reg);
21742174
2175 // Emit a testb. No special NOREX tricks are needed since there's
2176 // only one GPR operand!
2177 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2175 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2176 // target GR8_NOREX registers, so make sure the register class is
2177 // forced.
2178 return CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl, MVT::i32,
21782179 Subreg, ShiftedImm);
21792180 }
21802181
11441144 "{$src, %eax|EAX, $src}">;
11451145 def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX,
11461146 "{$src, %rax|RAX, $src}">;
1147
1148 // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
1149 // register class is constrained to GR8_NOREX.
1150 let isPseudo = 1 in
1151 def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask),
1152 "", []>;
11471153 }
11481154
24202420 switch (MI->getOpcode()) {
24212421 case X86::V_SET0:
24222422 return Expand2AddrUndef(MI, get(HasAVX ? X86::VPXORrr : X86::PXORrr));
2423 case X86::TEST8ri_NOREX:
2424 MI->setDesc(get(X86::TEST8ri));
2425 return true;
24232426 }
24242427 return false;
24252428 }
0 ; RUN: llc -O0 < %s
1 ; RUN: llc < %s
12 target triple = "x86_64-apple-macosx10.7"
23
34 ; This test case extracts a sub_8bit_hi sub-register:
3637 store i16 %10, i16* undef, align 1
3738 ret void
3839 }
40
41 ; This test case extracts a sub_8bit_hi sub-register:
42 ;
43 ; %vreg2 = COPY %vreg1:sub_8bit_hi; GR8:%vreg2 GR64_ABCD:%vreg1
44 ; TEST8ri %vreg2, 1, %EFLAGS; GR8:%vreg2
45 ;
46 ; %vreg2 must be constrained to GR8_NOREX, or the COPY could become impossible.
47 ;
48 ; PR11088
49
50 define fastcc i32 @g(i64 %FB) nounwind uwtable readnone align 2 {
51 entry:
52 %and32 = and i64 %FB, 256
53 %cmp33 = icmp eq i64 %and32, 0
54 %Features.6.or35 = select i1 %cmp33, i32 0, i32 undef
55 %cmp38 = icmp eq i64 undef, 0
56 %or40 = or i32 %Features.6.or35, 4
57 %Features.8 = select i1 %cmp38, i32 %Features.6.or35, i32 %or40
58 %and42 = and i64 %FB, 32
59 %or45 = or i32 %Features.8, 2
60 %cmp43 = icmp eq i64 %and42, 0
61 %Features.8.or45 = select i1 %cmp43, i32 %Features.8, i32 %or45
62 %and47 = and i64 %FB, 8192
63 %cmp48 = icmp eq i64 %and47, 0
64 %or50 = or i32 %Features.8.or45, 32
65 %Features.10 = select i1 %cmp48, i32 %Features.8.or45, i32 %or50
66 %or55 = or i32 %Features.10, 64
67 %Features.10.or55 = select i1 undef, i32 %Features.10, i32 %or55
68 %and57 = lshr i64 %FB, 2
69 %and57.tr = trunc i64 %and57 to i32
70 %or60 = and i32 %and57.tr, 1
71 %Features.12 = or i32 %Features.10.or55, %or60
72 %and62 = and i64 %FB, 128
73 %or65 = or i32 %Features.12, 8
74 %cmp63 = icmp eq i64 %and62, 0
75 %Features.12.or65 = select i1 %cmp63, i32 %Features.12, i32 %or65
76 %Features.14 = select i1 undef, i32 undef, i32 %Features.12.or65
77 %Features.16 = select i1 undef, i32 undef, i32 %Features.14
78 ret i32 %Features.16
79 }