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[SystemZ, LoopStrengthReduce] This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308729 91177308-0d34-0410-b5e6-96231b3b80d8 Jonas Paulsson 3 years ago
35 changed file(s) with 303 addition(s) and 79 deletion(s). Raw diff Collapse all Expand all
419419 /// this target, for a load/store of the specified type.
420420 /// The type may be VoidTy, in which case only return true if the addressing
421421 /// mode is legal for a load/store of any legal type.
422 /// If target returns true in LSRWithInstrQueries(), I may be valid.
422423 /// TODO: Handle pre/postinc as well.
423424 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
424425 bool HasBaseReg, int64_t Scale,
425 unsigned AddrSpace = 0) const;
426 unsigned AddrSpace = 0,
427 Instruction *I = nullptr) const;
426428
427429 /// \brief Return true if LSR cost of C1 is lower than C1.
428430 bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
451453 int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
452454 bool HasBaseReg, int64_t Scale,
453455 unsigned AddrSpace = 0) const;
456
457 /// \brief Return true if the loop strength reduce pass should make
458 /// Instruction* based TTI queries to isLegalAddressingMode(). This is
459 /// needed on SystemZ, where e.g. a memcpy can only have a 12 bit unsigned
460 /// immediate offset and no index register.
461 bool LSRWithInstrQueries() const;
454462
455463 /// \brief Return true if target supports the load / store
456464 /// instruction with the given Offset on the form reg + Offset. It
881889 virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
882890 int64_t BaseOffset, bool HasBaseReg,
883891 int64_t Scale,
884 unsigned AddrSpace) = 0;
892 unsigned AddrSpace,
893 Instruction *I) = 0;
885894 virtual bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
886895 TargetTransformInfo::LSRCost &C2) = 0;
887896 virtual bool isLegalMaskedStore(Type *DataType) = 0;
892901 virtual int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
893902 int64_t BaseOffset, bool HasBaseReg,
894903 int64_t Scale, unsigned AddrSpace) = 0;
904 virtual bool LSRWithInstrQueries() = 0;
895905 virtual bool isFoldableMemAccessOffset(Instruction *I, int64_t Offset) = 0;
896906 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) = 0;
897907 virtual bool isProfitableToHoist(Instruction *I) = 0;
10841094 }
10851095 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
10861096 bool HasBaseReg, int64_t Scale,
1087 unsigned AddrSpace) override {
1097 unsigned AddrSpace,
1098 Instruction *I) override {
10881099 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
1089 Scale, AddrSpace);
1100 Scale, AddrSpace, I);
10901101 }
10911102 bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
10921103 TargetTransformInfo::LSRCost &C2) override {
11121123 unsigned AddrSpace) override {
11131124 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
11141125 Scale, AddrSpace);
1126 }
1127 bool LSRWithInstrQueries() override {
1128 return Impl.LSRWithInstrQueries();
11151129 }
11161130 bool isFoldableMemAccessOffset(Instruction *I, int64_t Offset) override {
11171131 return Impl.isFoldableMemAccessOffset(I, Offset);
229229
230230 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
231231 bool HasBaseReg, int64_t Scale,
232 unsigned AddrSpace) {
232 unsigned AddrSpace, Instruction *I = nullptr) {
233233 // Guess that only reg and reg+reg addressing is allowed. This heuristic is
234234 // taken from the implementation of LSR.
235235 return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
260260 return 0;
261261 return -1;
262262 }
263
264 bool LSRWithInstrQueries() { return false; }
263265
264266 bool isFoldableMemAccessOffset(Instruction *I, int64_t Offset) { return true; }
265267
109109
110110 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
111111 bool HasBaseReg, int64_t Scale,
112 unsigned AddrSpace) {
112 unsigned AddrSpace, Instruction *I = nullptr) {
113113 TargetLoweringBase::AddrMode AM;
114114 AM.BaseGV = BaseGV;
115115 AM.BaseOffs = BaseOffset;
116116 AM.HasBaseReg = HasBaseReg;
117117 AM.Scale = Scale;
118 return getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace);
118 return getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace, I);
119119 }
120120
121121 bool isLSRCostLess(TTI::LSRCost C1, TTI::LSRCost C2) {
18861886 ///
18871887 /// TODO: Remove default argument
18881888 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1889 Type *Ty, unsigned AddrSpace) const;
1889 Type *Ty, unsigned AddrSpace,
1890 Instruction *I = nullptr) const;
18901891
18911892 /// \brief Return the cost of the scaling factor used in the addressing mode
18921893 /// represented by AM for this target, for a load/store of the specified type.
143143 int64_t BaseOffset,
144144 bool HasBaseReg,
145145 int64_t Scale,
146 unsigned AddrSpace) const {
146 unsigned AddrSpace,
147 Instruction *I) const {
147148 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
148 Scale, AddrSpace);
149 Scale, AddrSpace, I);
149150 }
150151
151152 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
183184 return Cost;
184185 }
185186
187 bool TargetTransformInfo::LSRWithInstrQueries() const {
188 return TTIImpl->LSRWithInstrQueries();
189 }
190
186191 bool TargetTransformInfo::isFoldableMemAccessOffset(Instruction *I,
187192 int64_t Offset) const {
188193 return TTIImpl->isFoldableMemAccessOffset(I, Offset);
14801480 /// by AM is legal for this target, for a load/store of the specified type.
14811481 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
14821482 const AddrMode &AM, Type *Ty,
1483 unsigned AS) const {
1483 unsigned AS, Instruction *I) const {
14841484 // The default implementation of this implements a conservative RISCy, r+r and
14851485 // r+i addr mode.
14861486
78177817 /// by AM is legal for this target, for a load/store of the specified type.
78187818 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
78197819 const AddrMode &AM, Type *Ty,
7820 unsigned AS) const {
7820 unsigned AS, Instruction *I) const {
78217821 // AArch64 has five basic addressing modes:
78227822 // reg
78237823 // reg + 9-bit signed offset
337337 /// Return true if the addressing mode represented by AM is legal for this
338338 /// target, for a load/store of the specified type.
339339 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
340 unsigned AS) const override;
340 unsigned AS,
341 Instruction *I = nullptr) const override;
341342
342343 /// \brief Return the cost of the scaling factor used in the addressing
343344 /// mode represented by AM for this target, for a load/store
623623
624624 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
625625 const AddrMode &AM, Type *Ty,
626 unsigned AS) const {
626 unsigned AS, Instruction *I) const {
627627 // No global is ever allowed as a base.
628628 if (AM.BaseGV)
629629 return false;
150150 Type *&/*AccessTy*/) const override;
151151
152152 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
153 unsigned AS) const override;
153 unsigned AS,
154 Instruction *I = nullptr) const override;
154155
155156 bool canMergeStoresTo(unsigned AS, EVT MemVT,
156157 const SelectionDAG &DAG) const override;
1237912379 /// by AM is legal for this target, for a load/store of the specified type.
1238012380 bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
1238112381 const AddrMode &AM, Type *Ty,
12382 unsigned AS) const {
12382 unsigned AS, Instruction *I) const {
1238312383 EVT VT = getValueType(DL, Ty, true);
1238412384 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
1238512385 return false;
316316 /// isLegalAddressingMode - Return true if the addressing mode represented
317317 /// by AM is legal for this target, for a load/store of the specified type.
318318 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
319 Type *Ty, unsigned AS) const override;
319 Type *Ty, unsigned AS,
320 Instruction *I = nullptr) const override;
320321
321322 /// getScalingFactorCost - Return the cost of the scaling used in
322323 /// addressing mode represented by AM.
723723 /// by AM is legal for this target, for a load/store of the specified type.
724724 bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
725725 const AddrMode &AM, Type *Ty,
726 unsigned AS) const {
726 unsigned AS, Instruction *I) const {
727727 int64_t Offs = AM.BaseOffs;
728728
729729 // Allow absolute addresses.
8282 SelectionDAG &DAG) const override;
8383
8484 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
85 unsigned AS) const override;
85 unsigned AS,
86 Instruction *I = nullptr) const override;
8687
8788 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
8889 ISD::MemIndexedMode &AM,
29922992 /// AM is legal for this target, for a load/store of the specified type.
29932993 bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
29942994 const AddrMode &AM, Type *Ty,
2995 unsigned AS) const {
2995 unsigned AS, Instruction *I) const {
29962996 if (Ty->isSized()) {
29972997 // When LSR detects uses of the same base address to access different
29982998 // types (e.g. unions), it will assume a conservative type for these
230230 /// mode is legal for a load/store of any legal type.
231231 /// TODO: Handle pre/postinc as well.
232232 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
233 Type *Ty, unsigned AS) const override;
233 Type *Ty, unsigned AS,
234 Instruction *I = nullptr) const override;
234235 /// Return true if folding a constant offset with the given GlobalAddress
235236 /// is legal. It is frequently not legal in PIC relocation models.
236237 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
39903990
39913991 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
39923992 const AddrMode &AM, Type *Ty,
3993 unsigned AS) const {
3993 unsigned AS, Instruction *I) const {
39943994 // No global is ever allowed as a base.
39953995 if (AM.BaseGV)
39963996 return false;
624624 }
625625
626626 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
627 Type *Ty, unsigned AS) const override;
627 Type *Ty, unsigned AS,
628 Instruction *I = nullptr) const override;
628629
629630 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
630631
38043804 /// (CodeGenPrepare.cpp)
38053805 bool NVPTXTargetLowering::isLegalAddressingMode(const DataLayout &DL,
38063806 const AddrMode &AM, Type *Ty,
3807 unsigned AS) const {
3807 unsigned AS, Instruction *I) const {
38083808 // AddrMode - This represents an addressing mode of:
38093809 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
38103810 //
455455 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
456456 /// address mode (CodeGenPrepare.cpp)
457457 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
458 unsigned AS) const override;
458 unsigned AS,
459 Instruction *I = nullptr) const override;
459460
460461 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
461462 // Truncating 64-bit to 32-bit is free in SASS.
1280912809 // by AM is legal for this target, for a load/store of the specified type.
1281012810 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
1281112811 const AddrMode &AM, Type *Ty,
12812 unsigned AS) const {
12812 unsigned AS, Instruction *I) const {
1281312813 // PPC does not allow r+i addressing modes for vectors!
1281412814 if (Ty->isVectorTy() && AM.BaseOffs != 0)
1281512815 return false;
726726 /// isLegalAddressingMode - Return true if the addressing mode represented
727727 /// by AM is legal for this target, for a load/store of the specified type.
728728 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
729 Type *Ty, unsigned AS) const override;
729 Type *Ty, unsigned AS,
730 Instruction *I = nullptr) const override;
730731
731732 /// isLegalICmpImmediate - Return true if the specified immediate is legal
732733 /// icmp immediate, that is the target has icmp instructions which can
585585 return true;
586586 }
587587
588 // Information about the addressing mode for a memory access.
589 struct AddressingMode {
590 // True if a long displacement is supported.
591 bool LongDisplacement;
592
593 // True if use of index register is supported.
594 bool IndexReg;
595
596 AddressingMode(bool LongDispl, bool IdxReg) :
597 LongDisplacement(LongDispl), IndexReg(IdxReg) {}
598 };
599
600 // Return the desired addressing mode for a Load which has only one use (in
601 // the same block) which is a Store.
602 static AddressingMode getLoadStoreAddrMode(bool HasVector,
603 Type *Ty) {
604 // With vector support a Load->Store combination may be combined to either
605 // an MVC or vector operations and it seems to work best to allow the
606 // vector addressing mode.
607 if (HasVector)
608 return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
609
610 // Otherwise only the MVC case is special.
611 bool MVC = Ty->isIntegerTy(8);
612 return AddressingMode(!MVC/*LongDispl*/, !MVC/*IdxReg*/);
613 }
614
615 // Return the addressing mode which seems most desirable given an LLVM
616 // Instruction pointer.
617 static AddressingMode
618 supportedAddressingMode(Instruction *I, bool HasVector) {
619 if (IntrinsicInst *II = dyn_cast(I)) {
620 switch (II->getIntrinsicID()) {
621 default: break;
622 case Intrinsic::memset:
623 case Intrinsic::memmove:
624 case Intrinsic::memcpy:
625 return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
626 }
627 }
628
629 if (isa(I) && I->hasOneUse()) {
630 auto *SingleUser = dyn_cast(*I->user_begin());
631 if (SingleUser->getParent() == I->getParent()) {
632 if (isa(SingleUser)) {
633 if (auto *C = dyn_cast(SingleUser->getOperand(1)))
634 if (isInt<16>(C->getSExtValue()) || isUInt<16>(C->getZExtValue()))
635 // Comparison of memory with 16 bit signed / unsigned immediate
636 return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
637 } else if (isa(SingleUser))
638 // Load->Store
639 return getLoadStoreAddrMode(HasVector, I->getType());
640 }
641 } else if (auto *StoreI = dyn_cast(I)) {
642 if (auto *LoadI = dyn_cast(StoreI->getValueOperand()))
643 if (LoadI->hasOneUse() && LoadI->getParent() == I->getParent())
644 // Load->Store
645 return getLoadStoreAddrMode(HasVector, LoadI->getType());
646 }
647
648 if (HasVector && (isa(I) || isa(I))) {
649
650 // * Use LDE instead of LE/LEY for z13 to avoid partial register
651 // dependencies (LDE only supports small offsets).
652 // * Utilize the vector registers to hold floating point
653 // values (vector load / store instructions only support small
654 // offsets).
655
656 Type *MemAccessTy = (isa(I) ? I->getType() :
657 I->getOperand(0)->getType());
658 bool IsFPAccess = MemAccessTy->isFloatingPointTy();
659 bool IsVectorAccess = MemAccessTy->isVectorTy();
660
661 // A store of an extracted vector element will be combined into a VSTE type
662 // instruction.
663 if (!IsVectorAccess && isa(I)) {
664 Value *DataOp = I->getOperand(0);
665 if (isa(DataOp))
666 IsVectorAccess = true;
667 }
668
669 // A load which gets inserted into a vector element will be combined into a
670 // VLE type instruction.
671 if (!IsVectorAccess && isa(I) && I->hasOneUse()) {
672 User *LoadUser = *I->user_begin();
673 if (isa(LoadUser))
674 IsVectorAccess = true;
675 }
676
677 if (IsFPAccess || IsVectorAccess)
678 return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
679 }
680
681 return AddressingMode(true/*LongDispl*/, true/*IdxReg*/);
682 }
683
684 // TODO: This method should also check for the displacement when *I is
685 // passed. It may also be possible to merge with isFoldableMemAccessOffset()
686 // now that both methods get the *I.
588687 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL,
589 const AddrMode &AM, Type *Ty,
590 unsigned AS) const {
688 const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const {
591689 // Punt on globals for now, although they can be used in limited
592690 // RELATIVE LONG cases.
593691 if (AM.BaseGV)
597695 if (!isInt<20>(AM.BaseOffs))
598696 return false;
599697
600 // Indexing is OK but no scale factor can be applied.
601 return AM.Scale == 0 || AM.Scale == 1;
602 }
603
698 if (I != nullptr &&
699 !supportedAddressingMode(I, Subtarget.hasVector()).IndexReg)
700 // No indexing allowed.
701 return AM.Scale == 0;
702 else
703 // Indexing is OK but no scale factor can be applied.
704 return AM.Scale == 0 || AM.Scale == 1;
705 }
706
707 // TODO: Should we check for isInt<20> also?
604708 bool SystemZTargetLowering::isFoldableMemAccessOffset(Instruction *I,
605709 int64_t Offset) const {
606 // This only applies to z13.
607 if (!Subtarget.hasVector())
608 return true;
609
610 // * Use LDE instead of LE/LEY to avoid partial register
611 // dependencies (LDE only supports small offsets).
612 // * Utilize the vector registers to hold floating point
613 // values (vector load / store instructions only support small
614 // offsets).
615
616 assert (isa(I) || isa(I));
617 Type *MemAccessTy = (isa(I) ? I->getType() :
618 I->getOperand(0)->getType());
619 bool IsFPAccess = MemAccessTy->isFloatingPointTy();
620 bool IsVectorAccess = MemAccessTy->isVectorTy();
621
622 // A store of an extracted vector element will be combined into a VSTE type
623 // instruction.
624 if (!IsVectorAccess && isa(I)) {
625 Value *DataOp = I->getOperand(0);
626 if (isa(DataOp))
627 IsVectorAccess = true;
628 }
629
630 // A load which gets inserted into a vector element will be combined into a
631 // VLE type instruction.
632 if (!IsVectorAccess && isa(I) && I->hasOneUse()) {
633 User *LoadUser = *I->user_begin();
634 if (isa(LoadUser))
635 IsVectorAccess = true;
636 }
637
638 if (!isUInt<12>(Offset) && (IsFPAccess || IsVectorAccess))
639 return false;
710 if (!supportedAddressingMode(I, Subtarget.hasVector()).LongDisplacement)
711 return (isUInt<12>(Offset));
640712
641713 return true;
642714 }
383383 bool isLegalICmpImmediate(int64_t Imm) const override;
384384 bool isLegalAddImmediate(int64_t Imm) const override;
385385 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
386 unsigned AS) const override;
386 unsigned AS,
387 Instruction *I = nullptr) const override;
387388 bool isFoldableMemAccessOffset(Instruction *I, int64_t Offset) const override;
388389 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
389390 unsigned Align,
289289 UP.AllowExpensiveTripCount = true;
290290
291291 UP.Force = true;
292 }
293
294
295 bool SystemZTTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
296 TargetTransformInfo::LSRCost &C2) {
297 // SystemZ specific: check instruction count (first), and don't care about
298 // ImmCost, since offsets are checked explicitly.
299 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
300 C1.NumIVMuls, C1.NumBaseAdds,
301 C1.ScaleCost, C1.SetupCost) <
302 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
303 C2.NumIVMuls, C2.NumBaseAdds,
304 C2.ScaleCost, C2.SetupCost);
292305 }
293306
294307 unsigned SystemZTTIImpl::getNumberOfRegisters(bool Vector) {
4747 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
4848 TTI::UnrollingPreferences &UP);
4949
50 bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
51 TargetTransformInfo::LSRCost &C2);
5052 /// @}
5153
5254 /// \name Vector TTI Implementations
6062 unsigned getMinPrefetchStride() { return 2048; }
6163
6264 bool prefersVectorizedAddressing() { return false; }
65 bool LSRWithInstrQueries() { return true; }
6366 bool supportsEfficientVectorElementLoadStore() { return true; }
6467 bool enableInterleavedAccessVectorization() { return true; }
6568
232232 bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL,
233233 const AddrMode &AM,
234234 Type *Ty,
235 unsigned AS) const {
235 unsigned AS,
236 Instruction *I) const {
236237 // WebAssembly offsets are added as unsigned without wrapping. The
237238 // isLegalAddressingMode gives us no way to determine if wrapping could be
238239 // happening, so we approximate this by accepting only non-negative offsets.
5454 bool isCheapToSpeculateCttz() const override;
5555 bool isCheapToSpeculateCtlz() const override;
5656 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
57 unsigned AS) const override;
57 unsigned AS,
58 Instruction *I = nullptr) const override;
5859 bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, unsigned Align,
5960 bool *Fast) const override;
6061 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
2475624756 /// target, for a load/store of the specified type.
2475724757 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
2475824758 const AddrMode &AM, Type *Ty,
24759 unsigned AS) const {
24759 unsigned AS,
24760 Instruction *I) const {
2476024761 // X86 supports extremely general addressing modes.
2476124762 CodeModel::Model M = getTargetMachine().getCodeModel();
2476224763
902902 /// Return true if the addressing mode represented
903903 /// by AM is legal for this target, for a load/store of the specified type.
904904 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
905 Type *Ty, unsigned AS) const override;
905 Type *Ty, unsigned AS,
906 Instruction *I = nullptr) const override;
906907
907908 /// Return true if the specified immediate is legal
908909 /// icmp immediate, that is the target has icmp instructions which can
18881888 /// by AM is legal for this target, for a load/store of the specified type.
18891889 bool XCoreTargetLowering::isLegalAddressingMode(const DataLayout &DL,
18901890 const AddrMode &AM, Type *Ty,
1891 unsigned AS) const {
1891 unsigned AS,
1892 Instruction *I) const {
18921893 if (Ty->getTypeID() == Type::VoidTyID)
18931894 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
18941895
122122 MachineBasicBlock *MBB) const override;
123123
124124 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
125 Type *Ty, unsigned AS) const override;
125 Type *Ty, unsigned AS,
126 Instruction *I = nullptr) const override;
126127
127128 /// If a physical register, this returns the register that receives the
128129 /// exception address on entry to an EH pad.
782782 // of intrinsics.
783783 switch (II->getIntrinsicID()) {
784784 default: break;
785 case Intrinsic::memset:
785786 case Intrinsic::prefetch:
786787 if (II->getArgOperand(0) == OperandVal)
788 isAddress = true;
789 break;
790 case Intrinsic::memmove:
791 case Intrinsic::memcpy:
792 if (II->getArgOperand(0) == OperandVal ||
793 II->getArgOperand(1) == OperandVal)
787794 isAddress = true;
788795 break;
789796 }
12791286
12801287 // Check with target if this offset with this instruction is
12811288 // specifically not supported.
1282 if ((isa(Fixup.UserInst) || isa(Fixup.UserInst)) &&
1289 if (LU.Kind == LSRUse::Address && Offset != 0 &&
12831290 !TTI.isFoldableMemAccessOffset(Fixup.UserInst, Offset))
12841291 C.NumBaseAdds++;
12851292 }
15341541 static bool isAMCompletelyFolded(const TargetTransformInfo &TTI,
15351542 LSRUse::KindType Kind, MemAccessTy AccessTy,
15361543 GlobalValue *BaseGV, int64_t BaseOffset,
1537 bool HasBaseReg, int64_t Scale) {
1544 bool HasBaseReg, int64_t Scale,
1545 Instruction *Fixup = nullptr) {
15381546 switch (Kind) {
15391547 case LSRUse::Address:
15401548 return TTI.isLegalAddressingMode(AccessTy.MemTy, BaseGV, BaseOffset,
1541 HasBaseReg, Scale, AccessTy.AddrSpace);
1549 HasBaseReg, Scale, AccessTy.AddrSpace, Fixup);
15421550
15431551 case LSRUse::ICmpZero:
15441552 // There's not even a target hook for querying whether it would be legal to
16441652
16451653 static bool isAMCompletelyFolded(const TargetTransformInfo &TTI,
16461654 const LSRUse &LU, const Formula &F) {
1655 // Target may want to look at the user instructions.
1656 if (LU.Kind == LSRUse::Address && TTI.LSRWithInstrQueries()) {
1657 for (const LSRFixup &Fixup : LU.Fixups)
1658 if (!isAMCompletelyFolded(TTI, LSRUse::Address, LU.AccessTy, F.BaseGV,
1659 F.BaseOffset, F.HasBaseReg, F.Scale,
1660 Fixup.UserInst))
1661 return false;
1662 return true;
1663 }
1664
16471665 return isAMCompletelyFolded(TTI, LU.MinOffset, LU.MaxOffset, LU.Kind,
16481666 LU.AccessTy, F.BaseGV, F.BaseOffset, F.HasBaseReg,
16491667 F.Scale);
3939 for.body.3.i: ; preds = %for.body.3.i, %for.body.3.lr.ph.i
4040 ; CHECK-LABEL: .LBB0_5:
4141 ; CHECK-NOT: stfh %r{{.*}}, 0(%r{{.*}})
42 ; CHECK: lg %r{{.*}}, -4(%r{{.*}})
42 ; CHECK: lg %r{{.*}}, 8(%r{{.*}})
4343 ; Overlapping load should go before the store
4444 %indvars.iv.i = phi i64 [ 0, %for.body.3.lr.ph.i ], [ %indvars.iv.next.i, %for.body.3.i ]
4545 %3 = shl nsw i64 %indvars.iv.i, 6
88 define void @f1(i32 *%dest, i32 %a) {
99 ; CHECK-LABEL: f1:
1010 ; CHECK-NOT: sllg
11 ; CHECK: st %r3, 0({{%r[1-5],%r[1-5]}})
11 ; CHECK: st %r3, 400({{%r[1-5],%r[1-5]}})
1212 ; CHECK: br %r14
1313 entry:
1414 br label %loop
238238 %exitcond = icmp eq i32 %lftr.wideiv, %S
239239 br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
240240 }
241
242 ; Test that a memcpy loop does not get a lot of lays before each mvc (D12 and no index-reg).
243 %0 = type { %1, %2* }
244 %1 = type { %2*, %2* }
245 %2 = type <{ %3, i32, [4 x i8] }>
246 %3 = type { i16*, i16*, i16* }
247
248 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #0
249
250 define void @f8() {
251 ; CHECK-Z13-LABEL: f8:
252 ; CHECK-Z13: mvc
253 ; CHECK-Z13-NEXT: mvc
254 ; CHECK-Z13-NEXT: mvc
255 ; CHECK-Z13-NEXT: mvc
256
257 bb:
258 %tmp = load %0*, %0** undef, align 8
259 br i1 undef, label %bb2, label %bb1
260
261 bb1: ; preds = %bb
262 br label %bb2
263
264 bb2: ; preds = %bb1, %bb
265 %tmp3 = phi %0* [ %tmp, %bb ], [ undef, %bb1 ]
266 %tmp4 = phi %0* [ undef, %bb ], [ undef, %bb1 ]
267 br label %bb5
268
269 bb5: ; preds = %bb5, %bb2
270 %tmp6 = phi %0* [ %tmp21, %bb5 ], [ %tmp3, %bb2 ]
271 %tmp7 = phi %0* [ %tmp20, %bb5 ], [ %tmp4, %bb2 ]
272 %tmp8 = getelementptr inbounds %0, %0* %tmp7, i64 -1
273 %tmp9 = getelementptr inbounds %0, %0* %tmp6, i64 -1
274 %tmp10 = bitcast %0* %tmp9 to i8*
275 %tmp11 = bitcast %0* %tmp8 to i8*
276 tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 24, i32 8, i1 false)
277 %tmp12 = getelementptr inbounds %0, %0* %tmp7, i64 -2
278 %tmp13 = getelementptr inbounds %0, %0* %tmp6, i64 -2
279 %tmp14 = bitcast %0* %tmp13 to i8*
280 %tmp15 = bitcast %0* %tmp12 to i8*
281 tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 24, i32 8, i1 false)
282 %tmp16 = getelementptr inbounds %0, %0* %tmp7, i64 -3
283 %tmp17 = getelementptr inbounds %0, %0* %tmp6, i64 -3
284 %tmp18 = bitcast %0* %tmp17 to i8*
285 %tmp19 = bitcast %0* %tmp16 to i8*
286 tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 24, i32 8, i1 false)
287 %tmp20 = getelementptr inbounds %0, %0* %tmp7, i64 -4
288 %tmp21 = getelementptr inbounds %0, %0* %tmp6, i64 -4
289 %tmp22 = bitcast %0* %tmp21 to i8*
290 %tmp23 = bitcast %0* %tmp20 to i8*
291 tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 24, i32 8, i1 false)
292 br label %bb5
293 }
294
295 ; Test that a chsi does not need an aghik inside the loop (no index reg)
296 define void @f9() {
297 ; CHECK-Z13-LABEL: f9:
298 ; CHECK-Z13: # =>This Inner Loop Header: Depth=1
299 ; CHECK-Z13-NOT: aghik
300 ; CHECK-Z13: chsi
301
302 entry:
303 br label %for.body.i63
304
305 for.body.i63: ; preds = %for.inc.i, %entry
306 %indvars.iv155.i = phi i64 [ 0, %entry ], [ %indvars.iv.next156.i.3, %for.inc.i ]
307 %arrayidx.i62 = getelementptr inbounds i32, i32* undef, i64 %indvars.iv155.i
308 %tmp = load i32, i32* %arrayidx.i62, align 4
309 %cmp9.i = icmp eq i32 %tmp, 0
310 br i1 %cmp9.i, label %for.inc.i, label %if.then10.i
311
312 if.then10.i: ; preds = %for.body.i63
313 unreachable
314
315 for.inc.i: ; preds = %for.body.i63
316 %indvars.iv.next156.i = or i64 %indvars.iv155.i, 1
317 %arrayidx.i62.1 = getelementptr inbounds i32, i32* undef, i64 %indvars.iv.next156.i
318 %tmp1 = load i32, i32* %arrayidx.i62.1, align 4
319 %indvars.iv.next156.i.3 = add nsw i64 %indvars.iv155.i, 4
320 br label %for.body.i63
321 }