llvm.org GIT mirror llvm / ecdc9d5
Add disassembler to MIPS. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 7 years ago
21 changed file(s) with 2916 addition(s) and 95 deletion(s). Raw diff Collapse all Expand all
11
22 tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
33 tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
4 tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
45 tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)
56 tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
67 tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
78 tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
89 tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
910 tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
11 tablegen(LLVM MipsGenEDInfo.inc -gen-enhanced-disassembly-info)
1012 add_public_tablegen_target(MipsCommonTableGen)
1113
1214 add_llvm_target(MipsCodeGen
3133 )
3234
3335 add_subdirectory(InstPrinter)
36 add_subdirectory(Disassembler)
3437 add_subdirectory(TargetInfo)
3538 add_subdirectory(MCTargetDesc)
3639 add_subdirectory(AsmParser)
0 include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
1
2 add_llvm_library(LLVMMipsDisassembler
3 MipsDisassembler.cpp
4 )
5
6 # workaround for hanging compilation on MSVC9 and 10
7 if( MSVC_VERSION EQUAL 1400 OR MSVC_VERSION EQUAL 1500 OR MSVC_VERSION EQUAL 1600 )
8 set_property(
9 SOURCE MipsDisassembler.cpp
10 PROPERTY COMPILE_FLAGS "/Od"
11 )
12 endif()
13
14 add_dependencies(LLVMMipsDisassembler MipsCommonTableGen)
15 include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
16
17 add_llvm_library(LLVMMipsDisassembler
18 MipsDisassembler.cpp
19 )
20
21 # workaround for hanging compilation on MSVC9 and 10
22 if( MSVC_VERSION EQUAL 1400 OR MSVC_VERSION EQUAL 1500 OR MSVC_VERSION EQUAL 1600 )
23 set_property(
24 SOURCE MipsDisassembler.cpp
25 PROPERTY COMPILE_FLAGS "/Od"
26 )
27 endif()
28
29 add_dependencies(LLVMMipsDisassembler MipsCommonTableGen)
0 ;===- ./lib/Target/Mips/Disassembler/LLVMBuild.txt --------------*- Conf -*--===;
1 ;
2 ; The LLVM Compiler Infrastructure
3 ;
4 ; This file is distributed under the University of Illinois Open Source
5 ; License. See LICENSE.TXT for details.
6 ;
7 ;===------------------------------------------------------------------------===;
8 ;
9 ; This is an LLVMBuild description file for the components in this subdirectory.
10 ;
11 ; For more information on the LLVMBuild system, please see:
12 ;
13 ; http://llvm.org/docs/LLVMBuild.html
14 ;
15 ;===------------------------------------------------------------------------===;
16
17 [component_0]
18 type = Library
19 name = MipsDisassembler
20 parent = Mips
21 required_libraries = MC Support MipsInfo
22 add_to_library_groups = Mips
0 ##===- lib/Target/Mips/Disassembler/Makefile ----------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMMipsDisassembler
11
12 # Hack: we need to include 'main' Mips target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
0 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the Mips Disassembler.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Mips.h"
14 #include "MipsSubtarget.h"
15 #include "llvm/MC/EDInstInfo.h"
16 #include "llvm/MC/MCDisassembler.h"
17 #include "llvm/Support/MemoryObject.h"
18 #include "llvm/Support/TargetRegistry.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/MathExtras.h"
23
24
25 #include "MipsGenEDInfo.inc"
26
27 using namespace llvm;
28
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
30
31 /// MipsDisassembler - a disasembler class for Mips32.
32 class MipsDisassembler : public MCDisassembler {
33 public:
34 /// Constructor - Initializes the disassembler.
35 ///
36 MipsDisassembler(const MCSubtargetInfo &STI, bool bigEndian) :
37 MCDisassembler(STI), isBigEndian(bigEndian) {
38 }
39
40 ~MipsDisassembler() {
41 }
42
43 /// getInstruction - See MCDisassembler.
44 DecodeStatus getInstruction(MCInst &instr,
45 uint64_t &size,
46 const MemoryObject ®ion,
47 uint64_t address,
48 raw_ostream &vStream,
49 raw_ostream &cStream) const;
50
51 /// getEDInfo - See MCDisassembler.
52 const EDInstInfo *getEDInfo() const;
53
54 private:
55 bool isBigEndian;
56 };
57
58
59 /// Mips64Disassembler - a disasembler class for Mips64.
60 class Mips64Disassembler : public MCDisassembler {
61 public:
62 /// Constructor - Initializes the disassembler.
63 ///
64 Mips64Disassembler(const MCSubtargetInfo &STI, bool bigEndian) :
65 MCDisassembler(STI), isBigEndian(bigEndian) {
66 }
67
68 ~Mips64Disassembler() {
69 }
70
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
73 uint64_t &size,
74 const MemoryObject ®ion,
75 uint64_t address,
76 raw_ostream &vStream,
77 raw_ostream &cStream) const;
78
79 /// getEDInfo - See MCDisassembler.
80 const EDInstInfo *getEDInfo() const;
81
82 private:
83 bool isBigEndian;
84 };
85
86 const EDInstInfo *MipsDisassembler::getEDInfo() const {
87 return instInfoMips;
88 }
89
90 const EDInstInfo *Mips64Disassembler::getEDInfo() const {
91 return instInfoMips;
92 }
93
94 // Decoder tables for Mips register
95 static const unsigned CPURegsTable[] = {
96 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1,
97 Mips::A0, Mips::A1, Mips::A2, Mips::A3,
98 Mips::T0, Mips::T1, Mips::T2, Mips::T3,
99 Mips::T4, Mips::T5, Mips::T6, Mips::T7,
100 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
101 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
102 Mips::T8, Mips::T9, Mips::K0, Mips::K1,
103 Mips::GP, Mips::SP, Mips::FP, Mips::RA
104 };
105
106 static const unsigned FGR32RegsTable[] = {
107 Mips::F0, Mips::F1, Mips::F2, Mips::F3,
108 Mips::F4, Mips::F5, Mips::F6, Mips::F7,
109 Mips::F8, Mips::F9, Mips::F10, Mips::F11,
110 Mips::F12, Mips::F13, Mips::F14, Mips::F15,
111 Mips::F16, Mips::F17, Mips::F18, Mips::F18,
112 Mips::F20, Mips::F21, Mips::F22, Mips::F23,
113 Mips::F24, Mips::F25, Mips::F26, Mips::F27,
114 Mips::F28, Mips::F29, Mips::F30, Mips::F31
115 };
116
117 static const unsigned CPU64RegsTable[] = {
118 Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64,
119 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
120 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64,
121 Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64,
122 Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64,
123 Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64,
124 Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64,
125 Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64
126 };
127
128 static const unsigned FGR64RegsTable[] = {
129 Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64,
130 Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64,
131 Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64,
132 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
133 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64,
134 Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64,
135 Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64,
136 Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64
137 };
138
139 static const unsigned AFGR64RegsTable[] = {
140 Mips::D0, Mips::D1, Mips::D2, Mips::D3,
141 Mips::D4, Mips::D5, Mips::D6, Mips::D7,
142 Mips::D8, Mips::D9, Mips::D10, Mips::D11,
143 Mips::D12, Mips::D13, Mips::D14, Mips::D15
144 };
145
146 // Forward declare these because the autogenerated code will reference them.
147 // Definitions are further down.
148 static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
149 unsigned RegNo,
150 uint64_t Address,
151 const void *Decoder);
152
153 static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
154 unsigned RegNo,
155 uint64_t Address,
156 const void *Decoder);
157
158 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
159 unsigned RegNo,
160 uint64_t Address,
161 const void *Decoder);
162
163 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
164 unsigned RegNo,
165 uint64_t Address,
166 const void *Decoder);
167
168 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
169 unsigned RegNo,
170 uint64_t Address,
171 const void *Decoder);
172
173 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
174 unsigned Insn,
175 uint64_t Address,
176 const void *Decoder);
177
178 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
179 unsigned RegNo,
180 uint64_t Address,
181 const void *Decoder);
182
183 static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
184 unsigned Insn,
185 uint64_t Address,
186 const void *Decoder);
187
188 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
189 unsigned Offset,
190 uint64_t Address,
191 const void *Decoder);
192
193 static DecodeStatus DecodeBC1(MCInst &Inst,
194 unsigned Insn,
195 uint64_t Address,
196 const void *Decoder);
197
198
199 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
200 unsigned Insn,
201 uint64_t Address,
202 const void *Decoder);
203
204 static DecodeStatus DecodeMem(MCInst &Inst,
205 unsigned Insn,
206 uint64_t Address,
207 const void *Decoder);
208
209 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
210 uint64_t Address,
211 const void *Decoder);
212
213 static DecodeStatus DecodeSimm16(MCInst &Inst,
214 unsigned Insn,
215 uint64_t Address,
216 const void *Decoder);
217
218 static DecodeStatus DecodeCondCode(MCInst &Inst,
219 unsigned Insn,
220 uint64_t Address,
221 const void *Decoder);
222
223 static DecodeStatus DecodeInsSize(MCInst &Inst,
224 unsigned Insn,
225 uint64_t Address,
226 const void *Decoder);
227
228 static DecodeStatus DecodeExtSize(MCInst &Inst,
229 unsigned Insn,
230 uint64_t Address,
231 const void *Decoder);
232
233 namespace llvm {
234 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
235 TheMips64elTarget;
236 }
237
238 static MCDisassembler *createMipsDisassembler(
239 const Target &T,
240 const MCSubtargetInfo &STI) {
241 return new MipsDisassembler(STI,true);
242 }
243
244 static MCDisassembler *createMipselDisassembler(
245 const Target &T,
246 const MCSubtargetInfo &STI) {
247 return new MipsDisassembler(STI,false);
248 }
249
250 static MCDisassembler *createMips64Disassembler(
251 const Target &T,
252 const MCSubtargetInfo &STI) {
253 return new Mips64Disassembler(STI,true);
254 }
255
256 static MCDisassembler *createMips64elDisassembler(
257 const Target &T,
258 const MCSubtargetInfo &STI) {
259 return new Mips64Disassembler(STI, false);
260 }
261
262 extern "C" void LLVMInitializeMipsDisassembler() {
263 // Register the disassembler.
264 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
265 createMipsDisassembler);
266 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
267 createMipselDisassembler);
268 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
269 createMips64Disassembler);
270 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
271 createMips64elDisassembler);
272 }
273
274
275 #include "MipsGenDisassemblerTables.inc"
276
277 /// readInstruction - read four bytes from the MemoryObject
278 /// and return 32 bit word sorted according to the given endianess
279 static DecodeStatus readInstruction32(const MemoryObject ®ion,
280 uint64_t address,
281 uint64_t &size,
282 uint32_t &insn,
283 bool isBigEndian) {
284 uint8_t Bytes[4];
285
286 // We want to read exactly 4 Bytes of data.
287 if (region.readBytes(address, 4, (uint8_t*)Bytes, NULL) == -1) {
288 size = 0;
289 return MCDisassembler::Fail;
290 }
291
292 if (isBigEndian) {
293 // Encoded as a big-endian 32-bit word in the stream.
294 insn = (Bytes[3] << 0) |
295 (Bytes[2] << 8) |
296 (Bytes[1] << 16) |
297 (Bytes[0] << 24);
298 }
299 else {
300 // Encoded as a small-endian 32-bit word in the stream.
301 insn = (Bytes[0] << 0) |
302 (Bytes[1] << 8) |
303 (Bytes[2] << 16) |
304 (Bytes[3] << 24);
305 }
306
307 return MCDisassembler::Success;
308 }
309
310 DecodeStatus
311 MipsDisassembler::getInstruction(MCInst &instr,
312 uint64_t &Size,
313 const MemoryObject &Region,
314 uint64_t Address,
315 raw_ostream &vStream,
316 raw_ostream &cStream) const {
317 uint32_t Insn;
318
319 DecodeStatus Result = readInstruction32(Region, Address, Size,
320 Insn, isBigEndian);
321 if (Result == MCDisassembler::Fail)
322 return MCDisassembler::Fail;
323
324 // Calling the auto-generated decoder function.
325 Result = decodeMipsInstruction32(instr, Insn, Address, this, STI);
326 if (Result != MCDisassembler::Fail) {
327 Size = 4;
328 return Result;
329 }
330
331 return MCDisassembler::Fail;
332 }
333
334 DecodeStatus
335 Mips64Disassembler::getInstruction(MCInst &instr,
336 uint64_t &Size,
337 const MemoryObject &Region,
338 uint64_t Address,
339 raw_ostream &vStream,
340 raw_ostream &cStream) const {
341 uint32_t Insn;
342
343 DecodeStatus Result = readInstruction32(Region, Address, Size,
344 Insn, isBigEndian);
345 if (Result == MCDisassembler::Fail)
346 return MCDisassembler::Fail;
347
348 // Calling the auto-generated decoder function.
349 Result = decodeMips64Instruction32(instr, Insn, Address, this, STI);
350 if (Result != MCDisassembler::Fail) {
351 Size = 4;
352 return Result;
353 }
354 // If we fail to decode in Mips64 decoder space we can try in Mips32
355 Result = decodeMipsInstruction32(instr, Insn, Address, this, STI);
356 if (Result != MCDisassembler::Fail) {
357 Size = 4;
358 return Result;
359 }
360
361 return MCDisassembler::Fail;
362 }
363
364 static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
365 unsigned RegNo,
366 uint64_t Address,
367 const void *Decoder) {
368
369 if (RegNo > 31)
370 return MCDisassembler::Fail;
371
372 Inst.addOperand(MCOperand::CreateReg(CPU64RegsTable[RegNo]));
373 return MCDisassembler::Success;
374 }
375
376 static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
377 unsigned RegNo,
378 uint64_t Address,
379 const void *Decoder) {
380 if (RegNo > 31)
381 return MCDisassembler::Fail;
382
383 Inst.addOperand(MCOperand::CreateReg(CPURegsTable[RegNo]));
384 return MCDisassembler::Success;
385 }
386
387 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
388 unsigned RegNo,
389 uint64_t Address,
390 const void *Decoder) {
391 if (RegNo > 31)
392 return MCDisassembler::Fail;
393
394 Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[RegNo]));
395 return MCDisassembler::Success;
396 }
397
398 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
399 unsigned RegNo,
400 uint64_t Address,
401 const void *Decoder) {
402 if (RegNo > 31)
403 return MCDisassembler::Fail;
404
405 Inst.addOperand(MCOperand::CreateReg(FGR32RegsTable[RegNo]));
406 return MCDisassembler::Success;
407 }
408
409 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
410 unsigned RegNo,
411 uint64_t Address,
412 const void *Decoder) {
413 Inst.addOperand(MCOperand::CreateReg(RegNo));
414 return MCDisassembler::Success;
415 }
416
417 static DecodeStatus DecodeMem(MCInst &Inst,
418 unsigned Insn,
419 uint64_t Address,
420 const void *Decoder) {
421 int Offset = SignExtend32<16>(Insn & 0xffff);
422 int Reg = (int)fieldFromInstruction32(Insn, 16, 5);
423 int Base = (int)fieldFromInstruction32(Insn, 21, 5);
424
425 if(Inst.getOpcode() == Mips::SC){
426 Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
427 }
428
429 Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
430 Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
431 Inst.addOperand(MCOperand::CreateImm(Offset));
432
433 return MCDisassembler::Success;
434 }
435
436 static DecodeStatus DecodeFMem(MCInst &Inst,
437 unsigned Insn,
438 uint64_t Address,
439 const void *Decoder) {
440 int Offset = SignExtend32<16>(Insn & 0xffff);
441 int Reg = (int)fieldFromInstruction32(Insn, 16, 5);
442 int Base = (int)fieldFromInstruction32(Insn, 21, 5);
443
444 Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[Reg]));
445 Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
446 Inst.addOperand(MCOperand::CreateImm(Offset));
447
448 return MCDisassembler::Success;
449 }
450
451
452 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
453 unsigned RegNo,
454 uint64_t Address,
455 const void *Decoder) {
456 // Currently only hardware register 29 is supported.
457 if (RegNo != 29)
458 return MCDisassembler::Fail;
459 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
460 return MCDisassembler::Success;
461 }
462
463 static DecodeStatus DecodeCondCode(MCInst &Inst,
464 unsigned Insn,
465 uint64_t Address,
466 const void *Decoder) {
467 int CondCode = Insn & 0xf;
468 Inst.addOperand(MCOperand::CreateImm(CondCode));
469 return MCDisassembler::Success;
470 }
471
472 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
473 unsigned RegNo,
474 uint64_t Address,
475 const void *Decoder) {
476 if (RegNo > 31)
477 return MCDisassembler::Fail;
478
479 Inst.addOperand(MCOperand::CreateReg(AFGR64RegsTable[RegNo]));
480 return MCDisassembler::Success;
481 }
482
483 static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
484 unsigned RegNo,
485 uint64_t Address,
486 const void *Decoder) {
487 //Currently only hardware register 29 is supported
488 if (RegNo != 29)
489 return MCDisassembler::Fail;
490 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
491 return MCDisassembler::Success;
492 }
493
494 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
495 unsigned Offset,
496 uint64_t Address,
497 const void *Decoder) {
498 unsigned BranchOffset = Offset & 0xffff;
499 BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
500 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
501 return MCDisassembler::Success;
502 }
503
504 static DecodeStatus DecodeBC1(MCInst &Inst,
505 unsigned Insn,
506 uint64_t Address,
507 const void *Decoder) {
508 unsigned BranchOffset = Insn & 0xffff;
509 BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
510 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
511 return MCDisassembler::Success;
512 }
513
514 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
515 unsigned Insn,
516 uint64_t Address,
517 const void *Decoder) {
518
519 unsigned JumpOffset = fieldFromInstruction32(Insn, 0, 26) << 2;
520 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
521 return MCDisassembler::Success;
522 }
523
524
525 static DecodeStatus DecodeSimm16(MCInst &Inst,
526 unsigned Insn,
527 uint64_t Address,
528 const void *Decoder) {
529 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
530 return MCDisassembler::Success;
531 }
532
533 static DecodeStatus DecodeInsSize(MCInst &Inst,
534 unsigned Insn,
535 uint64_t Address,
536 const void *Decoder) {
537 // First we need to grab the pos(lsb) from MCInst.
538 int Pos = Inst.getOperand(2).getImm();
539 int Size = (int) Insn - Pos + 1;
540 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
541 return MCDisassembler::Success;
542 }
543
544 static DecodeStatus DecodeExtSize(MCInst &Inst,
545 unsigned Insn,
546 uint64_t Address,
547 const void *Decoder) {
548 int Size = (int) Insn + 1;
549 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
550 return MCDisassembler::Success;
551 }
1515 ;===------------------------------------------------------------------------===;
1616
1717 [common]
18 subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo
18 subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo
1919
2020 [component_0]
2121 type = TargetGroup
2323 parent = Target
2424 has_asmparser = 1
2525 has_asmprinter = 1
26 has_disassembler = 1
2627 has_jit = 1
2728
2829 [component_1]
3333
3434 using namespace llvm;
3535
36 static std::string ParseMipsTriple(StringRef TT, StringRef CPU) {
37 std::string MipsArchFeature;
38 size_t DashPosition = 0;
39 StringRef TheTriple;
40
41 // Let's see if there is a dash, like mips-unknown-linux.
42 DashPosition = TT.find('-');
43
44 if (DashPosition == StringRef::npos) {
45 // No dash, we check the string size.
46 TheTriple = TT.substr(0);
47 } else {
48 // We are only interested in substring before dash.
49 TheTriple = TT.substr(0,DashPosition);
50 }
51
52 if (TheTriple == "mips" || TheTriple == "mipsel") {
53 if (CPU.empty() || CPU == "mips32") {
54 MipsArchFeature = "+mips32";
55 } else if (CPU == "mips32r2") {
56 MipsArchFeature = "+mips32r2";
57 }
58 } else {
59 if (CPU.empty() || CPU == "mips64") {
60 MipsArchFeature = "+mips64";
61 } else if (CPU == "mips64r2") {
62 MipsArchFeature = "+mips64r2";
63 }
64 }
65 return MipsArchFeature;
66 }
67
3668 static MCInstrInfo *createMipsMCInstrInfo() {
3769 MCInstrInfo *X = new MCInstrInfo();
3870 InitMipsMCInstrInfo(X);
4779
4880 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
4981 StringRef FS) {
82 std::string ArchFS = ParseMipsTriple(TT,CPU);
83 if (!FS.empty()) {
84 if (!ArchFS.empty())
85 ArchFS = ArchFS + "," + FS.str();
86 else
87 ArchFS = FS;
88 }
5089 MCSubtargetInfo *X = new MCSubtargetInfo();
51 InitMipsMCSubtargetInfo(X, TT, CPU, FS);
90 InitMipsMCSubtargetInfo(X, TT, CPU, ArchFS);
5291 return X;
5392 }
5493
1414 BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
1515 MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \
1616 MipsGenDAGISel.inc MipsGenCallingConv.inc \
17 MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc
18
19 DIRS = InstPrinter AsmParser TargetInfo MCTargetDesc
17 MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \
18 MipsGenEDInfo.inc MipsGenDisassemblerTables.inc
19 DIRS = InstPrinter Disassembler AsmParser TargetInfo MCTargetDesc
2020
2121 include $(LEVEL)/Makefile.common
2222
3535 //===----------------------------------------------------------------------===//
3636 // Shifts
3737 // 64-bit shift instructions.
38 let DecoderNamespace = "Mips64" in {
3839 class shift_rotate_imm64 func, bits<5> isRotate, string instr_asm,
3940 SDNode OpNode>:
4041 shift_rotate_imm
4849
4950 multiclass Atomic2Ops64 {
5051 def #NAME# : Atomic2Ops, Requires<[NotN64]>;
51 def _P8 : Atomic2Ops, Requires<[IsN64]>;
52 def _P8 : Atomic2Ops, Requires<[IsN64]> {
53 let isCodeGenOnly = 1;
54 }
5255 }
5356
5457 multiclass AtomicCmpSwap64 {
5558 def #NAME# : AtomicCmpSwap, Requires<[NotN64]>;
5659 def _P8 : AtomicCmpSwap,
57 Requires<[IsN64]>;
58 }
59
60 let usesCustomInserter = 1, Predicates = [HasMips64] in {
60 Requires<[IsN64]> {
61 let isCodeGenOnly = 1;
62 }
63 }
64 }
65 let usesCustomInserter = 1, Predicates = [HasMips64],
66 DecoderNamespace = "Mips64" in {
6167 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64;
6268 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64;
6369 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64;
7177 //===----------------------------------------------------------------------===//
7278 // Instruction definition
7379 //===----------------------------------------------------------------------===//
74
80 let DecoderNamespace = "Mips64" in {
7581 /// Arithmetic Instructions (ALU Immediate)
7682 def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
7783 CPU64Regs>;
96102 def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>;
97103 def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>;
98104 def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
99 def DSLLV : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>;
100 def DSRLV : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>;
101 def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>;
102
105 def DSLLV : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>;
106 def DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>;
107 def DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>;
108 }
103109 // Rotate Instructions
104 let Predicates = [HasMips64r2] in {
110 let Predicates = [HasMips64r2], DecoderNamespace = "Mips64" in {
105111 def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
106112 def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
107113 }
108114
115 let DecoderNamespace = "Mips64" in {
109116 /// Load and Store Instructions
110117 /// aligned
111118 defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
131138
132139 /// Load-linked, Store-conditional
133140 def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, Requires<[NotN64]>;
134 def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]>;
141 def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]> {
142 let isCodeGenOnly = 1;
143 }
135144 def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, Requires<[NotN64]>;
136 def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]>;
145 def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]> {
146 let isCodeGenOnly = 1;
147 }
137148
138149 /// Jump and Branch Instructions
139150 def JR64 : JumpFR<0x00, 0x08, "jr", CPU64Regs>;
141152 def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
142153 def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
143154 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
144 def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>;
155 def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>;
145156 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
146
157 }
158 let DecoderNamespace = "Mips64" in
147159 def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>;
148160
161 let DecoderNamespace = "Mips64" in {
149162 /// Multiply and Divide Instructions.
150163 def DMULT : Mult64<0x1c, "dmult", IIImul>;
151164 def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
170183 def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>;
171184
172185 def LEA_ADDiu64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
173
174 let Uses = [SP_64] in
186 }
187 let Uses = [SP_64], DecoderNamespace = "Mips64" in
175188 def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
176 Requires<[IsN64]>;
177
189 Requires<[IsN64]> {
190 let isCodeGenOnly = 1;
191 }
192 let DecoderNamespace = "Mips64" in {
178193 def RDHWR64 : ReadHardware;
179194
180195 def DEXT : ExtBase<3, "dext", CPU64Regs>;
185200
186201 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
187202 "sll\t$rd, $rt, 0", [], IIAlu>;
203 let isCodeGenOnly = 1 in
188204 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
189205 "sll\t$rd, $rt, 0", [], IIAlu>;
190
206 }
191207 //===----------------------------------------------------------------------===//
192208 // Arbitrary patterns that map to one or more instructions
193209 //===----------------------------------------------------------------------===//
9494
9595 // Instantiation of instructions.
9696 def MOVZ_I_I : CondMovIntInt;
97 let Predicates = [HasMips64] in {
97 let Predicates = [HasMips64],DecoderNamespace = "Mips64" in {
9898 def MOVZ_I_I64 : CondMovIntInt;
99 def MOVZ_I64_I : CondMovIntInt;
100 def MOVZ_I64_I64 : CondMovIntInt;
99 def MOVZ_I64_I : CondMovIntInt {
100 let isCodeGenOnly = 1;
101 }
102 def MOVZ_I64_I64 : CondMovIntInt {
103 let isCodeGenOnly = 1;
104 }
101105 }
102106
103107 def MOVN_I_I : CondMovIntInt;
104 let Predicates = [HasMips64] in {
108 let Predicates = [HasMips64],DecoderNamespace = "Mips64" in {
105109 def MOVN_I_I64 : CondMovIntInt;
106 def MOVN_I64_I : CondMovIntInt;
107 def MOVN_I64_I64 : CondMovIntInt;
110 def MOVN_I64_I : CondMovIntInt {
111 let isCodeGenOnly = 1;
112 }
113 def MOVN_I64_I64 : CondMovIntInt {
114 let isCodeGenOnly = 1;
115 }
108116 }
109117
110118 def MOVZ_I_S : CondMovIntFP;
111119 def MOVZ_I64_S : CondMovIntFP,
112 Requires<[HasMips64]>;
120 Requires<[HasMips64]> {
121 let DecoderNamespace = "Mips64";
122 }
113123
114124 def MOVN_I_S : CondMovIntFP;
115125 def MOVN_I64_S : CondMovIntFP,
116 Requires<[HasMips64]>;
126 Requires<[HasMips64]> {
127 let DecoderNamespace = "Mips64";
128 }
117129
118130 let Predicates = [NotFP64bit] in {
119131 def MOVZ_I_D32 : CondMovIntFP;
120132 def MOVN_I_D32 : CondMovIntFP;
121133 }
122 let Predicates = [IsFP64bit] in {
134 let Predicates = [IsFP64bit],DecoderNamespace = "Mips64" in {
123135 def MOVZ_I_D64 : CondMovIntFP;
124 def MOVZ_I64_D64 : CondMovIntFP;
136 def MOVZ_I64_D64 : CondMovIntFP {
137 let isCodeGenOnly = 1;
138 }
125139 def MOVN_I_D64 : CondMovIntFP;
126 def MOVN_I64_D64 : CondMovIntFP;
140 def MOVN_I64_D64 : CondMovIntFP {
141 let isCodeGenOnly = 1;
142 }
127143 }
128144
129145 def MOVT_I : CondMovFPInt;
130146 def MOVT_I64 : CondMovFPInt,
131 Requires<[HasMips64]>;
147 Requires<[HasMips64]> {
148 let DecoderNamespace = "Mips64";
149 }
132150
133151 def MOVF_I : CondMovFPInt;
134152 def MOVF_I64 : CondMovFPInt,
135 Requires<[HasMips64]>;
153 Requires<[HasMips64]> {
154 let DecoderNamespace = "Mips64";
155 }
136156
137157 def MOVT_S : CondMovFPFP;
138158 def MOVF_S : CondMovFPFP;
141161 def MOVT_D32 : CondMovFPFP;
142162 def MOVF_D32 : CondMovFPFP;
143163 }
144 let Predicates = [IsFP64bit] in {
164 let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
145165 def MOVT_D64 : CondMovFPFP;
146166 def MOVF_D64 : CondMovFPFP;
147167 }
4646 SDT_MipsExtractElementF64>;
4747
4848 // Operand for printing out a condition code.
49 let PrintMethod = "printFCCOperand" in
49 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
5050 def condcode : Operand;
5151
5252 //===----------------------------------------------------------------------===//
5353 // Feature predicates.
5454 //===----------------------------------------------------------------------===//
5555
56 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">;
57 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">;
58 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
59 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
56 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, AssemblerPredicate<"FeatureFP64Bit">;
57 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, AssemblerPredicate<"!FeatureFP64Bit">;
58 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, AssemblerPredicate<"FeatureSingleFloat">;
59 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, AssemblerPredicate<"!FeatureSingleFloat">;
6060
6161 // FP immediate patterns.
6262 def fpimm0 : PatLeaf<(fpimm), [{
8282 //===----------------------------------------------------------------------===//
8383
8484 // FP load.
85 let DecoderMethod = "DecodeFMem" in {
8586 class FPLoad op, string opstr, RegisterClass RC, Operand MemOpnd>:
8687 FMem
8788 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load_a addr:$addr))],
9293 FMem
9394 !strconcat(opstr, "\t$ft, $addr"), [(store_a RC:$ft, addr:$addr)],
9495 IIStore>;
95
96 }
9697 // FP indexed load.
9798 class FPIdxLoad funct, string opstr, RegisterClass DRC,
9899 RegisterClass PRC, PatFrag FOp>:
117118 def _D32 : FFR1,
118119 Requires<[NotFP64bit]>;
119120 def _D64 : FFR1,
120 Requires<[IsFP64bit]>;
121 Requires<[IsFP64bit]> {
122 let DecoderNamespace = "Mips64";
123 }
121124 }
122125
123126 // Instructions that convert an FP value to 64-bit fixed point.
124 let Predicates = [IsFP64bit] in
127 let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in
125128 multiclass FFR1_L_M funct, string opstr> {
126129 def _S : FFR1;
127130 def _D64 : FFR1;
133136 def _D32 : FFR1P,
134137 Requires<[NotFP64bit]>;
135138 def _D64 : FFR1P,
136 Requires<[IsFP64bit]>;
139 Requires<[IsFP64bit]> {
140 let DecoderNamespace = "Mips64";
141 }
137142 }
138143
139144 multiclass FFR2P_M funct, string opstr, SDNode OpNode, bit isComm = 0> {
142147 def _D32 : FFR2P,
143148 Requires<[NotFP64bit]>;
144149 def _D64 : FFR2P,
145 Requires<[IsFP64bit]>;
146 }
150 Requires<[IsFP64bit]> {
151 let DecoderNamespace = "Mips64";
152 }
153 }
147154 }
148155
149156 // FP madd/msub/nmadd/nmsub instruction classes.
171178 defm FLOOR_W : FFR1_W_M<0xf, "floor">;
172179 defm FLOOR_L : FFR1_L_M<0xb, "floor">;
173180 defm CVT_W : FFR1_W_M<0x24, "cvt">;
174 defm CVT_L : FFR1_L_M<0x25, "cvt">;
181 //defm CVT_L : FFR1_L_M<0x25, "cvt">;
175182
176183 def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
184 def CVT_L_S : FFR1<0x25, 16, "cvt", "l.s", FGR64, FGR32>;
185 def CVT_L_D64: FFR1<0x25, 17, "cvt", "l.d", FGR64, FGR64>;
177186
178187 let Predicates = [NotFP64bit] in {
179188 def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
181190 def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
182191 }
183192
184 let Predicates = [IsFP64bit] in {
193 let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
185194 def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
186195 def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
187196 def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;
234243 def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
235244 Requires<[NotFP64bit]>;
236245 def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>,
237 Requires<[IsFP64bit]>;
246 Requires<[IsFP64bit]> {
247 let DecoderNamespace = "Mips64";
248 }
238249
239250 /// Floating Point Memory Instructions
240 let Predicates = [IsN64] in {
251 let Predicates = [IsN64], DecoderNamespace = "Mips64" in {
241252 def LWC1_P8 : FPLoad<0x31, "lwc1", FGR32, mem64>;
242253 def SWC1_P8 : FPStore<0x39, "swc1", FGR32, mem64>;
243 def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64>;
244 def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64>;
254 def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> {
255 let isCodeGenOnly =1;
256 }
257 def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64> {
258 let isCodeGenOnly =1;
259 }
245260 }
246261
247262 let Predicates = [NotN64] in {
249264 def SWC1 : FPStore<0x39, "swc1", FGR32, mem>;
250265 }
251266
252 let Predicates = [NotN64, HasMips64] in {
267 let Predicates = [NotN64, HasMips64], DecoderNamespace = "Mips64" in {
253268 def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>;
254269 def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>;
255270 }
272287 def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store_a>;
273288 }
274289
275 let Predicates = [HasMips64, NotN64] in {
290 let Predicates = [HasMips64, NotN64], DecoderNamespace="Mips64" in {
276291 def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load_a>;
277292 def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store_a>;
278293 }
279294
280295 // n64
281 let Predicates = [IsN64] in {
296 let Predicates = [IsN64], isCodeGenOnly=1 in {
282297 def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load_a>;
283298 def LUXC1_P8 : FPIdxLoad<0x5, "luxc1", FGR32, CPU64Regs, load_u>;
284299 def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>;
313328 def NMSUB_D32 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, AFGR64>;
314329 }
315330
316 let Predicates = [HasMips32r2, IsFP64bit] in {
331 let Predicates = [HasMips32r2, IsFP64bit], isCodeGenOnly=1 in {
317332 def MADD_D64 : FMADDSUB<0x4, 1, "madd", "d", fadd, FGR64>;
318333 def MSUB_D64 : FMADDSUB<0x5, 1, "msub", "d", fsub, FGR64>;
319334 }
320335
321 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath] in {
336 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath], isCodeGenOnly=1 in {
322337 def NMADD_D64 : FNMADDSUB<0x6, 1, "nmadd", "d", fadd, FGR64>;
323338 def NMSUB_D64 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, FGR64>;
324339 }
341356 let Inst{16} = tf;
342357 }
343358
359 let DecoderMethod = "DecodeBC1" in {
344360 def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">;
345361 def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
346
362 }
347363 //===----------------------------------------------------------------------===//
348364 // Floating Point Flag Conditions
349365 //===----------------------------------------------------------------------===//
375391 let Defs=[FCR31] in {
376392 def FCMP_S32 : FCMP<0x10, FGR32, "s">;
377393 def FCMP_D32 : FCMP<0x11, AFGR64, "d">, Requires<[NotFP64bit]>;
378 def FCMP_D64 : FCMP<0x11, FGR64, "d">, Requires<[IsFP64bit]>;
394 def FCMP_D64 : FCMP<0x11, FGR64, "d">, Requires<[IsFP64bit]> {
395 let DecoderNamespace = "Mips64";
396 }
379397 }
380398
381399 //===----------------------------------------------------------------------===//
437455
438456 // Patterns for unaligned floating point loads and stores.
439457 let Predicates = [HasMips32r2Or64, NotN64] in {
440 def : Pat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
458 def : Pat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
441459 def : Pat<(store_u FGR32:$src, CPURegs:$addr),
442460 (SUXC1 FGR32:$src, CPURegs:$addr, ZERO)>;
443461 }
444462
445463 let Predicates = [IsN64] in {
446 def : Pat<(f32 (load_u CPU64Regs:$addr)), (LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
464 def : Pat<(f32 (load_u CPU64Regs:$addr)), (LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
447465 def : Pat<(store_u FGR32:$src, CPU64Regs:$addr),
448466 (SUXC1_P8 FGR32:$src, CPU64Regs:$addr, ZERO_64)>;
449467 }
4444
4545 let Namespace = "Mips";
4646
47 let Size = 4;
48
4749 bits<6> Opcode = 0;
4850
4951 // Top 6 bits are the 'opcode' field
6365
6466 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
6567 let TSFlags{3-0} = FormBits;
68
69 let DecoderNamespace = "Mips";
70
71 field bits<32> SoftFail = 0;
6672 }
6773
6874 // Mips Pseudo Instructions Format
120120 //===----------------------------------------------------------------------===//
121121 // Mips Instruction Predicate Definitions.
122122 //===----------------------------------------------------------------------===//
123 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
124 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
125 def HasSwap : Predicate<"Subtarget.hasSwap()">;
126 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
127 def HasMips32 : Predicate<"Subtarget.hasMips32()">;
128 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
129 def HasMips64 : Predicate<"Subtarget.hasMips64()">;
130 def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">;
131 def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
132 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
133 def IsN64 : Predicate<"Subtarget.isABI_N64()">;
134 def NotN64 : Predicate<"!Subtarget.isABI_N64()">;
135 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
136 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
137 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
123 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
124 AssemblerPredicate<"FeatureSEInReg">;
125 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
126 AssemblerPredicate<"FeatureBitCount">;
127 def HasSwap : Predicate<"Subtarget.hasSwap()">,
128 AssemblerPredicate<"FeatureSwap">;
129 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
130 AssemblerPredicate<"FeatureCondMov">;
131 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
132 AssemblerPredicate<"FeatureMips32">;
133 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
134 AssemblerPredicate<"FeatureMips32r2">;
135 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
136 AssemblerPredicate<"FeatureMips64">;
137 def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">,
138 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">;
139 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
140 AssemblerPredicate<"!FeatureMips64">;
141 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
142 AssemblerPredicate<"FeatureMips64r2">;
143 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
144 AssemblerPredicate<"FeatureN64">;
145 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
146 AssemblerPredicate<"!FeatureN64">;
147 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
148 AssemblerPredicate<"FeatureMips32">;
149 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
150 AssemblerPredicate<"FeatureMips32">;
151 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
152 AssemblerPredicate<"FeatureMips32">;
138153
139154 //===----------------------------------------------------------------------===//
140155 // Mips Operand, Complex Patterns and Transformations Definitions.
147162 def brtarget : Operand {
148163 let EncoderMethod = "getBranchTargetOpValue";
149164 let OperandType = "OPERAND_PCREL";
165 let DecoderMethod = "DecodeBranchTarget";
150166 }
151167 def calltarget : Operand {
152168 let EncoderMethod = "getJumpTargetOpValue";
153169 }
154170 def calltarget64: Operand;
155 def simm16 : Operand;
171 def simm16 : Operand {
172 let DecoderMethod= "DecodeSimm16";
173 }
156174 def simm16_64 : Operand;
157175 def shamt : Operand;
158176
188206 // size operand of ext instruction
189207 def size_ext : Operand {
190208 let EncoderMethod = "getSizeExtEncoding";
209 let DecoderMethod = "DecodeExtSize";
191210 }
192211
193212 // size operand of ins instruction
194213 def size_ins : Operand {
195214 let EncoderMethod = "getSizeInsEncoding";
215 let DecoderMethod = "DecodeInsSize";
196216 }
197217
198218 // Transformation Function - get the lower 16 bits.
372392 bits<21> addr;
373393 let Inst{25-21} = addr{20-16};
374394 let Inst{15-0} = addr{15-0};
395 let DecoderMethod = "DecodeMem";
375396 }
376397
377398 // Memory Load/Store
406427 def #NAME# : LoadM,
407428 Requires<[NotN64]>;
408429 def _P8 : LoadM,
409 Requires<[IsN64]>;
430 Requires<[IsN64]> {
431 let DecoderNamespace = "Mips64";
432 let isCodeGenOnly = 1;
433 }
410434 }
411435
412436 // 64-bit load.
415439 def #NAME# : LoadM,
416440 Requires<[NotN64]>;
417441 def _P8 : LoadM,
418 Requires<[IsN64]>;
442 Requires<[IsN64]> {
443 let DecoderNamespace = "Mips64";
444 let isCodeGenOnly = 1;
445 }
419446 }
420447
421448 // 32-bit load.
423450 def #NAME# : LoadUnAlign,
424451 Requires<[NotN64]>;
425452 def _P8 : LoadUnAlign,
426 Requires<[IsN64]>;
453 Requires<[IsN64]> {
454 let DecoderNamespace = "Mips64";
455 let isCodeGenOnly = 1;
456 }
427457 }
428458 // 32-bit store.
429459 multiclass StoreM32 op, string instr_asm, PatFrag OpNode,
431461 def #NAME# : StoreM,
432462 Requires<[NotN64]>;
433463 def _P8 : StoreM,
434 Requires<[IsN64]>;
464 Requires<[IsN64]> {
465 let DecoderNamespace = "Mips64";
466 let isCodeGenOnly = 1;
467 }
435468 }
436469
437470 // 64-bit store.
440473 def #NAME# : StoreM,
441474 Requires<[NotN64]>;
442475 def _P8 : StoreM,
443 Requires<[IsN64]>;
476 Requires<[IsN64]> {
477 let DecoderNamespace = "Mips64";
478 let isCodeGenOnly = 1;
479 }
444480 }
445481
446482 // 32-bit store.
448484 def #NAME# : StoreUnAlign,
449485 Requires<[NotN64]>;
450486 def _P8 : StoreUnAlign,
451 Requires<[IsN64]>;
487 Requires<[IsN64]> {
488 let DecoderNamespace = "Mips64";
489 let isCodeGenOnly = 1;
490 }
452491 }
453492
454493 // Conditional Branch
498537 let isBarrier=1;
499538 let hasDelaySlot = 1;
500539 let Predicates = [RelocStatic];
540 let DecoderMethod = "DecodeJumpTarget";
501541 }
502542
503543 // Unconditional branch
528568 class JumpLink op, string instr_asm>:
529569 FJ
530570 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
531 IIBranch>;
571 IIBranch> {
572 let DecoderMethod = "DecodeJumpTarget";
573 }
532574
533575 class JumpLinkReg op, bits<6> func, string instr_asm,
534576 RegisterClass RC>:
684726
685727 multiclass Atomic2Ops32 {
686728 def #NAME# : Atomic2Ops, Requires<[NotN64]>;
687 def _P8 : Atomic2Ops, Requires<[IsN64]>;
729 def _P8 : Atomic2Ops, Requires<[IsN64]> {
730 let DecoderNamespace = "Mips64";
731 }
688732 }
689733
690734 // Atomic Compare & Swap.
696740
697741 multiclass AtomicCmpSwap32 {
698742 def #NAME# : AtomicCmpSwap, Requires<[NotN64]>;
699 def _P8 : AtomicCmpSwap, Requires<[IsN64]>;
743 def _P8 : AtomicCmpSwap, Requires<[IsN64]> {
744 let DecoderNamespace = "Mips64";
745 }
700746 }
701747
702748 class LLBase Opc, string opstring, RegisterClass RC, Operand Mem> :
867913
868914 /// Load-linked, Store-conditional
869915 def LL : LLBase<0x30, "ll", CPURegs, mem>, Requires<[NotN64]>;
870 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, Requires<[IsN64]>;
916 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, Requires<[IsN64]> {
917 let DecoderNamespace = "Mips64";
918 }
919
871920 def SC : SCBase<0x38, "sc", CPURegs, mem>, Requires<[NotN64]>;
872 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>;
921 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]> {
922 let DecoderNamespace = "Mips64";
923 }
873924
874925 /// Jump and Branch Instructions
875926 def J : JumpFJ<0x02, "j">;
887938 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
888939 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
889940
890 let isReturn=1, isTerminator=1, hasDelaySlot=1,
941 let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
891942 isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
892943 def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
893944 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
922973 // instructions. The same not happens for stack address copies, so an
923974 // add op with mem ComplexPattern is used and the stack address copy
924975 // can be matched. It's similar to Sparc LEA_ADDRi
925 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
976 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
977 let isCodeGenOnly = 1;
978 }
926979
927980 // DynAlloc node points to dynamically allocated stack space.
928981 // $sp is added to the list of implicitly used registers to prevent dead code
929982 // elimination from removing instructions that modify $sp.
930983 let Uses = [SP] in
931 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
984 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
985 let isCodeGenOnly = 1;
986 }
932987
933988 // MADD*/MSUB*
934989 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
0 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux
1
2 # CHECK: abs.d $f12,$f14
3 0x46 0x20 0x39 0x85
4
5 # CHECK: abs.s $f6,$f7
6 0x46 0x00 0x39 0x85
7
8 # CHECK: add t1,a2,a3
9 0x00 0xc7 0x48 0x20
10
11 # CHECK: add.d $f18,$f12,$f14
12 0x46 0x27 0x32 0x40
13
14 # CHECK: add.s $f9,$f6,$f7
15 0x46 0x07 0x32 0x40
16
17 # CHECK: addi t1,a2,17767
18 0x20 0xc9 0x45 0x67
19
20 # CHECK: addiu t1,a2,-15001
21 0x24 0xc9 0xc5 0x67
22
23 # CHECK: addu t1,a2,a3
24 0x00 0xc7 0x48 0x21
25
26 # CHECK: and t1,a2,a3
27 0x00 0xc7 0x48 0x24
28
29 # CHECK: andi t1,a2,0x4567
30 0x30 0xc9 0x45 0x67
31
32 # CHECK: b 00000534
33 0x10 0x00 0x01 0x4c
34
35 # CHECK: bal 00000534
36 0x04 0x11 0x01 0x4c
37
38 # CHECK: bc1f 00000534
39 0x45 0x00 0x01 0x4c
40
41 # CHECK: bc1t 00000534
42 0x45 0x01 0x01 0x4c
43
44 # CHECK: beq t1,a2,00000534
45 0x11 0x26 0x01 0x4c
46
47 # CHECK: bgez a2,00000534
48 0x04 0xc1 0x01 0x4c
49
50 # CHECK: bgezal a2,00000534
51 0x04 0xd1 0x01 0x4c
52
53 # CHECK: bgtz a2,00000534
54 0x1c 0xc0 0x01 0x4c
55
56 # CHECK: blez a2,00000534
57 0x18 0xc0 0x01 0x4c
58
59 # CHECK: bne t1,a2,00000534
60 0x15 0x26 0x01 0x4c
61
62 # CHECK: c.eq.d $f12,$f14
63 0x46 0x27 0x30 0x32
64
65 # CHECK: c.eq.s $f6,$f7
66 0x46 0x07 0x30 0x32
67
68 # CHECK: c.f.d $f12,$f14
69 0x46 0x27 0x30 0x30
70
71 # CHECK: c.f.s $f6,$f7
72 0x46 0x07 0x30 0x30
73
74 # CHECK: c.le.d $f12,$f14
75 0x46 0x27 0x30 0x3e
76
77 # CHECK: c.le.s $f6,$f7
78 0x46 0x07 0x30 0x3e
79
80 # CHECK: c.lt.d $f12,$f14
81 0x46 0x27 0x30 0x3c
82
83 # CHECK: c.lt.s $f6,$f7
84 0x46 0x07 0x30 0x3c
85
86 # CHECK: c.nge.d $f12,$f14
87 0x46 0x27 0x30 0x3d
88
89 # CHECK: c.nge.s $f6,$f7
90 0x46 0x07 0x30 0x3d
91
92 # CHECK: c.ngl.d $f12,$f14
93 0x46 0x27 0x30 0x3b
94
95 # CHECK: c.ngl.s $f6,$f7
96 0x46 0x07 0x30 0x3b
97
98 # CHECK: c.ngle.d $f12,$f14
99 0x46 0x27 0x30 0x39
100
101 # CHECK: c.ngle.s $f6,$f7
102 0x46 0x07 0x30 0x39
103
104 # CHECK: c.ngt.d $f12,$f14
105 0x46 0x27 0x30 0x3f
106
107 # CHECK: c.ngt.s $f6,$f7
108 0x46 0x07 0x30 0x3f
109
110 # CHECK: c.ole.d $f12,$f14
111 0x46 0x27 0x30 0x36
112
113 # CHECK: c.ole.s $f6,$f7
114 0x46 0x07 0x30 0x36
115
116 # CHECK: c.olt.d $f12,$f14
117 0x46 0x27 0x30 0x34
118
119 # CHECK: c.olt.s $f6,$f7
120 0x46 0x07 0x30 0x34
121
122 # CHECK: c.seq.d $f12,$f14
123 0x46 0x27 0x30 0x3a
124
125 # CHECK: c.seq.s $f6,$f7
126 0x46 0x07 0x30 0x3a
127
128 # CHECK: c.sf.d $f12,$f14
129 0x46 0x27 0x30 0x38
130
131 # CHECK: c.sf.s $f6,$f7
132 0x46 0x07 0x30 0x38
133
134 # CHECK: c.ueq.d $f12,$f14
135 0x46 0x27 0x30 0x33
136
137 # CHECK: c.ueq.s $f28,$f18
138 0x46 0x12 0xe0 0x33
139
140 # CHECK: c.ule.d $f12,$f14
141 0x46 0x27 0x30 0x37
142
143 # CHECK: c.ule.s $f6,$f7
144 0x46 0x07 0x30 0x37
145
146 # CHECK: c.ult.d $f12,$f14
147 0x46 0x27 0x30 0x35
148
149 # CHECK: c.ult.s $f6,$f7
150 0x46 0x07 0x30 0x35
151
152 # CHECK: c.un.d $f12,$f14
153 0x46 0x27 0x30 0x31
154
155 # CHECK: c.un.s $f6,$f7
156 0x46 0x07 0x30 0x31
157
158 # CHECK: ceil.w.d $f12,$f14
159 0x46 0x20 0x39 0x8e
160
161 # CHECK: ceil.w.s $f6,$f7
162 0x46 0x00 0x39 0x8e
163
164 # CHECK: cfc1 a2,$7
165 0x44 0x46 0x38 0x00
166
167 # CHECK: clo a2,a3
168 0x70 0xe6 0x30 0x21
169
170 # CHECK: clz a2,a3
171 0x70 0xe6 0x30 0x20
172
173 # CHECK: ctc1 a2,$7
174 0x44 0xc6 0x38 0x00
175
176 # CHECK: cvt.d.s $f6,$f7
177 0x46 0x00 0x38 0xa1
178
179 # CHECK: cvt.d.w $f12,$f14
180 0x46 0x80 0x38 0xa1
181
182 # CHECK: cvt.l.d $f12,$f14
183 0x46 0x20 0x39 0xa5
184
185 # CHECK: cvt.l.s $f6,$f7
186 0x46 0x00 0x39 0xa5
187
188 # CHECK: cvt.s.d $f12,$f14
189 0x46 0x20 0x39 0xa0
190
191 # CHECK: cvt.s.w $f6,$f7
192 0x46 0x80 0x39 0xa0
193
194 # CHECK: cvt.w.d $f12,$f14
195 0x46 0x20 0x39 0xa4
196
197 # CHECK: cvt.w.s $f6,$f7
198 0x46 0x00 0x39 0xa4
199
200 # CHECK: floor.w.d $f12,$f14
201 0x46 0x20 0x39 0x8f
202
203 # CHECK: floor.w.s $f6,$f7
204 0x46 0x00 0x39 0x8f
205
206 # CHECK: j 00000530
207 0x08 0x00 0x01 0x4c
208
209 # CHECK: jal 00000530
210 0x0c 0x00 0x01 0x4c
211
212 # CHECK: jalr a2,a3
213 0x00 0xe0 0xf8 0x09
214
215 # CHECK: jr a3
216 0x00 0xe0 0x00 0x08
217
218 # CHECK: lb a0,9158(a1)
219 0x80 0xa4 0x23 0xc6
220
221 # CHECK: lbu a0,6(a1)
222 0x90 0xa4 0x00 0x06
223
224 # CHECK: ldc1 $f9,9158(a3)
225 0xd4 0xe9 0x23 0xc6
226
227 # CHECK: lh a0,12(a1)
228 0x84 0xa4 0x00 0x0c
229
230 # CHECK: lh a0,12(a1)
231 0x84 0xa4 0x00 0x0c
232
233 # CHECK: li v1,17767
234 0x24 0x03 0x45 0x67
235
236 # CHECK: ll t1,9158(a3)
237 0xc0 0xe9 0x23 0xc6
238
239 # CHECK: lui a2,0x4567
240 0x3c 0x06 0x45 0x67
241
242 # CHECK: lw a0,24(a1)
243 0x8c 0xa4 0x00 0x18
244
245 # CHECK: lwc1 $f9,9158(a3)
246 0xc4 0xe9 0x23 0xc6
247
248 # CHECK: madd a2,a3
249 0x70 0xc7 0x00 0x00
250
251 # CHECK: maddu a2,a3
252 0x70 0xc7 0x00 0x01
253
254 # CHECK: mfc1 a2,$f7
255 0x44 0x06 0x38 0x00
256
257 # CHECK: mfhi a1
258 0x00 0x00 0x28 0x10
259
260 # CHECK: mflo a1
261 0x00 0x00 0x28 0x12
262
263 # CHECK: mov.d $f6,$f7
264 0x46 0x20 0x39 0x86
265
266 # CHECK: mov.s $f6,$f7
267 0x46 0x00 0x39 0x86
268
269 # CHECK: move a2,a1
270 0x00 0xa0 0x30 0x21
271
272 # CHECK: msub a2,a3
273 0x70 0xc7 0x00 0x04
274
275 # CHECK: msubu a2,a3
276 0x70 0xc7 0x00 0x05
277
278 # CHECK: mtc1 a2,$f7
279 0x44 0x86 0x38 0x00
280
281 # CHECK: mthi a3
282 0x00 0xe0 0x00 0x11
283
284 # CHECK: mtlo a3
285 0x00 0xe0 0x00 0x13
286
287 # CHECK: mul.d $f9,$f12,$f14
288 0x46 0x27 0x32 0x42
289
290 # CHECK: mul.s $f9,$f6,$f7
291 0x46 0x07 0x32 0x42
292
293 # CHECK: mul t1,a2,a3
294 0x70 0xc7 0x48 0x02
295
296 # CHECK: mult v1,a1
297 0x00 0x65 0x00 0x18
298
299 # CHECK: multu v1,a1
300 0x00 0x65 0x00 0x19
301
302 # CHECK: neg.d $f12,$f14
303 0x46 0x20 0x39 0x87
304
305 # CHECK: neg.s $f6,$f7
306 0x46 0x00 0x39 0x87
307
308 # CHECK: neg v1,a1
309 0x00 0x05 0x18 0x22
310
311 # CHECK: nop
312 0x00 0x00 0x00 0x00
313
314 # CHECK: nor t1,a2,a3
315 0x00 0xc7 0x48 0x27
316
317 # CHECK: not v1,a1
318 0x00 0xa0 0x18 0x27
319
320 # CHECK: or v1,v1,a1
321 0x00 0x65 0x18 0x25
322
323 # CHECK: ori t1,a2,0x4567
324 0x34 0xc9 0x45 0x67
325
326 # CHECK: rdhwr a2,$29
327 0x7c 0x06 0xe8 0x3b
328
329 # CHECK: round.w.d $f12,$f14
330 0x46 0x20 0x39 0x8c
331
332 # CHECK: round.w.s $f6,$f7
333 0x46 0x00 0x39 0x8c
334
335 # CHECK: sb a0,9158(a1)
336 0xa0 0xa4 0x23 0xc6
337
338 # CHECK: sb a0,6(a1)
339 0xa0 0xa4 0x00 0x06
340
341 # CHECK: sc t1,9158(a3)
342 0xe0 0xe9 0x23 0xc6
343
344 # CHECK: sdc1 $f9,9158(a3)
345 0xf4 0xe9 0x23 0xc6
346
347 # CHECK: sh a0,9158(a1)
348 0xa4 0xa4 0x23 0xc6
349
350 # CHECK: sll a0,v1,0x7
351 0x00 0x03 0x21 0xc0
352
353 # CHECK: sllv v0,v1,a1
354 0x00 0xa3 0x10 0x04
355
356 # CHECK: slt v1,v1,a1
357 0x00 0x65 0x18 0x2a
358
359 # CHECK: slti v1,v1,103
360 0x28 0x63 0x00 0x67
361
362 # CHECK: sltiu v1,v1,103
363 0x2c 0x63 0x00 0x67
364
365 # CHECK: sltu v1,v1,a1
366 0x00 0x65 0x18 0x2b
367
368 # CHECK: sqrt.d $f12,$f14
369 0x46 0x20 0x39 0x84
370
371 # CHECK: sqrt.s $f6,$f7
372 0x46 0x00 0x39 0x84
373
374 # CHECK: sra a0,v1,0x7
375 0x00 0x03 0x21 0xc3
376
377 # CHECK: sra a0,v1,0x7
378 0x00 0x03 0x21 0xc3
379
380 # CHECK: srav v0,v1,a1
381 0x00 0xa3 0x10 0x07
382
383 # CHECK: srl a0,v1,0x7
384 0x00 0x03 0x21 0xc2
385
386 # CHECK: srlv v0,v1,a1
387 0x00 0xa3 0x10 0x06
388
389 # CHECK: sub.d $f9,$f12,$f14
390 0x46 0x27 0x32 0x41
391
392 # CHECK: sub.s $f9,$f6,$f7
393 0x46 0x07 0x32 0x41
394
395 # CHECK: sub t1,a2,a3
396 0x00 0xc7 0x48 0x22
397
398 # CHECK: subu a0,v1,a1
399 0x00 0x65 0x20 0x23
400
401 # CHECK: sw a0,24(a1)
402 0xac 0xa4 0x00 0x18
403
404 # CHECK: swc1 $f9,9158(a3)
405 0xe4 0xe9 0x23 0xc6
406
407 # CHECK: sync 0x7
408 0x00 0x00 0x01 0xcf
409
410 # CHECK: trunc.w.d $f12,$f14
411 0x46 0x20 0x39 0x8d
412
413 # CHECK: trunc.w.s $f6,$f7
414 0x46 0x00 0x39 0x8d
415
416 # CHECK: xor v1,v1,a1
417 0x00 0x65 0x18 0x26
418
419 # CHECK: xori t1,a2,0x4567
420 0x38 0xc9 0x45 0x67
0 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux
1
2 # CHECK: abs.d $f12,$f14
3 0x85 0x39 0x20 0x46
4
5 # CHECK: abs.s $f6,$f7
6 0x85 0x39 0x00 0x46
7
8 # CHECK: add t1,a2,a3
9 0x20 0x48 0xc7 0x00
10
11 # CHECK: add.d $f18,$f12,$f14
12 0x40 0x32 0x27 0x46
13
14 # CHECK: add.s $f9,$f6,$f7
15 0x40 0x32 0x07 0x46
16
17 # CHECK: addi t1,a2,17767
18 0x67 0x45 0xc9 0x20
19
20 # CHECK: addiu t1,a2,-15001
21 0x67 0xc5 0xc9 0x24
22
23 # CHECK: addu t1,a2,a3
24 0x21 0x48 0xc7 0x00
25
26 # CHECK: and t1,a2,a3
27 0x24 0x48 0xc7 0x00
28
29 # CHECK: andi t1,a2,0x4567
30 0x67 0x45 0xc9 0x30
31
32 # CHECK: b 00000534
33 0x4c 0x01 0x00 0x10
34
35 # CHECK: bal 00000534
36 0x4c 0x01 0x11 0x04
37
38 # CHECK: bc1f 00000534
39 0x4c 0x01 0x00 0x45
40
41 # CHECK: bc1t 00000534
42 0x4c 0x01 0x01 0x45
43
44 # CHECK: beq t1,a2,00000534
45 0x4c 0x01 0x26 0x11
46
47 # CHECK: bgez a2,00000534
48 0x4c 0x01 0xc1 0x04
49
50 # CHECK: bgezal a2,00000534
51 0x4c 0x01 0xd1 0x04
52
53 # CHECK: bgtz a2,00000534
54 0x4c 0x01 0xc0 0x1c
55
56 # CHECK: blez a2,00000534
57 0x4c 0x01 0xc0 0x18
58
59 # CHECK: bne t1,a2,00000534
60 0x4c 0x01 0x26 0x15
61
62 # CHECK: c.eq.d $f12,$f14
63 0x32 0x30 0x27 0x46
64
65 # CHECK: c.eq.s $f6,$f7
66 0x32 0x30 0x07 0x46
67
68 # CHECK: c.f.d $f12,$f14
69 0x30 0x30 0x27 0x46
70
71 # CHECK: c.f.s $f6,$f7
72 0x30 0x30 0x07 0x46
73
74 # CHECK: c.le.d $f12,$f14
75 0x3e 0x30 0x27 0x46
76
77 # CHECK: c.le.s $f6,$f7
78 0x3e 0x30 0x07 0x46
79
80 # CHECK: c.lt.d $f12,$f14
81 0x3c 0x30 0x27 0x46
82
83 # CHECK: c.lt.s $f6,$f7
84 0x3c 0x30 0x07 0x46
85
86 # CHECK: c.nge.d $f12,$f14
87 0x3d 0x30 0x27 0x46
88
89 # CHECK: c.nge.s $f6,$f7
90 0x3d 0x30 0x07 0x46
91
92 # CHECK: c.ngl.d $f12,$f14
93 0x3b 0x30 0x27 0x46
94
95 # CHECK: c.ngl.s $f6,$f7
96 0x3b 0x30 0x07 0x46
97
98 # CHECK: c.ngle.d $f12,$f14
99 0x39 0x30 0x27 0x46
100
101 # CHECK: c.ngle.s $f6,$f7
102 0x39 0x30 0x07 0x46
103
104 # CHECK: c.ngt.d $f12,$f14
105 0x3f 0x30 0x27 0x46
106
107 # CHECK: c.ngt.s $f6,$f7
108 0x3f 0x30 0x07 0x46
109
110 # CHECK: c.ole.d $f12,$f14
111 0x36 0x30 0x27 0x46
112
113 # CHECK: c.ole.s $f6,$f7
114 0x36 0x30 0x07 0x46
115
116 # CHECK: c.olt.d $f12,$f14
117 0x34 0x30 0x27 0x46
118
119 # CHECK: c.olt.s $f6,$f7
120 0x34 0x30 0x07 0x46
121
122 # CHECK: c.seq.d $f12,$f14
123 0x3a 0x30 0x27 0x46
124
125 # CHECK: c.seq.s $f6,$f7
126 0x3a 0x30 0x07 0x46
127
128 # CHECK: c.sf.d $f12,$f14
129 0x38 0x30 0x27 0x46
130
131 # CHECK: c.sf.s $f6,$f7
132 0x38 0x30 0x07 0x46
133
134 # CHECK: c.ueq.d $f12,$f14
135 0x33 0x30 0x27 0x46
136
137 # CHECK: c.ueq.s $f28,$f18
138 0x33 0xe0 0x12 0x46
139
140 # CHECK: c.ule.d $f12,$f14
141 0x37 0x30 0x27 0x46
142
143 # CHECK: c.ule.s $f6,$f7
144 0x37 0x30 0x07 0x46
145
146 # CHECK: c.ult.d $f12,$f14
147 0x35 0x30 0x27 0x46
148
149 # CHECK: c.ult.s $f6,$f7
150 0x35 0x30 0x07 0x46
151
152 # CHECK: c.un.d $f12,$f14
153 0x31 0x30 0x27 0x46
154
155 # CHECK: c.un.s $f6,$f7
156 0x31 0x30 0x07 0x46
157
158 # CHECK: ceil.w.d $f12,$f14
159 0x8e 0x38 0x20 0x46
160
161 # CHECK: ceil.w.s $f6,$f7
162 0x8e 0x38 0x00 0x46
163
164 # CHECK: cfc1 a2,$7
165 0x00 0x38 0x46 0x44
166
167 # CHECK: clo a2,a3
168 0x21 0x30 0xe6 0x70
169
170 # CHECK: clz a2,a3
171 0x20 0x30 0xe6 0x70
172
173 # CHECK: ctc1 a2,$7
174 0x00 0x38 0xc6 0x44
175
176 # CHECK: cvt.d.s $f6,$f7
177 0xa1 0x39 0x00 0x46
178
179 # CHECK: cvt.d.w $f12,$f14
180 0xa1 0x39 0x80 0x46
181
182 # CHECK: cvt.l.d $f12,$f14
183 0xa5 0x39 0x20 0x46
184
185 # CHECK: cvt.l.s $f6,$f7
186 0xa5 0x39 0x00 0x46
187
188 # CHECK: cvt.s.d $f12,$f14
189 0xa0 0x39 0x20 0x46
190
191 # CHECK: cvt.s.w $f6,$f7
192 0xa0 0x39 0x80 0x46
193
194 # CHECK: cvt.w.d $f12,$f14
195 0xa4 0x39 0x20 0x46
196
197 # CHECK: cvt.w.s $f6,$f7
198 0xa4 0x39 0x00 0x46
199
200 # CHECK: floor.w.d $f12,$f14
201 0x8f 0x39 0x20 0x46
202
203 # CHECK: floor.w.s $f6,$f7
204 0x8f 0x39 0x00 0x46
205
206 # CHECK: j 00000530
207 0x4c 0x01 0x00 0x08
208
209 # CHECK: jal 00000530
210 0x4c 0x01 0x00 0x0c
211
212 # CHECK: jalr a2,a3
213 0x09 0xf8 0xe0 0x00
214
215 # CHECK: jr a3
216 0x08 0x00 0xe0 0x00
217
218 # CHECK: lb a0,9158(a1)
219 0xc6 0x23 0xa4 0x80
220
221 # CHECK: lbu a0,6(a1)
222 0x06 0x00 0xa4 0x90
223
224 # CHECK: ldc1 $f9,9158(a3)
225 0xc6 0x23 0xe9 0xd4
226
227 # CHECK: lh a0,12(a1)
228 0x0c 0x00 0xa4 0x84
229
230 # CHECK: lh a0,12(a1)
231 0x0c 0x00 0xa4 0x84
232
233 # CHECK: li v1,17767
234 0x67 0x45 0x03 0x24
235
236 # CHECK: ll t1,9158(a3)
237 0xc6 0x23 0xe9 0xc0
238
239 # CHECK: lui a2,0x4567
240 0x67 0x45 0x06 0x3c
241
242 # CHECK: lw a0,24(a1)
243 0x18 0x00 0xa4 0x8c
244
245 # CHECK lw at,-18316(v0)
246 0x74 0xb8 0x41 0x8c
247
248 # CHECK: lwc1 $f9,9158(a3)
249 0xc6 0x23 0xe9 0xc4
250
251 # CHECK: madd a2,a3
252 0x00 0x00 0xc7 0x70
253
254 # CHECK: maddu a2,a3
255 0x01 0x00 0xc7 0x70
256
257 # CHECK: mfc1 a2,$f7
258 0x00 0x38 0x06 0x44
259
260 # CHECK: mfhi a1
261 0x10 0x28 0x00 0x00
262
263 # CHECK: mflo a1
264 0x12 0x28 0x00 0x00
265
266 # CHECK: mov.d $f12,$f14
267 0x86 0x39 0x20 0x46
268
269 # CHECK: mov.s $f6,$f7
270 0x86 0x39 0x00 0x46
271
272 # CHECK: move a2,a1
273 0x21 0x30 0xa0 0x00
274
275 # CHECK: msub a2,a3
276 0x04 0x00 0xc7 0x70
277
278 # CHECK: msubu a2,a3
279 0x05 0x00 0xc7 0x70
280
281 # CHECK: mtc1 a2,$f7
282 0x00 0x38 0x86 0x44
283
284 # CHECK: mthi a3
285 0x11 0x00 0xe0 0x00
286
287 # CHECK: mtlo a3
288 0x13 0x00 0xe0 0x00
289
290 # CHECK: mul.d $f9,$f12,$f14
291 0x42 0x32 0x27 0x46
292
293 # CHECK: mul.s $f9,$f6,$f7
294 0x42 0x32 0x07 0x46
295
296 # CHECK: mul t1,a2,a3
297 0x02 0x48 0xc7 0x70
298
299 # CHECK: mult v1,a1
300 0x18 0x00 0x65 0x00
301
302 # CHECK: multu v1,a1
303 0x19 0x00 0x65 0x00
304
305 # CHECK: neg.d $f12,$f14
306 0x87 0x39 0x20 0x46
307
308 # CHECK: neg.s $f6,$f7
309 0x87 0x39 0x00 0x46
310
311 # CHECK: neg v1,a1
312 0x22 0x18 0x05 0x00
313
314 # CHECK: nop
315 0x00 0x00 0x00 0x00
316
317 # CHECK: nor t1,a2,a3
318 0x27 0x48 0xc7 0x00
319
320 # CHECK: not v1,a1
321 0x27 0x18 0xa0 0x00
322
323 # CHECK: or v1,v1,a1
324 0x25 0x18 0x65 0x00
325
326 # CHECK: ori t1,a2,0x4567
327 0x67 0x45 0xc9 0x34
328
329 # CHECK: rdhwr a2,$29
330 0x3b 0xe8 0x06 0x7c
331
332 # CHECK: round.w.d $f12,$f14
333 0x8c 0x39 0x20 0x46
334
335 # CHECK: round.w.s $f6,$f7
336 0x8c 0x39 0x00 0x46
337
338 # CHECK: sb a0,9158(a1)
339 0xc6 0x23 0xa4 0xa0
340
341 # CHECK: sb a0,6(a1)
342 0x06 0x00 0xa4 0xa0
343
344 # CHECK: sc t1,9158(a3)
345 0xc6 0x23 0xe9 0xe0
346
347 # CHECK: sdc1 $f9,9158(a3)
348 0xc6 0x23 0xe9 0xf4
349
350 # CHECK: sh a0,9158(a1)
351 0xc6 0x23 0xa4 0xa4
352
353 # CHECK: sll a0,v1,0x7
354 0xc0 0x21 0x03 0x00
355
356 # CHECK: sllv v0,v1,a1
357 0x04 0x10 0xa3 0x00
358
359 # CHECK: slt v1,v1,a1
360 0x2a 0x18 0x65 0x00
361
362 # CHECK: slti v1,v1,103
363 0x67 0x00 0x63 0x28
364
365 # CHECK: sltiu v1,v1,103
366 0x67 0x00 0x63 0x2c
367
368 # CHECK: sltu v1,v1,a1
369 0x2b 0x18 0x65 0x00
370
371 # CHECK: sqrt.d $f12,$f14
372 0x84 0x39 0x20 0x46
373
374 # CHECK: sqrt.s $f6,$f7
375 0x84 0x39 0x00 0x46
376
377 # CHECK: sra a0,v1,0x7
378 0xc3 0x21 0x03 0x00
379
380 # CHECK: sra a0,v1,0x7
381 0xc3 0x21 0x03 0x00
382
383 # CHECK: srav v0,v1,a1
384 0x07 0x10 0xa3 0x00
385
386 # CHECK: srl a0,v1,0x7
387 0xc2 0x21 0x03 0x00
388
389 # CHECK: srlv v0,v1,a1
390 0x06 0x10 0xa3 0x00
391
392 # CHECK: sub.d $f9,$f12,$f14
393 0x41 0x32 0x27 0x46
394
395 # CHECK: sub.s $f9,$f6,$f7
396 0x41 0x32 0x07 0x46
397
398 # CHECK: sub t1,a2,a3
399 0x22 0x48 0xc7 0x00
400
401 # CHECK: subu a0,v1,a1
402 0x23 0x20 0x65 0x00
403
404 # CHECK: sw a0,24(a1)
405 0x18 0x00 0xa4 0xac
406
407 # CHECK: swc1 $f9,9158(a3)
408 0xc6 0x23 0xe9 0xe4
409
410 # CHECK: sync 0x7
411 0xcf 0x01 0x00 0x00
412
413 # CHECK: trunc.w.d $f12,$f14
414 0x8d 0x39 0x20 0x46
415
416 # CHECK: trunc.w.s $f6,$f7
417 0x8d 0x39 0x00 0x46
418
419 # CHECK: xor v1,v1,a1
420 0x26 0x18 0x65 0x00
421
422 # CHECK: xori t1,a2,0x4567
423 0x67 0x45 0xc9 0x38
0 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2
1
2 # CHECK: abs.d $f12,$f14
3 0x46 0x20 0x39 0x85
4
5 # CHECK: abs.s $f6,$f7
6 0x46 0x00 0x39 0x85
7
8 # CHECK: add t1,a2,a3
9 0x00 0xc7 0x48 0x20
10
11 # CHECK: add.d $f18,$f12,$f14
12 0x46 0x27 0x32 0x40
13
14 # CHECK: add.s $f9,$f6,$f7
15 0x46 0x07 0x32 0x40
16
17 # CHECK: addi t1,a2,17767
18 0x20 0xc9 0x45 0x67
19
20 # CHECK: addiu t1,a2,-15001
21 0x24 0xc9 0xc5 0x67
22
23 # CHECK: addu t1,a2,a3
24 0x00 0xc7 0x48 0x21
25
26 # CHECK: and t1,a2,a3
27 0x00 0xc7 0x48 0x24
28
29 # CHECK: andi t1,a2,0x4567
30 0x30 0xc9 0x45 0x67
31
32 # CHECK: b 00000534
33 0x10 0x00 0x01 0x4c
34
35 # CHECK: bal 00000534
36 0x04 0x11 0x01 0x4c
37
38 # CHECK: bc1f 00000534
39 0x45 0x00 0x01 0x4c
40
41 # CHECK: bc1t 00000534
42 0x45 0x01 0x01 0x4c
43
44 # CHECK: beq t1,a2,00000534
45 0x11 0x26 0x01 0x4c
46
47 # CHECK: bgez a2,00000534
48 0x04 0xc1 0x01 0x4c
49
50 # CHECK: bgezal a2,00000534
51 0x04 0xd1 0x01 0x4c
52
53 # CHECK: bgtz a2,00000534
54 0x1c 0xc0 0x01 0x4c
55
56 # CHECK: blez a2,00000534
57 0x18 0xc0 0x01 0x4c
58
59 # CHECK: bne t1,a2,00000534
60 0x15 0x26 0x01 0x4c
61
62 # CHECK: c.eq.d $f12,$f14
63 0x46 0x27 0x30 0x32
64
65 # CHECK: c.eq.s $f6,$f7
66 0x46 0x07 0x30 0x32
67
68 # CHECK: c.f.d $f12,$f14
69 0x46 0x27 0x30 0x30
70
71 # CHECK: c.f.s $f6,$f7
72 0x46 0x07 0x30 0x30
73
74 # CHECK: c.le.d $f12,$f14
75 0x46 0x27 0x30 0x3e
76
77 # CHECK: c.le.s $f6,$f7
78 0x46 0x07 0x30 0x3e
79
80 # CHECK: c.lt.d $f12,$f14
81 0x46 0x27 0x30 0x3c
82
83 # CHECK: c.lt.s $f6,$f7
84 0x46 0x07 0x30 0x3c
85
86 # CHECK: c.nge.d $f12,$f14
87 0x46 0x27 0x30 0x3d
88
89 # CHECK: c.nge.s $f6,$f7
90 0x46 0x07 0x30 0x3d
91
92 # CHECK: c.ngl.d $f12,$f14
93 0x46 0x27 0x30 0x3b
94
95 # CHECK: c.ngl.s $f6,$f7
96 0x46 0x07 0x30 0x3b
97
98 # CHECK: c.ngle.d $f12,$f14
99 0x46 0x27 0x30 0x39
100
101 # CHECK: c.ngle.s $f6,$f7
102 0x46 0x07 0x30 0x39
103
104 # CHECK: c.ngt.d $f12,$f14
105 0x46 0x27 0x30 0x3f
106
107 # CHECK: c.ngt.s $f6,$f7
108 0x46 0x07 0x30 0x3f
109
110 # CHECK: c.ole.d $f12,$f14
111 0x46 0x27 0x30 0x36
112
113 # CHECK: c.ole.s $f6,$f7
114 0x46 0x07 0x30 0x36
115
116 # CHECK: c.olt.d $f12,$f14
117 0x46 0x27 0x30 0x34
118
119 # CHECK: c.olt.s $f6,$f7
120 0x46 0x07 0x30 0x34
121
122 # CHECK: c.seq.d $f12,$f14
123 0x46 0x27 0x30 0x3a
124
125 # CHECK: c.seq.s $f6,$f7
126 0x46 0x07 0x30 0x3a
127
128 # CHECK: c.sf.d $f12,$f14
129 0x46 0x27 0x30 0x38
130
131 # CHECK: c.sf.s $f6,$f7
132 0x46 0x07 0x30 0x38
133
134 # CHECK: c.ueq.d $f12,$f14
135 0x46 0x27 0x30 0x33
136
137 # CHECK: c.ueq.s $f28,$f18
138 0x46 0x12 0xe0 0x33
139
140 # CHECK: c.ule.d $f12,$f14
141 0x46 0x27 0x30 0x37
142
143 # CHECK: c.ule.s $f6,$f7
144 0x46 0x07 0x30 0x37
145
146 # CHECK: c.ult.d $f12,$f14
147 0x46 0x27 0x30 0x35
148
149 # CHECK: c.ult.s $f6,$f7
150 0x46 0x07 0x30 0x35
151
152 # CHECK: c.un.d $f12,$f14
153 0x46 0x27 0x30 0x31
154
155 # CHECK: c.un.s $f6,$f7
156 0x46 0x07 0x30 0x31
157
158 # CHECK: ceil.w.d $f12,$f14
159 0x46 0x20 0x39 0x8e
160
161 # CHECK: ceil.w.s $f6,$f7
162 0x46 0x00 0x39 0x8e
163
164 # CHECK: cfc1 a2,$7
165 0x44 0x46 0x38 0x00
166
167 # CHECK: clo a2,a3
168 0x70 0xe6 0x30 0x21
169
170 # CHECK: clz a2,a3
171 0x70 0xe6 0x30 0x20
172
173 # CHECK: ctc1 a2,$7
174 0x44 0xc6 0x38 0x00
175
176 # CHECK: cvt.d.s $f6,$f7
177 0x46 0x00 0x38 0xa1
178
179 # CHECK: cvt.d.w $f12,$f14
180 0x46 0x80 0x38 0xa1
181
182 # CHECK: cvt.l.d $f12,$f14
183 0x46 0x20 0x39 0xa5
184
185 # CHECK: cvt.l.s $f6,$f7
186 0x46 0x00 0x39 0xa5
187
188 # CHECK: cvt.s.d $f12,$f14
189 0x46 0x20 0x39 0xa0
190
191 # CHECK: cvt.s.w $f6,$f7
192 0x46 0x80 0x39 0xa0
193
194 # CHECK: cvt.w.d $f12,$f14
195 0x46 0x20 0x39 0xa4
196
197 # CHECK: cvt.w.s $f6,$f7
198 0x46 0x00 0x39 0xa4
199
200 # CHECK: floor.w.d $f12,$f14
201 0x46 0x20 0x39 0x8f
202
203 # CHECK: floor.w.s $f6,$f7
204 0x46 0x00 0x39 0x8f
205
206 # CHECK: ins s3,t1,0x6,0x7
207 0x7d 0x33 0x61 0x84
208
209 # CHECK: j 00000530
210 0x08 0x00 0x01 0x4c
211
212 # CHECK: jal 00000530
213 0x0c 0x00 0x01 0x4c
214
215 # CHECK: jalr a2,a3
216 0x00 0xe0 0xf8 0x09
217
218 # CHECK: jr a3
219 0x00 0xe0 0x00 0x08
220
221 # CHECK: lb a0,9158(a1)
222 0x80 0xa4 0x23 0xc6
223
224 # CHECK: lbu a0,6(a1)
225 0x90 0xa4 0x00 0x06
226
227 # CHECK: ldc1 $f9,9158(a3)
228 0xd4 0xe9 0x23 0xc6
229
230 # CHECK: lh a0,12(a1)
231 0x84 0xa4 0x00 0x0c
232
233 # CHECK: lh a0,12(a1)
234 0x84 0xa4 0x00 0x0c
235
236 # CHECK: li v1,17767
237 0x24 0x03 0x45 0x67
238
239 # CHECK: ll t1,9158(a3)
240 0xc0 0xe9 0x23 0xc6
241
242 # CHECK: lui a2,0x4567
243 0x3c 0x06 0x45 0x67
244
245 # CHECK: lw a0,24(a1)
246 0x8c 0xa4 0x00 0x18
247
248 # CHECK: lwc1 $f9,9158(a3)
249 0xc4 0xe9 0x23 0xc6
250
251 # CHECK: madd a2,a3
252 0x70 0xc7 0x00 0x00
253
254 # CHECK: maddu a2,a3
255 0x70 0xc7 0x00 0x01
256
257 # CHECK: mfc1 a2,$f7
258 0x44 0x06 0x38 0x00
259
260 # CHECK: mfhi a1
261 0x00 0x00 0x28 0x10
262
263 # CHECK: mflo a1
264 0x00 0x00 0x28 0x12
265
266 # CHECK: mov.d $f6,$f7
267 0x46 0x20 0x39 0x86
268
269 # CHECK: mov.s $f6,$f7
270 0x46 0x00 0x39 0x86
271
272 # CHECK: move a2,a1
273 0x00 0xa0 0x30 0x21
274
275 # CHECK: msub a2,a3
276 0x70 0xc7 0x00 0x04
277
278 # CHECK: msubu a2,a3
279 0x70 0xc7 0x00 0x05
280
281 # CHECK: mtc1 a2,$f7
282 0x44 0x86 0x38 0x00
283
284 # CHECK: mthi a3
285 0x00 0xe0 0x00 0x11
286
287 # CHECK: mtlo a3
288 0x00 0xe0 0x00 0x13
289
290 # CHECK: mul.d $f9,$f12,$f14
291 0x46 0x27 0x32 0x42
292
293 # CHECK: mul.s $f9,$f6,$f7
294 0x46 0x07 0x32 0x42
295
296 # CHECK: mul t1,a2,a3
297 0x70 0xc7 0x48 0x02
298
299 # CHECK: mult v1,a1
300 0x00 0x65 0x00 0x18
301
302 # CHECK: multu v1,a1
303 0x00 0x65 0x00 0x19
304
305 # CHECK: neg.d $f12,$f14
306 0x46 0x20 0x39 0x87
307
308 # CHECK: neg.s $f6,$f7
309 0x46 0x00 0x39 0x87
310
311 # CHECK: neg v1,a1
312 0x00 0x05 0x18 0x22
313
314 # CHECK: nop
315 0x00 0x00 0x00 0x00
316
317 # CHECK: nor t1,a2,a3
318 0x00 0xc7 0x48 0x27
319
320 # CHECK: not v1,a1
321 0x00 0xa0 0x18 0x27
322
323 # CHECK: or v1,v1,a1
324 0x00 0x65 0x18 0x25
325
326 # CHECK: ori t1,a2,0x4567
327 0x34 0xc9 0x45 0x67
328
329 # CHECK: rdhwr a2,$29
330 0x7c 0x06 0xe8 0x3b
331
332 # CHECK: ror t1,a2,0x7
333 0x00 0x26 0x49 0xc2
334
335 # CHECK: rorv t1,a2,a3
336 0x00 0xe6 0x48 0x46
337
338 # CHECK: round.w.d $f12,$f14
339 0x46 0x20 0x39 0x8c
340
341 # CHECK: round.w.s $f6,$f7
342 0x46 0x00 0x39 0x8c
343
344 # CHECK: sb a0,9158(a1)
345 0xa0 0xa4 0x23 0xc6
346
347 # CHECK: sb a0,6(a1)
348 0xa0 0xa4 0x00 0x06
349
350 # CHECK: sc t1,9158(a3)
351 0xe0 0xe9 0x23 0xc6
352
353 # CHECK: sdc1 $f9,9158(a3)
354 0xf4 0xe9 0x23 0xc6
355
356 # CHECK: seb a2,a3
357 0x7c 0x07 0x34 0x20
358
359 # CHECK: seh a2,a3
360 0x7c 0x07 0x36 0x20
361
362 # CHECK: sh a0,9158(a1)
363 0xa4 0xa4 0x23 0xc6
364
365 # CHECK: sll a0,v1,0x7
366 0x00 0x03 0x21 0xc0
367
368 # CHECK: sllv v0,v1,a1
369 0x00 0xa3 0x10 0x04
370
371 # CHECK: slt v1,v1,a1
372 0x00 0x65 0x18 0x2a
373
374 # CHECK: slti v1,v1,103
375 0x28 0x63 0x00 0x67
376
377 # CHECK: sltiu v1,v1,103
378 0x2c 0x63 0x00 0x67
379
380 # CHECK: sltu v1,v1,a1
381 0x00 0x65 0x18 0x2b
382
383 # CHECK: sqrt.d $f12,$f14
384 0x46 0x20 0x39 0x84
385
386 # CHECK: sqrt.s $f6,$f7
387 0x46 0x00 0x39 0x84
388
389 # CHECK: sra a0,v1,0x7
390 0x00 0x03 0x21 0xc3
391
392 # CHECK: sra a0,v1,0x7
393 0x00 0x03 0x21 0xc3
394
395 # CHECK: srav v0,v1,a1
396 0x00 0xa3 0x10 0x07
397
398 # CHECK: srl a0,v1,0x7
399 0x00 0x03 0x21 0xc2
400
401 # CHECK: srlv v0,v1,a1
402 0x00 0xa3 0x10 0x06
403
404 # CHECK: sub.d $f9,$f12,$f14
405 0x46 0x27 0x32 0x41
406
407 # CHECK: sub.s $f9,$f6,$f7
408 0x46 0x07 0x32 0x41
409
410 # CHECK: sub t1,a2,a3
411 0x00 0xc7 0x48 0x22
412
413 # CHECK: subu a0,v1,a1
414 0x00 0x65 0x20 0x23
415
416 # CHECK: sw a0,24(a1)
417 0xac 0xa4 0x00 0x18
418
419 # CHECK: swc1 $f9,9158(a3)
420 0xe4 0xe9 0x23 0xc6
421
422 # CHECK: sync 0x7
423 0x00 0x00 0x01 0xcf
424
425 # CHECK: trunc.w.d $f12,$f14
426 0x46 0x20 0x39 0x8d
427
428 # CHECK: trunc.w.s $f6,$f7
429 0x46 0x00 0x39 0x8d
430
431 # CHECK: wsbh a2,a3
432 0x7c 0x07 0x30 0xa0
433
434 # CHECK: xor v1,v1,a1
435 0x00 0x65 0x18 0x26
436
437 # CHECK: xori t1,a2,0x4567
438 0x38 0xc9 0x45 0x67
0 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2
1
2 # CHECK: abs.d $f12,$f14
3 0x85 0x39 0x20 0x46
4
5 # CHECK: abs.s $f6,$f7
6 0x85 0x39 0x00 0x46
7
8 # CHECK: add t1,a2,a3
9 0x20 0x48 0xc7 0x00
10
11 # CHECK: add.d $f18,$f12,$f14
12 0x40 0x32 0x27 0x46
13
14 # CHECK: add.s $f9,$f6,$f7
15 0x40 0x32 0x07 0x46
16
17 # CHECK: addi t1,a2,17767
18 0x67 0x45 0xc9 0x20
19
20 # CHECK: addiu t1,a2,-15001
21 0x67 0xc5 0xc9 0x24
22
23 # CHECK: addu t1,a2,a3
24 0x21 0x48 0xc7 0x00
25
26 # CHECK: and t1,a2,a3
27 0x24 0x48 0xc7 0x00
28
29 # CHECK: andi t1,a2,0x4567
30 0x67 0x45 0xc9 0x30
31
32 # CHECK: b 00000534
33 0x4c 0x01 0x00 0x10
34
35 # CHECK: bal 00000534
36 0x4c 0x01 0x11 0x04
37
38 # CHECK: bc1f 00000534
39 0x4c 0x01 0x00 0x45
40
41 # CHECK: bc1t 00000534
42 0x4c 0x01 0x01 0x45
43
44 # CHECK: beq t1,a2,00000534
45 0x4c 0x01 0x26 0x11
46
47 # CHECK: bgez a2,00000534
48 0x4c 0x01 0xc1 0x04
49
50 # CHECK: bgezal a2,00000534
51 0x4c 0x01 0xd1 0x04
52
53 # CHECK: bgtz a2,00000534
54 0x4c 0x01 0xc0 0x1c
55
56 # CHECK: blez a2,00000534
57 0x4c 0x01 0xc0 0x18
58
59 # CHECK: bne t1,a2,00000534
60 0x4c 0x01 0x26 0x15
61
62 # CHECK: c.eq.d $f12,$f14
63 0x32 0x30 0x27 0x46
64
65 # CHECK: c.eq.s $f6,$f7
66 0x32 0x30 0x07 0x46
67
68 # CHECK: c.f.d $f12,$f14
69 0x30 0x30 0x27 0x46
70
71 # CHECK: c.f.s $f6,$f7
72 0x30 0x30 0x07 0x46
73
74 # CHECK: c.le.d $f12,$f14
75 0x3e 0x30 0x27 0x46
76
77 # CHECK: c.le.s $f6,$f7
78 0x3e 0x30 0x07 0x46
79
80 # CHECK: c.lt.d $f12,$f14
81 0x3c 0x30 0x27 0x46
82
83 # CHECK: c.lt.s $f6,$f7
84 0x3c 0x30 0x07 0x46
85
86 # CHECK: c.nge.d $f12,$f14
87 0x3d 0x30 0x27 0x46
88
89 # CHECK: c.nge.s $f6,$f7
90 0x3d 0x30 0x07 0x46
91
92 # CHECK: c.ngl.d $f12,$f14
93 0x3b 0x30 0x27 0x46
94
95 # CHECK: c.ngl.s $f6,$f7
96 0x3b 0x30 0x07 0x46
97
98 # CHECK: c.ngle.d $f12,$f14
99 0x39 0x30 0x27 0x46
100
101 # CHECK: c.ngle.s $f6,$f7
102 0x39 0x30 0x07 0x46
103
104 # CHECK: c.ngt.d $f12,$f14
105 0x3f 0x30 0x27 0x46
106
107 # CHECK: c.ngt.s $f6,$f7
108 0x3f 0x30 0x07 0x46
109
110 # CHECK: c.ole.d $f12,$f14
111 0x36 0x30 0x27 0x46
112
113 # CHECK: c.ole.s $f6,$f7
114 0x36 0x30 0x07 0x46
115
116 # CHECK: c.olt.d $f12,$f14
117 0x34 0x30 0x27 0x46
118
119 # CHECK: c.olt.s $f6,$f7
120 0x34 0x30 0x07 0x46
121
122 # CHECK: c.seq.d $f12,$f14
123 0x3a 0x30 0x27 0x46
124
125 # CHECK: c.seq.s $f6,$f7
126 0x3a 0x30 0x07 0x46
127
128 # CHECK: c.sf.d $f12,$f14
129 0x38 0x30 0x27 0x46
130
131 # CHECK: c.sf.s $f6,$f7
132 0x38 0x30 0x07 0x46
133
134 # CHECK: c.ueq.d $f12,$f14
135 0x33 0x30 0x27 0x46
136
137 # CHECK: c.ueq.s $f28,$f18
138 0x33 0xe0 0x12 0x46
139
140 # CHECK: c.ule.d $f12,$f14
141 0x37 0x30 0x27 0x46
142
143 # CHECK: c.ule.s $f6,$f7
144 0x37 0x30 0x07 0x46
145
146 # CHECK: c.ult.d $f12,$f14
147 0x35 0x30 0x27 0x46
148
149 # CHECK: c.ult.s $f6,$f7
150 0x35 0x30 0x07 0x46
151
152 # CHECK: c.un.d $f12,$f14
153 0x31 0x30 0x27 0x46
154
155 # CHECK: c.un.s $f6,$f7
156 0x31 0x30 0x07 0x46
157
158 # CHECK: ceil.w.d $f12,$f14
159 0x8e 0x38 0x20 0x46
160
161 # CHECK: ceil.w.s $f6,$f7
162 0x8e 0x38 0x00 0x46
163
164 # CHECK: cfc1 a2,$7
165 0x00 0x38 0x46 0x44
166
167 # CHECK: clo a2,a3
168 0x21 0x30 0xe6 0x70
169
170 # CHECK: clz a2,a3
171 0x20 0x30 0xe6 0x70
172
173 # CHECK: ctc1 a2,$7
174 0x00 0x38 0xc6 0x44
175
176 # CHECK: cvt.d.s $f6,$f7
177 0xa1 0x39 0x00 0x46
178
179 # CHECK: cvt.d.w $f12,$f14
180 0xa1 0x39 0x80 0x46
181
182 # CHECK: cvt.l.d $f12,$f14
183 0xa5 0x39 0x20 0x46
184
185 # CHECK: cvt.l.s $f6,$f7
186 0xa5 0x39 0x00 0x46
187
188 # CHECK: cvt.s.d $f12,$f14
189 0xa0 0x39 0x20 0x46
190
191 # CHECK: cvt.s.w $f6,$f7
192 0xa0 0x39 0x80 0x46
193
194 # CHECK: cvt.w.d $f12,$f14
195 0xa4 0x39 0x20 0x46
196
197 # CHECK: cvt.w.s $f6,$f7
198 0xa4 0x39 0x00 0x46
199
200 # CHECK: floor.w.d $f12,$f14
201 0x8f 0x39 0x20 0x46
202
203 # CHECK: floor.w.s $f6,$f7
204 0x8f 0x39 0x00 0x46
205
206 # CHECK: ins s3,t1,0x6,0x7
207 0x84 0x61 0x33 0x7d
208
209 # CHECK: j 00000530
210 0x4c 0x01 0x00 0x08
211
212 # CHECK: jal 00000530
213 0x4c 0x01 0x00 0x0c
214
215 # CHECK: jalr a2,a3
216 0x09 0xf8 0xe0 0x00
217
218 # CHECK: jr a3
219 0x08 0x00 0xe0 0x00
220
221 # CHECK: lb a0,9158(a1)
222 0xc6 0x23 0xa4 0x80
223
224 # CHECK: lbu a0,6(a1)
225 0x06 0x00 0xa4 0x90
226
227 # CHECK: ldc1 $f9,9158(a3)
228 0xc6 0x23 0xe9 0xd4
229
230 # CHECK: lh a0,12(a1)
231 0x0c 0x00 0xa4 0x84
232
233 # CHECK: lh a0,12(a1)
234 0x0c 0x00 0xa4 0x84
235
236 # CHECK: li v1,17767
237 0x67 0x45 0x03 0x24
238
239 # CHECK: ll t1,9158(a3)
240 0xc6 0x23 0xe9 0xc0
241
242 # CHECK: lui a2,0x4567
243 0x67 0x45 0x06 0x3c
244
245 # CHECK: lw a0,24(a1)
246 0x18 0x00 0xa4 0x8c
247
248 # CHECK lw at,-18316(v0)
249 0x74 0xb8 0x41 0x8c
250
251 # CHECK: lwc1 $f9,9158(a3)
252 0xc6 0x23 0xe9 0xc4
253
254 # CHECK: madd a2,a3
255 0x00 0x00 0xc7 0x70
256
257 # CHECK: maddu a2,a3
258 0x01 0x00 0xc7 0x70
259
260 # CHECK: mfc1 a2,$f7
261 0x00 0x38 0x06 0x44
262
263 # CHECK: mfhi a1
264 0x10 0x28 0x00 0x00
265
266 # CHECK: mflo a1
267 0x12 0x28 0x00 0x00
268
269 # CHECK: mov.d $f12,$f14
270 0x86 0x39 0x20 0x46
271
272 # CHECK: mov.s $f6,$f7
273 0x86 0x39 0x00 0x46
274
275 # CHECK: move a2,a1
276 0x21 0x30 0xa0 0x00
277
278 # CHECK: msub a2,a3
279 0x04 0x00 0xc7 0x70
280
281 # CHECK: msubu a2,a3
282 0x05 0x00 0xc7 0x70
283
284 # CHECK: mtc1 a2,$f7
285 0x00 0x38 0x86 0x44
286
287 # CHECK: mthi a3
288 0x11 0x00 0xe0 0x00
289
290 # CHECK: mtlo a3
291 0x13 0x00 0xe0 0x00
292
293 # CHECK: mul.d $f9,$f12,$f14
294 0x42 0x32 0x27 0x46
295
296 # CHECK: mul.s $f9,$f6,$f7
297 0x42 0x32 0x07 0x46
298
299 # CHECK: mul t1,a2,a3
300 0x02 0x48 0xc7 0x70
301
302 # CHECK: mult v1,a1
303 0x18 0x00 0x65 0x00
304
305 # CHECK: multu v1,a1
306 0x19 0x00 0x65 0x00
307
308 # CHECK: neg.d $f12,$f14
309 0x87 0x39 0x20 0x46
310
311 # CHECK: neg.s $f6,$f7
312 0x87 0x39 0x00 0x46
313
314 # CHECK: neg v1,a1
315 0x22 0x18 0x05 0x00
316
317 # CHECK: nop
318 0x00 0x00 0x00 0x00
319
320 # CHECK: nor t1,a2,a3
321 0x27 0x48 0xc7 0x00
322
323 # CHECK: not v1,a1
324 0x27 0x18 0xa0 0x00
325
326 # CHECK: or v1,v1,a1
327 0x25 0x18 0x65 0x00
328
329 # CHECK: ori t1,a2,0x4567
330 0x67 0x45 0xc9 0x34
331
332 # CHECK: rdhwr a2,$29
333 0x3b 0xe8 0x06 0x7c
334
335 # CHECK: ror t1,a2,0x7
336 0xc2 0x49 0x26 0x00
337
338 # CHECK: rorv t1,a2,a3
339 0x46 0x48 0xe6 0x00
340
341 # CHECK: round.w.d $f12,$f14
342 0x8c 0x39 0x20 0x46
343
344 # CHECK: round.w.s $f6,$f7
345 0x8c 0x39 0x00 0x46
346
347 # CHECK: sb a0,9158(a1)
348 0xc6 0x23 0xa4 0xa0
349
350 # CHECK: sb a0,6(a1)
351 0x06 0x00 0xa4 0xa0
352
353 # CHECK: sc t1,9158(a3)
354 0xc6 0x23 0xe9 0xe0
355
356 # CHECK: sdc1 $f9,9158(a3)
357 0xc6 0x23 0xe9 0xf4
358
359 # CHECK: seb a2,a3
360 0x20 0x34 0x07 0x7c
361
362 # CHECK: seh a2,a3
363 0x20 0x36 0x07 0x7c
364
365 # CHECK: sh a0,9158(a1)
366 0xc6 0x23 0xa4 0xa4
367
368 # CHECK: sll a0,v1,0x7
369 0xc0 0x21 0x03 0x00
370
371 # CHECK: sllv v0,v1,a1
372 0x04 0x10 0xa3 0x00
373
374 # CHECK: slt v1,v1,a1
375 0x2a 0x18 0x65 0x00
376
377 # CHECK: slti v1,v1,103
378 0x67 0x00 0x63 0x28
379
380 # CHECK: sltiu v1,v1,103
381 0x67 0x00 0x63 0x2c
382
383 # CHECK: sltu v1,v1,a1
384 0x2b 0x18 0x65 0x00
385
386 # CHECK: sqrt.d $f12,$f14
387 0x84 0x39 0x20 0x46
388
389 # CHECK: sqrt.s $f6,$f7
390 0x84 0x39 0x00 0x46
391
392 # CHECK: sra a0,v1,0x7
393 0xc3 0x21 0x03 0x00
394
395 # CHECK: sra a0,v1,0x7
396 0xc3 0x21 0x03 0x00
397
398 # CHECK: srav v0,v1,a1
399 0x07 0x10 0xa3 0x00
400
401 # CHECK: srl a0,v1,0x7
402 0xc2 0x21 0x03 0x00
403
404 # CHECK: srlv v0,v1,a1
405 0x06 0x10 0xa3 0x00
406
407 # CHECK: sub.d $f9,$f12,$f14
408 0x41 0x32 0x27 0x46
409
410 # CHECK: sub.s $f9,$f6,$f7
411 0x41 0x32 0x07 0x46
412
413 # CHECK: sub t1,a2,a3
414 0x22 0x48 0xc7 0x00
415
416 # CHECK: subu a0,v1,a1
417 0x23 0x20 0x65 0x00
418
419 # CHECK: sw a0,24(a1)
420 0x18 0x00 0xa4 0xac
421
422 # CHECK: swc1 $f9,9158(a3)
423 0xc6 0x23 0xe9 0xe4
424
425 # CHECK: sync 0x7
426 0xcf 0x01 0x00 0x00
427
428 # CHECK: trunc.w.d $f12,$f14
429 0x8d 0x39 0x20 0x46
430
431 # CHECK: trunc.w.s $f6,$f7
432 0x8d 0x39 0x00 0x46
433
434 # CHECK: wsbh a2,a3
435 0xa0 0x30 0x07 0x7c
436
437 # CHECK: xor v1,v1,a1
438 0x26 0x18 0x65 0x00
439
440 # CHECK: xori t1,a2,0x4567
441 0x67 0x45 0xc9 0x38
0 # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux
1
2 # CHECK: daddiu t3,k0,31949
3 0x67 0x4b 0x7c 0xcd
4
5 # CHECK: daddu k0,at,t3
6 0x00 0x2b 0xd0 0x2d
7
8 # CHECK: ddiv zero,k0,s6
9 0x03 0x56 0x00 0x1e
10
11 # CHECK: ddivu zero,t1,t8
12 0x01 0x38 0x00 0x1f
13
14 # CHECK: dmfc1 v0,$f14
15 0x44 0x22 0x70 0x00
16
17 # CHECK: dmtc1 s7,$f5
18 0x44 0xb7 0x28 0x00
19
20 # CHECK: dmult t3,k0
21 0x01 0x7a 0x00 0x1c
22
23 # CHECK: dmultu s7,t5
24 0x02 0xed 0x00 0x1d
25
26 # CHECK: dsll v1,t8,0x11
27 0x00 0x18 0x1c 0x78
28
29 # CHECK: dsllv gp,k1,t8
30 0x03 0x1b 0xe0 0x14
31
32 # CHECK: dsra at,at,0x1e
33 0x00 0x01 0x0f 0xbb
34
35 # CHECK: dsrav at,at,s8
36 0x03 0xc1 0x08 0x17
37
38 # CHECK: dsrl t2,gp,0x18
39 0x00 0x1c 0x56 0x3a
40
41 # CHECK: dsrlv gp,t2,s7
42 0x02 0xea 0xe0 0x16
43
44 # CHECK: dsubu gp,k1,t8
45 0x03 0x78 0xe0 0x2f
46
47 # CHECK: lw k1,-15155(at)
48 0x8c 0x3b 0xc4 0xcd
49
50 # CHECK: lui at,0x1
51 0x3c 0x01 0x00 0x01
52
53 # CHECK: lwu v1,-1746(v1)
54 0x9c 0x63 0xf9 0x2e
55
56 # CHECK: lui ra,0x1
57 0x3c 0x1f 0x00 0x01
58
59 # CHECK: sw k0,-15159(at)
60 0xac 0x3a 0xc4 0xc9
61
62 # CHECK: ld k0,3958(zero)
63 0xdc 0x1a 0x0f 0x76
64
65 # CHECK: sd a2,17767(zero)
66 0xfc 0x06 0x45 0x67
0 # RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux
1
2 # CHECK: daddiu t3,k0,31949
3 0xcd 0x7c 0x4b 0x67
4
5 # CHECK: daddu k0,at,t3
6 0x2d 0xd0 0x2b 0x00
7
8 # CHECK: ddiv zero,k0,s6
9 0x1e 0x00 0x56 0x03
10
11 # CHECK: ddivu zero,t1,t8
12 0x1f 0x00 0x38 0x01
13
14 # CHECK: dmfc1 v0,$f14
15 0x00 0x70 0x22 0x44
16
17 # CHECK: dmtc1 s7,$f5
18 0x00 0x28 0xb7 0x44
19
20 # CHECK: dmult t3,k0
21 0x1c 0x00 0x7a 0x01
22
23 # CHECK: dmultu s7,t5
24 0x1d 0x00 0xed 0x02
25
26 # CHECK: dsll v1,t8,0x11
27 0x78 0x1c 0x18 0x00
28
29 # CHECK: dsllv gp,k1,t8
30 0x14 0xe0 0x1b 0x03
31
32 # CHECK: dsra at,at,0x1e
33 0xbb 0x0f 0x01 0x00
34
35 # CHECK: dsrav at,at,s8
36 0x17 0x08 0xc1 0x03
37
38 # CHECK: dsrl t2,gp,0x18
39 0x3a 0x56 0x1c 0x00
40
41 # CHECK: dsrlv gp,t2,s7
42 0x16 0xe0 0xea 0x02
43
44 # CHECK: dsubu gp,k1,t8
45 0x2f 0xe0 0x78 0x03
46
47 # CHECK: lw k1,-15155(at)
48 0xcd 0xc4 0x3b 0x8c
49
50 # CHECK: lui at,0x1
51 0x01 0x00 0x01 0x3c
52
53 # CHECK: lwu v1,-1746(v1)
54 0x2e 0xf9 0x63 0x9c
55
56 # CHECK: lui ra,0x1
57 0x01 0x00 0x1f 0x3c
58
59 # CHECK: sw k0,-15159(at)
60 0xc9 0xc4 0x3a 0xac
61
62 # CHECK: ld k0,3958(zero)
63 0x76 0x0f 0x1a 0xdc
64
65 # CHECK: sd a2,17767(zero)
66 0x67 0x45 0x06 0xfc
0 # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2
1
2 # CHECK: daddiu t3,k0,31949
3 0x67 0x4b 0x7c 0xcd
4
5 # CHECK: daddu k0,at,t3
6 0x00 0x2b 0xd0 0x2d
7
8 # CHECK: ddiv zero,k0,s6
9 0x03 0x56 0x00 0x1e
10
11 # CHECK: ddivu zero,t1,t8
12 0x01 0x38 0x00 0x1f
13
14 # CHECK: dmfc1 v0,$f14
15 0x44 0x22 0x70 0x00
16
17 # CHECK: dmtc1 s7,$f5
18 0x44 0xb7 0x28 0x00
19
20 # CHECK: dmult t3,k0
21 0x01 0x7a 0x00 0x1c
22
23 # CHECK: dmultu s7,t5
24 0x02 0xed 0x00 0x1d
25
26 # CHECK: dsll v1,t8,0x11
27 0x00 0x18 0x1c 0x78
28
29 # CHECK: dsllv gp,k1,t8
30 0x03 0x1b 0xe0 0x14
31
32 # CHECK: dsra at,at,0x1e
33 0x00 0x01 0x0f 0xbb
34
35 # CHECK: dsrav at,at,s8
36 0x03 0xc1 0x08 0x17
37
38 # CHECK: dsrl t2,gp,0x18
39 0x00 0x1c 0x56 0x3a
40
41 # CHECK: dsrlv gp,t2,s7
42 0x02 0xea 0xe0 0x16
43
44 # CHECK: dsubu gp,k1,t8
45 0x03 0x78 0xe0 0x2f
46
47 # CHECK: lw k1,-15155(at)
48 0x8c 0x3b 0xc4 0xcd
49
50 # CHECK: lui at,0x1
51 0x3c 0x01 0x00 0x01
52
53 # CHECK: lwu v1,-1746(v1)
54 0x9c 0x63 0xf9 0x2e
55
56 # CHECK: lui ra,0x1
57 0x3c 0x1f 0x00 0x01
58
59 # CHECK: sw k0,-15159(at)
60 0xac 0x3a 0xc4 0xc9
61
62 # CHECK: ld k0,3958(zero)
63 0xdc 0x1a 0x0f 0x76
64
65 # CHECK: sd a2,17767(zero)
66 0xfc 0x06 0x45 0x67
67
68 # CHECK: dclo t1,t8
69 0x73 0x09 0x48 0x25
70
71 # CHECK: dclz k0,t1
72 0x71 0x3a 0xd0 0x24
73
74 # CHECK: dext a3,gp,0x1d,0x1f
75 0x7f 0x87 0xf7 0x43
76
77 # CHECK: dins s4,gp,0xf,0x1
78 0x7f 0x94 0x7b 0xc7
79
80 # CHECK: dsbh a3,gp
81 0x7c 0x1c 0x38 0xa4
82
83 # CHECK: dshd v1,t6
84 0x7c 0x0e 0x19 0x64
85
86 # CHECK: drotr s4,k1,0x6
87 0x00 0x3b 0xa1 0xba
88
89 # CHECK: drotrv t8,s7,a1
90 0x00 0xb7 0xc0 0x56
0 # RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2
1
2 # CHECK: daddiu t3,k0,31949
3 0xcd 0x7c 0x4b 0x67
4
5 # CHECK: daddu k0,at,t3
6 0x2d 0xd0 0x2b 0x00
7
8 # CHECK: ddiv zero,k0,s6
9 0x1e 0x00 0x56 0x03
10
11 # CHECK: ddivu zero,t1,t8
12 0x1f 0x00 0x38 0x01
13
14 # CHECK: dmfc1 v0,$f14
15 0x00 0x70 0x22 0x44
16
17 # CHECK: dmtc1 s7,$f5
18 0x00 0x28 0xb7 0x44
19
20 # CHECK: dmult t3,k0
21 0x1c 0x00 0x7a 0x01
22
23 # CHECK: dmultu s7,t5
24 0x1d 0x00 0xed 0x02
25
26 # CHECK: dsll v1,t8,0x11
27 0x78 0x1c 0x18 0x00
28
29 # CHECK: dsllv gp,k1,t8
30 0x14 0xe0 0x1b 0x03
31
32 # CHECK: dsra at,at,0x1e
33 0xbb 0x0f 0x01 0x00
34
35 # CHECK: dsrav at,at,s8
36 0x17 0x08 0xc1 0x03
37
38 # CHECK: dsrl t2,gp,0x18
39 0x3a 0x56 0x1c 0x00
40
41 # CHECK: dsrlv gp,t2,s7
42 0x16 0xe0 0xea 0x02
43
44 # CHECK: dsubu gp,k1,t8
45 0x2f 0xe0 0x78 0x03
46
47 # CHECK: lw k1,-15155(at)
48 0xcd 0xc4 0x3b 0x8c
49
50 # CHECK: lui at,0x1
51 0x01 0x00 0x01 0x3c
52
53 # CHECK: lwu v1,-1746(v1)
54 0x2e 0xf9 0x63 0x9c
55
56 # CHECK: lui ra,0x1
57 0x01 0x00 0x1f 0x3c
58
59 # CHECK: sw k0,-15159(at)
60 0xc9 0xc4 0x3a 0xac
61
62 # CHECK: ld k0,3958(zero)
63 0x76 0x0f 0x1a 0xdc
64
65 # CHECK: sd a2,17767(zero)
66 0x67 0x45 0x06 0xfc
67
68 # CHECK: dclo t1,t8
69 0x25 0x48 0x09 0x73
70
71 # CHECK: dclz k0,t1
72 0x24 0xd0 0x3a 0x71
73
74 # CHECK: dext a3,gp,0x1d,0x1f
75 0x43 0xf7 0x87 0x7f
76
77 # CHECK: dins s4,gp,0xf,0x1
78 0xc7 0x7b 0x94 0x7f
79
80 # CHECK: dsbh a3,gp
81 0xa4 0x38 0x1c 0x7c
82
83 # CHECK: dshd v1,t6
84 0x64 0x19 0x0e 0x7c
85
86 # CHECK: drotr s4,k1,0x6
87 0xba 0xa1 0x3b 0x00
88
89 # CHECK: drotrv t8,s7,a1
90 0x56 0xc0 0xb7 0x00