llvm.org GIT mirror llvm / ec7ab53
clang-format a bit of code to make the next patch easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203203 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 5 years ago
3 changed file(s) with 99 addition(s) and 115 deletion(s). Raw diff Collapse all Expand all
4242 class MachineOperand {
4343 public:
4444 enum MachineOperandType {
45 MO_Register, ///< Register operand.
46 MO_Immediate, ///< Immediate operand
47 MO_CImmediate, ///< Immediate >64bit operand
48 MO_FPImmediate, ///< Floating-point immediate operand
49 MO_MachineBasicBlock, ///< MachineBasicBlock reference
50 MO_FrameIndex, ///< Abstract Stack Frame Index
51 MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
52 MO_TargetIndex, ///< Target-dependent index+offset operand.
53 MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
54 MO_ExternalSymbol, ///< Name of external global symbol
55 MO_GlobalAddress, ///< Address of a global value
56 MO_BlockAddress, ///< Address of a basic block
57 MO_RegisterMask, ///< Mask of preserved registers.
58 MO_RegisterLiveOut, ///< Mask of live-out registers.
59 MO_Metadata, ///< Metadata reference (for debug info)
60 MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
45 MO_Register, ///< Register operand.
46 MO_Immediate, ///< Immediate operand
47 MO_CImmediate, ///< Immediate >64bit operand
48 MO_FPImmediate, ///< Floating-point immediate operand
49 MO_MachineBasicBlock, ///< MachineBasicBlock reference
50 MO_FrameIndex, ///< Abstract Stack Frame Index
51 MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
52 MO_TargetIndex, ///< Target-dependent index+offset operand.
53 MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
54 MO_ExternalSymbol, ///< Name of external global symbol
55 MO_GlobalAddress, ///< Address of a global value
56 MO_BlockAddress, ///< Address of a basic block
57 MO_RegisterMask, ///< Mask of preserved registers.
58 MO_RegisterLiveOut, ///< Mask of live-out registers.
59 MO_Metadata, ///< Metadata reference (for debug info)
60 MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
6161 };
6262
6363 private:
149149
150150 /// Contents union - This contains the payload for the various operand types.
151151 union {
152 MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
153 const ConstantFP *CFP; // For MO_FPImmediate.
154 const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
155 int64_t ImmVal; // For MO_Immediate.
156 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
157 const MDNode *MD; // For MO_Metadata.
158 MCSymbol *Sym; // For MO_MCSymbol
152 MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
153 const ConstantFP *CFP; // For MO_FPImmediate.
154 const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
155 int64_t ImmVal; // For MO_Immediate.
156 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
157 const MDNode *MD; // For MO_Metadata.
158 MCSymbol *Sym; // For MO_MCSymbol
159159
160160 struct { // For MO_Register.
161161 // Register number is in SmallContents.RegNo.
2121 /// must be the same as in CodeGenTarget.cpp.
2222 ///
2323 namespace TargetOpcode {
24 enum {
25 PHI = 0,
26 INLINEASM = 1,
27 PROLOG_LABEL = 2,
28 EH_LABEL = 3,
29 GC_LABEL = 4,
24 enum {
25 PHI = 0,
26 INLINEASM = 1,
27 PROLOG_LABEL = 2,
28 EH_LABEL = 3,
29 GC_LABEL = 4,
3030
31 /// KILL - This instruction is a noop that is used only to adjust the
32 /// liveness of registers. This can be useful when dealing with
33 /// sub-registers.
34 KILL = 5,
31 /// KILL - This instruction is a noop that is used only to adjust the
32 /// liveness of registers. This can be useful when dealing with
33 /// sub-registers.
34 KILL = 5,
3535
36 /// EXTRACT_SUBREG - This instruction takes two operands: a register
37 /// that has subregisters, and a subregister index. It returns the
38 /// extracted subregister value. This is commonly used to implement
39 /// truncation operations on target architectures which support it.
40 EXTRACT_SUBREG = 6,
36 /// EXTRACT_SUBREG - This instruction takes two operands: a register
37 /// that has subregisters, and a subregister index. It returns the
38 /// extracted subregister value. This is commonly used to implement
39 /// truncation operations on target architectures which support it.
40 EXTRACT_SUBREG = 6,
4141
42 /// INSERT_SUBREG - This instruction takes three operands: a register that
43 /// has subregisters, a register providing an insert value, and a
44 /// subregister index. It returns the value of the first register with the
45 /// value of the second register inserted. The first register is often
46 /// defined by an IMPLICIT_DEF, because it is commonly used to implement
47 /// anyext operations on target architectures which support it.
48 INSERT_SUBREG = 7,
42 /// INSERT_SUBREG - This instruction takes three operands: a register that
43 /// has subregisters, a register providing an insert value, and a
44 /// subregister index. It returns the value of the first register with the
45 /// value of the second register inserted. The first register is often
46 /// defined by an IMPLICIT_DEF, because it is commonly used to implement
47 /// anyext operations on target architectures which support it.
48 INSERT_SUBREG = 7,
4949
50 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
51 IMPLICIT_DEF = 8,
50 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
51 IMPLICIT_DEF = 8,
5252
53 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
54 /// the first operand is an immediate integer constant. This constant is
55 /// often zero, because it is commonly used to assert that the instruction
56 /// defining the register implicitly clears the high bits.
57 SUBREG_TO_REG = 9,
53 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
54 /// the first operand is an immediate integer constant. This constant is
55 /// often zero, because it is commonly used to assert that the instruction
56 /// defining the register implicitly clears the high bits.
57 SUBREG_TO_REG = 9,
5858
59 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
60 /// register-to-register copy into a specific register class. This is only
61 /// used between instruction selection and MachineInstr creation, before
62 /// virtual registers have been created for all the instructions, and it's
63 /// only needed in cases where the register classes implied by the
64 /// instructions are insufficient. It is emitted as a COPY MachineInstr.
65 COPY_TO_REGCLASS = 10,
59 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
60 /// register-to-register copy into a specific register class. This is only
61 /// used between instruction selection and MachineInstr creation, before
62 /// virtual registers have been created for all the instructions, and it's
63 /// only needed in cases where the register classes implied by the
64 /// instructions are insufficient. It is emitted as a COPY MachineInstr.
65 COPY_TO_REGCLASS = 10,
6666
67 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
68 DBG_VALUE = 11,
67 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
68 DBG_VALUE = 11,
6969
70 /// REG_SEQUENCE - This variadic instruction is used to form a register that
71 /// represents a consecutive sequence of sub-registers. It's used as a
72 /// register coalescing / allocation aid and must be eliminated before code
73 /// emission.
74 // In SDNode form, the first operand encodes the register class created by
75 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
76 // pair. Once it has been lowered to a MachineInstr, the regclass operand
77 // is no longer present.
78 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
79 /// After register coalescing references of v1024 should be replace with
80 /// v1027:3, v1025 with v1027:4, etc.
81 REG_SEQUENCE = 12,
70 /// REG_SEQUENCE - This variadic instruction is used to form a register that
71 /// represents a consecutive sequence of sub-registers. It's used as a
72 /// register coalescing / allocation aid and must be eliminated before code
73 /// emission.
74 // In SDNode form, the first operand encodes the register class created by
75 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
76 // pair. Once it has been lowered to a MachineInstr, the regclass operand
77 // is no longer present.
78 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
79 /// After register coalescing references of v1024 should be replace with
80 /// v1027:3, v1025 with v1027:4, etc.
81 REG_SEQUENCE = 12,
8282
83 /// COPY - Target-independent register copy. This instruction can also be
84 /// used to copy between subregisters of virtual registers.
85 COPY = 13,
83 /// COPY - Target-independent register copy. This instruction can also be
84 /// used to copy between subregisters of virtual registers.
85 COPY = 13,
8686
87 /// BUNDLE - This instruction represents an instruction bundle. Instructions
88 /// which immediately follow a BUNDLE instruction which are marked with
89 /// 'InsideBundle' flag are inside the bundle.
90 BUNDLE = 14,
87 /// BUNDLE - This instruction represents an instruction bundle. Instructions
88 /// which immediately follow a BUNDLE instruction which are marked with
89 /// 'InsideBundle' flag are inside the bundle.
90 BUNDLE = 14,
9191
92 /// Lifetime markers.
93 LIFETIME_START = 15,
94 LIFETIME_END = 16,
92 /// Lifetime markers.
93 LIFETIME_START = 15,
94 LIFETIME_END = 16,
9595
96 /// A Stackmap instruction captures the location of live variables at its
97 /// position in the instruction stream. It is followed by a shadow of bytes
98 /// that must lie within the function and not contain another stackmap.
99 STACKMAP = 17,
96 /// A Stackmap instruction captures the location of live variables at its
97 /// position in the instruction stream. It is followed by a shadow of bytes
98 /// that must lie within the function and not contain another stackmap.
99 STACKMAP = 17,
100100
101 /// Patchable call instruction - this instruction represents a call to a
102 /// constant address, followed by a series of NOPs. It is intended to
103 /// support optimizations for dynamic languages (such as javascript) that
104 /// rewrite calls to runtimes with more efficient code sequences.
105 /// This also implies a stack map.
106 PATCHPOINT = 18
107 };
101 /// Patchable call instruction - this instruction represents a call to a
102 /// constant address, followed by a series of NOPs. It is intended to
103 /// support optimizations for dynamic languages (such as javascript) that
104 /// rewrite calls to runtimes with more efficient code sequences.
105 /// This also implies a stack map.
106 PATCHPOINT = 18
107 };
108108 } // end namespace TargetOpcode
109109 } // end namespace llvm
110110
293293 void CodeGenTarget::ComputeInstrsByEnum() const {
294294 // The ordering here must match the ordering in TargetOpcodes.h.
295295 static const char *const FixedInstrs[] = {
296 "PHI",
297 "INLINEASM",
298 "PROLOG_LABEL",
299 "EH_LABEL",
300 "GC_LABEL",
301 "KILL",
302 "EXTRACT_SUBREG",
303 "INSERT_SUBREG",
304 "IMPLICIT_DEF",
305 "SUBREG_TO_REG",
306 "COPY_TO_REGCLASS",
307 "DBG_VALUE",
308 "REG_SEQUENCE",
309 "COPY",
310 "BUNDLE",
311 "LIFETIME_START",
312 "LIFETIME_END",
313 "STACKMAP",
314 "PATCHPOINT",
315 0
316 };
296 "PHI", "INLINEASM", "PROLOG_LABEL", "EH_LABEL",
297 "GC_LABEL", "KILL", "EXTRACT_SUBREG", "INSERT_SUBREG",
298 "IMPLICIT_DEF", "SUBREG_TO_REG", "COPY_TO_REGCLASS", "DBG_VALUE",
299 "REG_SEQUENCE", "COPY", "BUNDLE", "LIFETIME_START",
300 "LIFETIME_END", "STACKMAP", "PATCHPOINT", 0};
317301 const DenseMap &Insts = getInstructions();
318302 for (const char *const *p = FixedInstrs; *p; ++p) {
319303 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);