llvm.org GIT mirror llvm / ebed2cc
[GlobalISel][IRTranslator] Add debug loc with line 0 to constants emitted into the entry block. Constants, including G_GLOBAL_VALUE, are all emitted into the entry block which lets us use the vreg def assuming it dominates all other users. However, it can cause jumpy debug behaviour since the DebugLoc attached to these MIs are from a user instruction that could be in a different block. Fixes PR40887. Differential Revision: https://reviews.llvm.org/D63286 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363331 91177308-0d34-0410-b5e6-96231b3b80d8 Amara Emerson 3 months ago
3 changed file(s) with 89 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
135135 LLVM_DEBUG(dbgs() << "Checking DILocation from " << *CurrInst
136136 << " was copied to " << MI);
137137 #endif
138 assert(CurrInst->getDebugLoc() == MI.getDebugLoc() &&
138 // We allow insts in the entry block to have a debug loc line of 0 because
139 // they could have originated from constants, and we don't want a jumpy
140 // debug experience.
141 assert((CurrInst->getDebugLoc() == MI.getDebugLoc() ||
142 MI.getDebugLoc().getLine() == 0) &&
139143 "Line info was not transferred to all instructions");
140144 }
141145 };
17121716
17131717 bool IRTranslator::translate(const Instruction &Inst) {
17141718 CurBuilder->setDebugLoc(Inst.getDebugLoc());
1715 EntryBuilder->setDebugLoc(Inst.getDebugLoc());
1716 switch(Inst.getOpcode()) {
1719 // We only emit constants into the entry block from here. To prevent jumpy
1720 // debug behaviour set the line to 0.
1721 if (const DebugLoc &DL = Inst.getDebugLoc())
1722 EntryBuilder->setDebugLoc(
1723 DebugLoc::get(0, 0, DL.getScope(), DL.getInlinedAt()));
1724 else
1725 EntryBuilder->setDebugLoc(DebugLoc());
1726
1727 switch (Inst.getOpcode()) {
17171728 #define HANDLE_INST(NUM, OPCODE, CLASS) \
17181729 case Instruction::OPCODE: \
17191730 return translate##OPCODE(Inst, *CurBuilder.get());
0 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 ; RUN: llc -mtriple aarch64 -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
2 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
3 target triple = "arm64-apple-ios5.0.0"
4
5 @var1 = common global i32 0, align 4, !dbg !0
6 @var2 = common global i32 0, align 4, !dbg !6
7
8 ; We check here that the G_GLOBAL_VALUE has a debug loc with line 0.
9 define i32 @main() #0 !dbg !14 {
10 ; CHECK-LABEL: name: main
11 ; CHECK: bb.1.entry:
12 ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
13 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
14 ; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1, debug-location !DILocation(line: 0, scope: !18)
15 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1, debug-location !DILocation(line: 0, scope: !18)
16 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2, debug-location !DILocation(line: 0, scope: !22)
17 ; CHECK: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2, debug-location !DILocation(line: 0, scope: !22)
18 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
19 ; CHECK: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store 4 into %ir.retval)
20 ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0), debug-location !17 :: (load 4 from @var1)
21 ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C1]], debug-location !19
22 ; CHECK: G_BRCOND [[ICMP]](s1), %bb.2, debug-location !20
23 ; CHECK: G_BR %bb.3, debug-location !20
24 ; CHECK: bb.2.if.then:
25 ; CHECK: successors: %bb.3(0x80000000)
26 ; CHECK: G_STORE [[C2]](s32), [[GV1]](p0), debug-location !21 :: (store 4 into @var2)
27 ; CHECK: bb.3.if.end:
28 ; CHECK: $w0 = COPY [[C]](s32), debug-location !24
29 ; CHECK: RET_ReallyLR implicit $w0, debug-location !24
30 entry:
31 %retval = alloca i32, align 4
32 store i32 0, i32* %retval, align 4
33 %0 = load i32, i32* @var1, align 4, !dbg !17
34 %cmp = icmp eq i32 %0, 1, !dbg !19
35 br i1 %cmp, label %if.then, label %if.end, !dbg !20
36
37 if.then:
38 store i32 2, i32* @var2, align 4, !dbg !21
39 br label %if.end, !dbg !23
40
41 if.end:
42 ret i32 0, !dbg !24
43 }
44
45 !llvm.dbg.cu = !{!2}
46 !llvm.module.flags = !{!9, !10, !11, !12}
47 !llvm.ident = !{!13}
48
49 !0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
50 !1 = distinct !DIGlobalVariable(name: "var1", scope: !2, file: !3, line: 1, type: !8, isLocal: false, isDefinition: true)
51 !2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, nameTableKind: GNU)
52 !3 = !DIFile(filename: "dbg.c", directory: "/")
53 !4 = !{}
54 !5 = !{!0, !6}
55 !6 = !DIGlobalVariableExpression(var: !7, expr: !DIExpression())
56 !7 = distinct !DIGlobalVariable(name: "var2", scope: !2, file: !3, line: 2, type: !8, isLocal: false, isDefinition: true)
57 !8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
58 !9 = !{i32 2, !"Dwarf Version", i32 2}
59 !10 = !{i32 2, !"Debug Info Version", i32 3}
60 !11 = !{i32 1, !"wchar_size", i32 4}
61 !12 = !{i32 7, !"PIC Level", i32 2}
62 !13 = !{!"clang"}
63 !14 = distinct !DISubprogram(name: "main", scope: !3, file: !3, line: 3, type: !15, scopeLine: 3, spFlags: DISPFlagDefinition, unit: !2, retainedNodes: !4)
64 !15 = !DISubroutineType(types: !16)
65 !16 = !{!8}
66 !17 = !DILocation(line: 4, column: 7, scope: !18)
67 !18 = distinct !DILexicalBlock(scope: !14, file: !3, line: 4, column: 7)
68 !19 = !DILocation(line: 4, column: 12, scope: !18)
69 !20 = !DILocation(line: 4, column: 7, scope: !14)
70 !21 = !DILocation(line: 5, column: 10, scope: !22)
71 !22 = distinct !DILexicalBlock(scope: !18, file: !3, line: 4, column: 18)
72 !23 = !DILocation(line: 6, column: 3, scope: !22)
73 !24 = !DILocation(line: 7, column: 3, scope: !14)
1313 ; The location of the prologue_end marker should not be affected by the presence
1414 ; of CFI instructions.
1515
16 ; RUN: llc -O0 -filetype=asm < %s | FileCheck %s
16 ; RUN: llc -fast-isel -O0 -filetype=asm < %s | FileCheck %s
1717
1818 ; ModuleID = 'test1.cpp'
1919 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"