llvm.org GIT mirror llvm / ebdeeab
Eliminate asm parser's dependency on TargetMachine: - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
49 changed file(s) with 318 addition(s) and 297 deletion(s). Raw diff Collapse all Expand all
381381 /// matcher, this is true. Targets should set this by inheriting their
382382 /// feature from the AssemblerPredicate class in addition to Predicate.
383383 bit AssemblerMatcherPredicate = 0;
384
385 /// AssemblerCondString - Name of the subtarget feature being tested used
386 /// as alternative condition string used for assembler matcher.
387 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
388 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
389 /// It can also list multiple features separated by ",".
390 /// e.g. "ModeThumb,FeatureThumb2" is translated to
391 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
392 string AssemblerCondString = "";
384393 }
385394
386395 /// NoHonorSignDependentRounding - This predicate is true if support for
688697
689698 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
690699 /// matches instructions and aliases.
691 class AssemblerPredicate {
700 class AssemblerPredicate {
692701 bit AssemblerMatcherPredicate = 1;
702 string AssemblerCondString = cond;
693703 }
694704
695705
1313 #ifndef LLVM_TARGET_TARGETMACHINE_H
1414 #define LLVM_TARGET_TARGETMACHINE_H
1515
16 #include "llvm/ADT/StringRef.h"
1617 #include
1718 #include
1819
9091 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
9192 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
9293 protected: // Can only create subclasses.
93 TargetMachine(const Target &);
94 TargetMachine(const Target &T, StringRef TargetTriple,
95 StringRef CPU, StringRef FS);
9496
9597 /// getSubtargetImpl - virtual method implemented by subclasses that returns
9698 /// a reference to that target's TargetSubtargetInfo-derived member variable.
98100
99101 /// TheTarget - The Target that this machine was created for.
100102 const Target &TheTarget;
103
104 /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
105 /// feature strings the TargetMachine instance is created with.
106 std::string TargetTriple;
107 std::string TargetCPU;
108 std::string TargetFS;
101109
102110 /// AsmInfo - Contains target specific asm information.
103111 ///
113121 virtual ~TargetMachine();
114122
115123 const Target &getTarget() const { return TheTarget; }
124
125 const StringRef getTargetTriple() const { return TargetTriple; }
126 const StringRef getTargetCPU() const { return TargetCPU; }
127 const StringRef getTargetFeatureString() const { return TargetFS; }
116128
117129 // Interfaces to the major aspects of target machine information:
118130 // -- Instruction opcode and operand information
294306 /// implemented with the LLVM target-independent code generator.
295307 ///
296308 class LLVMTargetMachine : public TargetMachine {
297 std::string TargetTriple;
298
299309 protected: // Can only create subclasses.
300 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
310 LLVMTargetMachine(const Target &T, StringRef TargetTriple,
311 StringRef CPU, StringRef FS);
301312
302313 private:
303314 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
310321 virtual void setCodeModelForStatic();
311322
312323 public:
313
314 const std::string &getTargetTriple() const { return TargetTriple; }
315
316324 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
317325 /// specified file emitted. Typically this will involve several steps of code
318326 /// generation. If OptLevel is None, the code generator should emit code as
3434 class MCInstPrinter;
3535 class MCInstrInfo;
3636 class MCRegisterInfo;
37 class MCSubtargetInfo;
3837 class MCStreamer;
3938 class TargetAsmBackend;
4039 class TargetAsmLexer;
6968 StringRef TT);
7069 typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
7170 typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
72 typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
73 StringRef CPU,
74 StringRef Features);
7571 typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
7672 const std::string &TT,
7773 const std::string &CPU,
8278 const std::string &TT);
8379 typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,
8480 const MCAsmInfo &MAI);
85 typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P,
86 TargetMachine &TM);
81 typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T, StringRef TT,
82 StringRef CPU, StringRef Features,
83 MCAsmParser &P);
8784 typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
8885 typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
8986 unsigned SyntaxVariant,
139136 /// if registered.
140137 MCRegInfoCtorFnTy MCRegInfoCtorFn;
141138
142 /// MCSubtargetInfoCtorFn - Constructor function for this target's
143 /// MCSubtargetInfo, if registered.
144 MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
145
146139 /// TargetMachineCtorFn - Construction function for this target's
147140 /// TargetMachine, if registered.
148141 TargetMachineCtorTy TargetMachineCtorFn;
266259 if (!MCRegInfoCtorFn)
267260 return 0;
268261 return MCRegInfoCtorFn();
269 }
270
271 /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
272 ///
273 /// \arg Triple - This argument is used to determine the target machine
274 /// feature set; it should always be provided. Generally this should be
275 /// either the target triple from the module, or the target triple of the
276 /// host if that does not exist.
277 /// \arg CPU - This specifies the name of the target CPU.
278 /// \arg Features - This specifies the string representation of the
279 /// additional target features.
280 MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU,
281 StringRef Features) const {
282 if (!MCSubtargetInfoCtorFn)
283 return 0;
284 return MCSubtargetInfoCtorFn(Triple, CPU, Features);
285262 }
286263
287264 /// createTargetMachine - Create a target specific machine implementation
321298 ///
322299 /// \arg Parser - The target independent parser implementation to use for
323300 /// parsing and lexing.
324 TargetAsmParser *createAsmParser(MCAsmParser &Parser,
325 TargetMachine &TM) const {
301 TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU,
302 StringRef Features, MCAsmParser &Parser) const {
326303 if (!AsmParserCtorFn)
327304 return 0;
328 return AsmParserCtorFn(*this, Parser, TM);
305 return AsmParserCtorFn(*this, Triple, CPU, Features, Parser);
329306 }
330307
331308 /// createAsmPrinter - Create a target specific assembly printer pass. This
527504 T.MCRegInfoCtorFn = Fn;
528505 }
529506
530 /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
531 /// the given target.
532 ///
533 /// Clients are responsible for ensuring that registration doesn't occur
534 /// while another thread is attempting to access the registry. Typically
535 /// this is done by initializing all targets at program startup.
536 ///
537 /// @param T - The target being registered.
538 /// @param Fn - A function to construct a MCSubtargetInfo for the target.
539 static void RegisterMCSubtargetInfo(Target &T,
540 Target::MCSubtargetInfoCtorFnTy Fn) {
541 // Ignore duplicate registration.
542 if (!T.MCSubtargetInfoCtorFn)
543 T.MCSubtargetInfoCtorFn = Fn;
544 }
545
546507 /// RegisterTargetMachine - Register a TargetMachine implementation for the
547508 /// given target.
548509 ///
819780 }
820781 };
821782
822 /// RegisterMCSubtargetInfo - Helper template for registering a target
823 /// subtarget info implementation. This invokes the static "Create" method
824 /// on the class to actually do the construction. Usage:
825 ///
826 /// extern "C" void LLVMInitializeFooTarget() {
827 /// extern Target TheFooTarget;
828 /// RegisterMCSubtargetInfo X(TheFooTarget);
829 /// }
830 template
831 struct RegisterMCSubtargetInfo {
832 RegisterMCSubtargetInfo(Target &T) {
833 TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
834 }
835 private:
836 static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU,
837 StringRef FS) {
838 return new MCSubtargetInfoImpl();
839 }
840 };
841
842 /// RegisterMCSubtargetInfoFn - Helper template for registering a target
843 /// subtarget info implementation. This invokes the specified function to
844 /// do the construction. Usage:
845 ///
846 /// extern "C" void LLVMInitializeFooTarget() {
847 /// extern Target TheFooTarget;
848 /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
849 /// }
850 struct RegisterMCSubtargetInfoFn {
851 RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
852 TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
853 }
854 };
855
856783 /// RegisterTargetMachine - Helper template for registering a target machine
857784 /// implementation, for use in the target machine initialization
858785 /// function. Usage:
930857 }
931858
932859 private:
933 static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P,
934 TargetMachine &TM) {
935 return new AsmParserImpl(T, P, TM);
860 static TargetAsmParser *Allocator(const Target &T, StringRef TT,
861 StringRef CPU, StringRef FS,
862 MCAsmParser &P) {
863 return new AsmParserImpl(T, TT, CPU, FS, P);
936864 }
937865 };
938866
110110 OwningPtr Parser(createMCAsmParser(TM.getTarget(), SrcMgr,
111111 OutContext, OutStreamer,
112112 *MAI));
113 OwningPtr TAP(TM.getTarget().createAsmParser(*Parser, TM));
113
114 OwningPtr
115 TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(),
116 TM.getTargetCPU(),
117 TM.getTargetFeatureString(),
118 *Parser));
114119 if (!TAP)
115120 report_fatal_error("Inline asm not supported by this streamer because"
116121 " we don't have an asm parser for this target\n");
9797 EnableFastISelOption("fast-isel", cl::Hidden,
9898 cl::desc("Enable the \"fast\" instruction selector"));
9999
100 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
101 const std::string &Triple)
102 : TargetMachine(T), TargetTriple(Triple) {
103 AsmInfo = T.createAsmInfo(TargetTriple);
100 LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
101 StringRef CPU, StringRef FS)
102 : TargetMachine(T, Triple, CPU, FS) {
103 AsmInfo = T.createAsmInfo(Triple);
104104 }
105105
106106 // Set the default code model for the JIT for a generic target.
142142 TargetAsmBackend *TAB = 0;
143143 if (ShowMCEncoding) {
144144 MCE = getTarget().createCodeEmitter(*this, *Context);
145 TAB = getTarget().createAsmBackend(TargetTriple);
145 TAB = getTarget().createAsmBackend(getTargetTriple());
146146 }
147147
148148 MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
159159 // Create the code emitter for the target if it exists. If not, .o file
160160 // emission fails.
161161 MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
162 TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
162 TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple());
163163 if (MCE == 0 || TAB == 0)
164164 return true;
165165
166 AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,
167 *TAB, Out, MCE,
166 AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(),
167 *Context, *TAB, Out, MCE,
168168 hasMCRelaxAll(),
169169 hasMCNoExecStack()));
170170 AsmStreamer.get()->InitSections();
240240 // Create the code emitter for the target if it exists. If not, .o file
241241 // emission fails.
242242 MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx);
243 TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
243 TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple());
244244 if (MCE == 0 || TAB == 0)
245245 return true;
246246
247247 OwningPtr AsmStreamer;
248 AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Ctx,
248 AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), *Ctx,
249249 *TAB, Out, MCE,
250250 hasMCRelaxAll(),
251251 hasMCNoExecStack()));
170170 std::string featureString;
171171 TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU,
172172 featureString));
173
173
174174 const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo();
175175
176176 if (!registerInfo)
182182
183183 if (!AsmInfo)
184184 return;
185
185
186186 Disassembler.reset(Tgt->createMCDisassembler());
187187
188188 if (!Disassembler)
370370 OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr,
371371 context, *streamer,
372372 *AsmInfo));
373 OwningPtr TargetParser(Tgt->createAsmParser(*genericParser,
374 *TargetMachine));
373
374 StringRef triple = tripleFromArch(Key.Arch);
375 OwningPtr TargetParser(Tgt->createAsmParser(triple, "", "",
376 *genericParser));
375377
376378 AsmToken OpcodeToken = genericParser->Lex();
377379 AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to
4040 class MCInst;
4141 class MCParsedAsmOperand;
4242 class MCStreamer;
43 class MCSubtargetInfo;
4344 template class SmallVectorImpl;
4445 class SourceMgr;
4546 class Target;
146146 //===----------------------------------------------------------------------===//
147147 // ARM Instruction Predicate Definitions.
148148 //
149 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
149 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
150 AssemblerPredicate<"HasV4TOps">;
150151 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
151152 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
152 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
153 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
153 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
154 AssemblerPredicate<"HasV5TEOps">;
155 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
156 AssemblerPredicate<"HasV6Ops">;
154157 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
155 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
158 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
159 AssemblerPredicate<"HasV6T2Ops">;
156160 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
157 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
161 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
162 AssemblerPredicate<"HasV7Ops">;
158163 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
159 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
160 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
161 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
162 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
163 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
164 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
165 AssemblerPredicate<"FeatureVFP2">;
166 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
167 AssemblerPredicate<"FeatureVFP3">;
168 def HasNEON : Predicate<"Subtarget->hasNEON()">,
169 AssemblerPredicate<"FeatureNEON">;
170 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
171 AssemblerPredicate<"FeatureFP16">;
172 def HasDivide : Predicate<"Subtarget->hasDivide()">,
173 AssemblerPredicate<"FeatureHWDiv">;
164174 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
165 AssemblerPredicate;
175 AssemblerPredicate<"FeatureT2XtPk">;
166176 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
167 AssemblerPredicate;
177 AssemblerPredicate<"FeatureDSPThumb2">;
168178 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
169 AssemblerPredicate;
179 AssemblerPredicate<"FeatureDB">;
170180 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
171 AssemblerPredicate;
181 AssemblerPredicate<"FeatureMP">;
172182 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
173183 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
174 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
184 def IsThumb : Predicate<"Subtarget->isThumb()">,
185 AssemblerPredicate<"ModeThumb">;
175186 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
176 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
177 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
187 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
188 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
189 def IsARM : Predicate<"!Subtarget->isThumb()">,
190 AssemblerPredicate<"!ModeThumb">;
178191 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
179192 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
180193
1717 #include "llvm/Support/CommandLine.h"
1818 #include "llvm/ADT/SmallVector.h"
1919
20 #define GET_SUBTARGETINFO_CTOR
20 #define GET_SUBTARGETINFO_ENUM
2121 #define GET_SUBTARGETINFO_MC_DESC
2222 #define GET_SUBTARGETINFO_TARGET_DESC
23 #define GET_SUBTARGETINFO_CTOR
2324 #include "ARMGenSubtargetInfo.inc"
2425
2526 using namespace llvm;
7979 const std::string &TT,
8080 const std::string &CPU,
8181 const std::string &FS)
82 : LLVMTargetMachine(T, TT),
82 : LLVMTargetMachine(T, TT, CPU, FS),
8383 Subtarget(TT, CPU, FS),
8484 JITInfo(),
8585 InstrItins(Subtarget.getInstrItineraryData()) {
1919 #include "llvm/MC/MCStreamer.h"
2020 #include "llvm/MC/MCExpr.h"
2121 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
2223 #include "llvm/Target/TargetRegistry.h"
2324 #include "llvm/Target/TargetAsmParser.h"
2425 #include "llvm/Support/SourceMgr.h"
2728 #include "llvm/ADT/StringExtras.h"
2829 #include "llvm/ADT/StringSwitch.h"
2930 #include "llvm/ADT/Twine.h"
31
32 #define GET_SUBTARGETINFO_ENUM
33 #include "ARMGenSubtargetInfo.inc"
34
3035 using namespace llvm;
3136
3237 namespace {
3540
3641 class ARMAsmParser : public TargetAsmParser {
3742 MCAsmParser &Parser;
38 TargetMachine &TM;
43 MCSubtargetInfo *STI;
3944
4045 MCAsmParser &getParser() const { return Parser; }
4146 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
7883 void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
7984 bool &CanAcceptPredicationCode);
8085
86 bool isThumb() const {
87 // FIXME: Can tablegen auto-generate this?
88 return (STI->getFeatureBits() & ARM::ModeThumb) != 0;
89 }
90
91 bool isThumbOne() const {
92 return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0;
93 }
94
8195 /// @name Auto-generated Match Functions
8296 /// {
8397
112126 const SmallVectorImpl &);
113127
114128 public:
115 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
116 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
117 MCAsmParserExtension::Initialize(_Parser);
118 // Initialize the set of available features.
119 setAvailableFeatures(ComputeAvailableFeatures(
120 &TM.getSubtarget()));
121 }
129 ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
130 MCAsmParser &_Parser)
131 : TargetAsmParser(T), Parser(_Parser) {
132 STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS);
133
134 MCAsmParserExtension::Initialize(_Parser);
135 // Initialize the set of available features.
136 setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
137 }
122138
123139 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
124140 SmallVectorImpl &Operands);
18511867 void ARMAsmParser::
18521868 GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
18531869 bool &CanAcceptPredicationCode) {
1854 bool isThumbOne = TM.getSubtarget().isThumb1Only();
1855 bool isThumb = TM.getSubtarget().isThumb();
1856
18571870 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
18581871 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
18591872 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
18621875 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
18631876 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
18641877 Mnemonic == "eor" || Mnemonic == "smlal" ||
1865 (Mnemonic == "mov" && !isThumbOne)) {
1878 (Mnemonic == "mov" && !isThumbOne())) {
18661879 CanAcceptCarrySet = true;
18671880 } else {
18681881 CanAcceptCarrySet = false;
18791892 CanAcceptPredicationCode = true;
18801893 }
18811894
1882 if (isThumb)
1895 if (isThumb())
18831896 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
18841897 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
18851898 CanAcceptPredicationCode = false;
22062219 // includes Feature_IsThumb or not to match the right instructions. This is
22072220 // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine.
22082221 if (Val == 16){
2209 assert(TM.getSubtarget().isThumb() &&
2222 assert(isThumb() &&
22102223 "switching between arm/thumb not yet suppported via .code 16)");
22112224 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
22122225 }
22132226 else{
2214 assert(!TM.getSubtarget().isThumb() &&
2227 assert(!isThumb() &&
22152228 "switching between thumb/arm not yet suppported via .code 32)");
22162229 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
22172230 }
2222 #define GET_INSTRINFO_MC_DESC
2323 #include "ARMGenInstrInfo.inc"
2424
25 #define GET_SUBTARGETINFO_ENUM
2526 #define GET_SUBTARGETINFO_MC_DESC
2627 #include "ARMGenSubtargetInfo.inc"
2728
2829 using namespace llvm;
29
30 MCInstrInfo *createARMMCInstrInfo() {
31 MCInstrInfo *X = new MCInstrInfo();
32 InitARMMCInstrInfo(X);
33 return X;
34 }
35
36 MCRegisterInfo *createARMMCRegisterInfo() {
37 MCRegisterInfo *X = new MCRegisterInfo();
38 InitARMMCRegisterInfo(X);
39 return X;
40 }
41
42 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
43 StringRef FS) {
44 std::string ArchFS = ARM_MC::ParseARMTriple(TT);
45 if (!FS.empty()) {
46 if (!ArchFS.empty())
47 ArchFS = ArchFS + "," + FS.str();
48 else
49 ArchFS = FS;
50 }
51
52 MCSubtargetInfo *X = new MCSubtargetInfo();
53 InitARMMCSubtargetInfo(X, CPU, ArchFS);
54 return X;
55 }
56
57 // Force static initialization.
58 extern "C" void LLVMInitializeARMMCInstrInfo() {
59 RegisterMCInstrInfo X(TheARMTarget);
60 RegisterMCInstrInfo Y(TheThumbTarget);
61
62 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
63 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
64 }
65
66 extern "C" void LLVMInitializeARMMCRegInfo() {
67 RegisterMCRegInfo X(TheARMTarget);
68 RegisterMCRegInfo Y(TheThumbTarget);
69
70 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
71 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
72 }
73
74 extern "C" void LLVMInitializeARMMCSubtargetInfo() {
75 RegisterMCSubtargetInfo X(TheARMTarget);
76 RegisterMCSubtargetInfo Y(TheThumbTarget);
77
78 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
79 createARMMCSubtargetInfo);
80 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
81 createARMMCSubtargetInfo);
82 }
8330
8431 std::string ARM_MC::ParseARMTriple(StringRef TT) {
8532 // Set the boolean corresponding to the current target triple, or the default
13481
13582 return ARMArchFeature;
13683 }
84
85 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
86 StringRef FS) {
87 std::string ArchFS = ARM_MC::ParseARMTriple(TT);
88 if (!FS.empty()) {
89 if (!ArchFS.empty())
90 ArchFS = ArchFS + "," + FS.str();
91 else
92 ArchFS = FS;
93 }
94
95 MCSubtargetInfo *X = new MCSubtargetInfo();
96 InitARMMCSubtargetInfo(X, CPU, ArchFS);
97 return X;
98 }
99
100 MCInstrInfo *createARMMCInstrInfo() {
101 MCInstrInfo *X = new MCInstrInfo();
102 InitARMMCInstrInfo(X);
103 return X;
104 }
105
106 MCRegisterInfo *createARMMCRegisterInfo() {
107 MCRegisterInfo *X = new MCRegisterInfo();
108 InitARMMCRegisterInfo(X);
109 return X;
110 }
111
112 // Force static initialization.
113 extern "C" void LLVMInitializeARMMCInstrInfo() {
114 RegisterMCInstrInfo X(TheARMTarget);
115 RegisterMCInstrInfo Y(TheThumbTarget);
116
117 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
118 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
119 }
120
121 extern "C" void LLVMInitializeARMMCRegInfo() {
122 RegisterMCRegInfo X(TheARMTarget);
123 RegisterMCRegInfo Y(TheThumbTarget);
124
125 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
126 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
127 }
1616 #include
1717
1818 namespace llvm {
19 class MCSubtargetInfo;
1920 class Target;
2021 class StringRef;
2122
2324
2425 namespace ARM_MC {
2526 std::string ParseARMTriple(StringRef TT);
27
28 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
29 /// This is exposed so Asm parser, etc. do not need to go through
30 /// TargetRegistry.
31 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
32 StringRef FS);
2633 }
2734
2835 } // End llvm namespace
1313 #include "AlphaSubtarget.h"
1414 #include "Alpha.h"
1515
16 #define GET_SUBTARGETINFO_CTOR
16 #define GET_SUBTARGETINFO_ENUM
1717 #define GET_SUBTARGETINFO_MC_DESC
1818 #define GET_SUBTARGETINFO_TARGET_DESC
19 #define GET_SUBTARGETINFO_CTOR
1920 #include "AlphaGenSubtargetInfo.inc"
2021
2122 using namespace llvm;
2626 AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT,
2727 const std::string &CPU,
2828 const std::string &FS)
29 : LLVMTargetMachine(T, TT),
29 : LLVMTargetMachine(T, TT, CPU, FS),
3030 DataLayout("e-f128:128:128-n64"),
3131 FrameLowering(Subtarget),
3232 Subtarget(TT, CPU, FS),
1212
1313 #include "BlackfinSubtarget.h"
1414
15 #define GET_SUBTARGETINFO_CTOR
15 #define GET_SUBTARGETINFO_ENUM
1616 #define GET_SUBTARGETINFO_MC_DESC
1717 #define GET_SUBTARGETINFO_TARGET_DESC
18 #define GET_SUBTARGETINFO_CTOR
1819 #include "BlackfinGenSubtargetInfo.inc"
1920
2021 using namespace llvm;
2727 const std::string &TT,
2828 const std::string &CPU,
2929 const std::string &FS)
30 : LLVMTargetMachine(T, TT),
30 : LLVMTargetMachine(T, TT, CPU, FS),
3131 DataLayout("e-p:32:32-i64:32-f64:32-n32"),
3232 Subtarget(TT, CPU, FS),
3333 TLInfo(*this),
2121 struct CTargetMachine : public TargetMachine {
2222 CTargetMachine(const Target &T, const std::string &TT,
2323 const std::string &CPU, const std::string &FS)
24 : TargetMachine(T) {}
24 : TargetMachine(T, TT, CPU, FS) {}
2525
2626 virtual bool addPassesToEmitFile(PassManagerBase &PM,
2727 formatted_raw_ostream &Out,
1212
1313 #include "SPUSubtarget.h"
1414 #include "SPU.h"
15 #include "SPURegisterInfo.h"
1516 #include "llvm/ADT/SmallVector.h"
16 #include "SPURegisterInfo.h"
1717
18 #define GET_SUBTARGETINFO_CTOR
18 #define GET_SUBTARGETINFO_ENUM
1919 #define GET_SUBTARGETINFO_MC_DESC
2020 #define GET_SUBTARGETINFO_TARGET_DESC
21 #define GET_SUBTARGETINFO_CTOR
2122 #include "SPUGenSubtargetInfo.inc"
2223
2324 using namespace llvm;
3535
3636 SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT,
3737 const std::string &CPU,const std::string &FS)
38 : LLVMTargetMachine(T, TT),
38 : LLVMTargetMachine(T, TT, CPU, FS),
3939 Subtarget(TT, CPU, FS),
4040 DataLayout(Subtarget.getTargetDataString()),
4141 InstrInfo(*this),
2323 struct CPPTargetMachine : public TargetMachine {
2424 CPPTargetMachine(const Target &T, const std::string &TT,
2525 const std::string &CPU, const std::string &FS)
26 : TargetMachine(T) {}
26 : TargetMachine(T, TT, CPU, FS) {}
2727
2828 virtual bool addPassesToEmitFile(PassManagerBase &PM,
2929 formatted_raw_ostream &Out,
3131
3232 class MBlazeAsmParser : public TargetAsmParser {
3333 MCAsmParser &Parser;
34 TargetMachine &TM;
3534
3635 MCAsmParser &getParser() const { return Parser; }
3736 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
6362
6463
6564 public:
66 MBlazeAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
67 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
65 MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
66 MCAsmParser &_Parser)
67 : TargetAsmParser(T), Parser(_Parser) {}
6868
6969 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
7070 SmallVectorImpl &Operands);
1515 #include "MBlazeRegisterInfo.h"
1616 #include "llvm/Support/CommandLine.h"
1717
18 #define GET_SUBTARGETINFO_CTOR
18 #define GET_SUBTARGETINFO_ENUM
1919 #define GET_SUBTARGETINFO_MC_DESC
2020 #define GET_SUBTARGETINFO_TARGET_DESC
21 #define GET_SUBTARGETINFO_CTOR
2122 #include "MBlazeGenSubtargetInfo.inc"
2223
2324 using namespace llvm;
6061 CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
6162 return HasItin && OptLevel >= CodeGenOpt::Default;
6263 }
63
8080 MBlazeTargetMachine::
8181 MBlazeTargetMachine(const Target &T, const std::string &TT,
8282 const std::string &CPU, const std::string &FS):
83 LLVMTargetMachine(T, TT),
83 LLVMTargetMachine(T, TT, CPU, FS),
8484 Subtarget(TT, CPU, FS),
8585 DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
8686 InstrInfo(*this),
1313 #include "MSP430Subtarget.h"
1414 #include "MSP430.h"
1515
16 #define GET_SUBTARGETINFO_CTOR
16 #define GET_SUBTARGETINFO_ENUM
1717 #define GET_SUBTARGETINFO_MC_DESC
1818 #define GET_SUBTARGETINFO_TARGET_DESC
19 #define GET_SUBTARGETINFO_CTOR
1920 #include "MSP430GenSubtargetInfo.inc"
2021
2122 using namespace llvm;
2929 const std::string &TT,
3030 const std::string &CPU,
3131 const std::string &FS)
32 : LLVMTargetMachine(T, TT),
32 : LLVMTargetMachine(T, TT, CPU, FS),
3333 Subtarget(TT, CPU, FS),
3434 // FIXME: Check TargetData string.
3535 DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
1313 #include "MipsSubtarget.h"
1414 #include "Mips.h"
1515
16 #define GET_SUBTARGETINFO_CTOR
16 #define GET_SUBTARGETINFO_ENUM
1717 #define GET_SUBTARGETINFO_MC_DESC
1818 #define GET_SUBTARGETINFO_TARGET_DESC
19 #define GET_SUBTARGETINFO_CTOR
1920 #include "MipsGenSubtargetInfo.inc"
2021
2122 using namespace llvm;
3636 MipsTargetMachine(const Target &T, const std::string &TT,
3737 const std::string &CPU, const std::string &FS,
3838 bool isLittle=false):
39 LLVMTargetMachine(T, TT),
39 LLVMTargetMachine(T, TT, CPU, FS),
4040 Subtarget(TT, CPU, FS, isLittle),
4141 DataLayout(isLittle ?
4242 std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
1313 #include "PTXSubtarget.h"
1414 #include "llvm/Support/ErrorHandling.h"
1515
16 #define GET_SUBTARGETINFO_CTOR
16 #define GET_SUBTARGETINFO_ENUM
1717 #define GET_SUBTARGETINFO_MC_DESC
1818 #define GET_SUBTARGETINFO_TARGET_DESC
19 #define GET_SUBTARGETINFO_CTOR
1920 #include "PTXGenSubtargetInfo.inc"
2021
2122 using namespace llvm;
5454 const std::string &CPU,
5555 const std::string &FS,
5656 bool is64Bit)
57 : LLVMTargetMachine(T, TT),
57 : LLVMTargetMachine(T, TT, CPU, FS),
5858 DataLayout(is64Bit ? DataLayout64 : DataLayout32),
5959 Subtarget(TT, CPU, FS, is64Bit),
6060 FrameLowering(Subtarget),
1616 #include "llvm/Target/TargetMachine.h"
1717 #include
1818
19 #define GET_SUBTARGETINFO_CTOR
19 #define GET_SUBTARGETINFO_ENUM
2020 #define GET_SUBTARGETINFO_MC_DESC
2121 #define GET_SUBTARGETINFO_TARGET_DESC
22 #define GET_SUBTARGETINFO_CTOR
2223 #include "PPCGenSubtargetInfo.inc"
2324
2425 using namespace llvm;
6868 PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
6969 const std::string &CPU,
7070 const std::string &FS, bool is64Bit)
71 : LLVMTargetMachine(T, TT),
71 : LLVMTargetMachine(T, TT, CPU, FS),
7272 Subtarget(TT, CPU, FS, is64Bit),
7373 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
7474 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
1212
1313 #include "SparcSubtarget.h"
1414
15 #define GET_SUBTARGETINFO_CTOR
15 #define GET_SUBTARGETINFO_ENUM
1616 #define GET_SUBTARGETINFO_MC_DESC
1717 #define GET_SUBTARGETINFO_TARGET_DESC
18 #define GET_SUBTARGETINFO_CTOR
1819 #include "SparcGenSubtargetInfo.inc"
1920
2021 using namespace llvm;
3131 SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT,
3232 const std::string &CPU,
3333 const std::string &FS, bool is64bit)
34 : LLVMTargetMachine(T, TT),
34 : LLVMTargetMachine(T, TT, CPU, FS),
3535 Subtarget(TT, CPU, FS, is64bit),
3636 DataLayout(Subtarget.getDataLayout()),
3737 TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
1515 #include "llvm/GlobalValue.h"
1616 #include "llvm/Target/TargetMachine.h"
1717
18 #define GET_SUBTARGETINFO_CTOR
18 #define GET_SUBTARGETINFO_ENUM
1919 #define GET_SUBTARGETINFO_MC_DESC
2020 #define GET_SUBTARGETINFO_TARGET_DESC
21 #define GET_SUBTARGETINFO_CTOR
2122 #include "SystemZGenSubtargetInfo.inc"
2223
2324 using namespace llvm;
2525 const std::string &TT,
2626 const std::string &CPU,
2727 const std::string &FS)
28 : LLVMTargetMachine(T, TT),
28 : LLVMTargetMachine(T, TT, CPU, FS),
2929 Subtarget(TT, CPU, FS),
3030 DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
3131 "-f64:64:64-f128:128:128-a0:16:16-n32:64"),
215215 // TargetMachine Class
216216 //
217217
218 TargetMachine::TargetMachine(const Target &T)
219 : TheTarget(T), AsmInfo(0),
218 TargetMachine::TargetMachine(const Target &T,
219 StringRef TT, StringRef CPU, StringRef FS)
220 : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), AsmInfo(0),
220221 MCRelaxAll(false),
221222 MCNoExecStack(false),
222223 MCSaveTempLabels(false),
1414 #include "llvm/MC/MCStreamer.h"
1515 #include "llvm/MC/MCExpr.h"
1616 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
1718 #include "llvm/MC/MCParser/MCAsmLexer.h"
1819 #include "llvm/MC/MCParser/MCAsmParser.h"
1920 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
2425 #include "llvm/ADT/Twine.h"
2526 #include "llvm/Support/SourceMgr.h"
2627 #include "llvm/Support/raw_ostream.h"
28
29 #define GET_SUBTARGETINFO_ENUM
30 #include "X86GenSubtargetInfo.inc"
31
2732 using namespace llvm;
2833
2934 namespace {
3136
3237 class X86ATTAsmParser : public TargetAsmParser {
3338 MCAsmParser &Parser;
34 TargetMachine &TM;
35
36 protected:
37 unsigned Is64Bit : 1;
39 MCSubtargetInfo *STI;
3840
3941 private:
4042 MCAsmParser &getParser() const { return Parser; }
6062 /// or %es:(%edi) in 32bit mode.
6163 bool isDstOp(X86Operand &Op);
6264
65 bool is64Bit() {
66 // FIXME: Can tablegen auto-generate this?
67 return (STI->getFeatureBits() & X86::Mode64Bit) != 0;
68 }
69
6370 /// @name Auto-generated Matcher Functions
6471 /// {
6572
6976 /// }
7077
7178 public:
72 X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM)
73 : TargetAsmParser(T), Parser(parser), TM(TM) {
79 X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
80 MCAsmParser &parser)
81 : TargetAsmParser(T), Parser(parser) {
82 STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS);
7483
7584 // Initialize the set of available features.
76 setAvailableFeatures(ComputeAvailableFeatures(
77 &TM.getSubtarget()));
85 setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
7886 }
7987 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
8088
8391
8492 virtual bool ParseDirective(AsmToken DirectiveID);
8593 };
86
87 class X86_32ATTAsmParser : public X86ATTAsmParser {
88 public:
89 X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
90 : X86ATTAsmParser(T, Parser, TM) {
91 Is64Bit = false;
92 }
93 };
94
95 class X86_64ATTAsmParser : public X86ATTAsmParser {
96 public:
97 X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
98 : X86ATTAsmParser(T, Parser, TM) {
99 Is64Bit = true;
100 }
101 };
102
10394 } // end anonymous namespace
10495
10596 /// @name Auto-generated Match Functions
364355 } // end anonymous namespace.
365356
366357 bool X86ATTAsmParser::isSrcOp(X86Operand &Op) {
367 unsigned basereg = Is64Bit ? X86::RSI : X86::ESI;
358 unsigned basereg = is64Bit() ? X86::RSI : X86::ESI;
368359
369360 return (Op.isMem() &&
370361 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
374365 }
375366
376367 bool X86ATTAsmParser::isDstOp(X86Operand &Op) {
377 unsigned basereg = Is64Bit ? X86::RDI : X86::EDI;
368 unsigned basereg = is64Bit() ? X86::RDI : X86::EDI;
378369
379370 return Op.isMem() && Op.Mem.SegReg == X86::ES &&
380371 isa(Op.Mem.Disp) &&
405396 // FIXME: This should be done using Requires and
406397 // Requires so "eiz" usage in 64-bit instructions
407398 // can be also checked.
408 if (RegNo == X86::RIZ && !Is64Bit)
399 if (RegNo == X86::RIZ && !is64Bit())
409400 return Error(Tok.getLoc(), "riz register in 64-bit mode only");
410401
411402 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
825816 // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
826817 if (Name.startswith("movs") && Operands.size() == 3 &&
827818 (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
828 (Is64Bit && Name == "movsq"))) {
819 (is64Bit() && Name == "movsq"))) {
829820 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
830821 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
831822 if (isSrcOp(Op) && isDstOp(Op2)) {
838829 // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
839830 if (Name.startswith("lods") && Operands.size() == 3 &&
840831 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
841 Name == "lodsl" || (Is64Bit && Name == "lodsq"))) {
832 Name == "lodsl" || (is64Bit() && Name == "lodsq"))) {
842833 X86Operand *Op1 = static_cast(Operands[1]);
843834 X86Operand *Op2 = static_cast(Operands[2]);
844835 if (isSrcOp(*Op1) && Op2->isReg()) {
868859 // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
869860 if (Name.startswith("stos") && Operands.size() == 3 &&
870861 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
871 Name == "stosl" || (Is64Bit && Name == "stosq"))) {
862 Name == "stosl" || (is64Bit() && Name == "stosq"))) {
872863 X86Operand *Op1 = static_cast(Operands[1]);
873864 X86Operand *Op2 = static_cast(Operands[2]);
874865 if (isDstOp(*Op2) && Op1->isReg()) {
11431134
11441135 // Force static initialization.
11451136 extern "C" void LLVMInitializeX86AsmParser() {
1146 RegisterAsmParser X(TheX86_32Target);
1147 RegisterAsmParser_64ATTAsmParser> Y(TheX86_64Target);
1137 RegisterAsmParserATTAsmParser> X(TheX86_32Target);
1138 RegisterAsmParser Y(TheX86_64Target);
11481139 LLVMInitializeX86AsmLexer();
11491140 }
11501141
2424 #define GET_INSTRINFO_MC_DESC
2525 #include "X86GenInstrInfo.inc"
2626
27 #define GET_SUBTARGETINFO_ENUM
2728 #define GET_SUBTARGETINFO_MC_DESC
2829 #include "X86GenSubtargetInfo.inc"
2930
3435 Triple TheTriple(TT);
3536 if (TheTriple.getArch() == Triple::x86_64)
3637 return "+64bit-mode";
37 return "";
38 return "-64bit-mode";
3839 }
3940
4041 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
127128 return false;
128129 }
129130
130 MCInstrInfo *createX86MCInstrInfo() {
131 MCInstrInfo *X = new MCInstrInfo();
132 InitX86MCInstrInfo(X);
133 return X;
134 }
135
136 MCRegisterInfo *createX86MCRegisterInfo() {
137 MCRegisterInfo *X = new MCRegisterInfo();
138 InitX86MCRegisterInfo(X);
139 return X;
140 }
141
142 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
143 StringRef FS) {
131 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
132 StringRef FS) {
144133 std::string ArchFS = X86_MC::ParseX86Triple(TT);
145134 if (!FS.empty()) {
146135 if (!ArchFS.empty())
158147 ArchFS = "+64bit-mode";
159148
160149 MCSubtargetInfo *X = new MCSubtargetInfo();
161 InitX86MCSubtargetInfo(X, CPU, ArchFS);
150 InitX86MCSubtargetInfo(X, CPUName, ArchFS);
151 return X;
152 }
153
154 MCInstrInfo *createX86MCInstrInfo() {
155 MCInstrInfo *X = new MCInstrInfo();
156 InitX86MCInstrInfo(X);
157 return X;
158 }
159
160 MCRegisterInfo *createX86MCRegisterInfo() {
161 MCRegisterInfo *X = new MCRegisterInfo();
162 InitX86MCRegisterInfo(X);
162163 return X;
163164 }
164165
178179 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
179180 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
180181 }
181
182 extern "C" void LLVMInitializeX86MCSubtargetInfo() {
183 RegisterMCSubtargetInfo X(TheX86_32Target);
184 RegisterMCSubtargetInfo Y(TheX86_64Target);
185
186 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
187 createX86MCSubtargetInfo);
188 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
189 createX86MCSubtargetInfo);
190 }
1616 #include
1717
1818 namespace llvm {
19 class MCSubtargetInfo;
1920 class Target;
2021 class StringRef;
2122
3031 unsigned *rEBX, unsigned *rECX, unsigned *rEDX);
3132
3233 void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model);
34
35 /// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
36 /// This is exposed so Asm parser, etc. do not need to go through
37 /// TargetRegistry.
38 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
39 StringRef FS);
3340 }
41
3442 } // End llvm namespace
43
3544
3645 // Defines symbolic names for X86 registers. This defines a mapping from
3746 // register name to register number.
437437 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
438438 def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
439439 def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
440 def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate;
441 def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate;
440 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
441 AssemblerPredicate<"!Mode64Bit">;
442 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
443 AssemblerPredicate<"Mode64Bit">;
442444 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
443445 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
444446 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
2020 #include "llvm/Target/TargetMachine.h"
2121 #include "llvm/ADT/SmallVector.h"
2222
23 #define GET_SUBTARGETINFO_CTOR
23 #define GET_SUBTARGETINFO_ENUM
2424 #define GET_SUBTARGETINFO_MC_DESC
2525 #define GET_SUBTARGETINFO_TARGET_DESC
26 #define GET_SUBTARGETINFO_CTOR
2627 #include "X86GenSubtargetInfo.inc"
2728
2829 using namespace llvm;
118118 X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
119119 const std::string &CPU,
120120 const std::string &FS, bool is64Bit)
121 : LLVMTargetMachine(T, TT),
121 : LLVMTargetMachine(T, TT, CPU, FS),
122122 Subtarget(TT, CPU, FS, StackAlignmentOverride),
123123 FrameLowering(*this, Subtarget),
124124 ELFWriterInfo(is64Bit, true) {
1313 #include "XCoreSubtarget.h"
1414 #include "XCore.h"
1515
16 #define GET_SUBTARGETINFO_CTOR
16 #define GET_SUBTARGETINFO_ENUM
1717 #define GET_SUBTARGETINFO_MC_DESC
1818 #define GET_SUBTARGETINFO_TARGET_DESC
19 #define GET_SUBTARGETINFO_CTOR
1920 #include "XCoreGenSubtargetInfo.inc"
2021
2122 using namespace llvm;
2222 XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT,
2323 const std::string &CPU,
2424 const std::string &FS)
25 : LLVMTargetMachine(T, TT),
25 : LLVMTargetMachine(T, TT, CPU, FS),
2626 Subtarget(TT, CPU, FS),
2727 DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
2828 "i16:16:32-i32:32:32-i64:32:32-n32"),
370370
371371 OwningPtr Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx,
372372 *Str.get(), *MAI));
373 OwningPtr TAP(TheTarget->createAsmParser(*Parser, *TM));
373 OwningPtr
374 TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, *Parser));
374375 if (!TAP) {
375376 errs() << ProgName
376377 << ": error: this target does not support assembly parsing.\n";
618618 Context, *Streamer,
619619 *_target->getMCAsmInfo()));
620620 OwningPtr
621 TAP(_target->getTarget().createAsmParser(*Parser.get(), *_target.get()));
621 TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(),
622 _target->getTargetCPU(),
623 _target->getTargetFeatureString(),
624 *Parser.get()));
622625 Parser->setTargetParser(*TAP);
623626 int Res = Parser->Run(false);
624627 if (Res)
18161816 Info.AsmParser->getValueAsString("AsmParserClassName");
18171817
18181818 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1819 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1820 << "Subtarget *Subtarget) const {\n";
1819 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
18211820 OS << " unsigned Features = 0;\n";
18221821 for (std::map::const_iterator
18231822 it = Info.SubtargetFeatures.begin(),
18241823 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
18251824 SubtargetFeatureInfo &SFI = *it->second;
1826 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1827 << ")\n";
1825
1826 OS << " if (";
1827 StringRef Conds = SFI.TheDef->getValueAsString("AssemblerCondString");
1828 std::pair Comma = Conds.split(',');
1829 bool First = true;
1830 do {
1831 if (!First)
1832 OS << " && ";
1833
1834 bool Neg = false;
1835 StringRef Cond = Comma.first;
1836 if (Cond[0] == '!') {
1837 Neg = true;
1838 Cond = Cond.substr(1);
1839 }
1840
1841 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
1842 if (Neg)
1843 OS << " == 0";
1844 else
1845 OS << " != 0";
1846 OS << ")";
1847
1848 if (Comma.second.empty())
1849 break;
1850
1851 First = false;
1852 Comma = Comma.second.split(',');
1853 } while (true);
1854
1855 OS << ")\n";
18281856 OS << " Features |= " << SFI.getEnumName() << ";\n";
18291857 }
18301858 OS << " return Features;\n";
21392167 OS << "#undef GET_ASSEMBLER_HEADER\n";
21402168 OS << " // This should be included into the middle of the declaration of\n";
21412169 OS << " // your subclasses implementation of TargetAsmParser.\n";
2142 OS << " unsigned ComputeAvailableFeatures(const " <<
2143 Target.getName() << "Subtarget *Subtarget) const;\n";
2170 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
21442171 OS << " enum MatchResultTy {\n";
21452172 OS << " Match_ConversionFail,\n";
21462173 OS << " Match_InvalidOperand,\n";
644644
645645 EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
646646
647 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
648 OS << "#undef GET_SUBTARGETINFO_ENUM\n";
649
650 OS << "namespace llvm {\n";
651 Enumeration(OS, "SubtargetFeature", true);
652 OS << "} // End llvm namespace \n";
653 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
654
647655 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
648656 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
649657
650658 OS << "namespace llvm {\n";
651 Enumeration(OS, "SubtargetFeature", true);
652 OS<<"\n";
653659 unsigned NumFeatures = FeatureKeyValues(OS);
654660 OS<<"\n";
655661 unsigned NumProcs = CPUKeyValues(OS);