llvm.org GIT mirror llvm / ebd4eec
R600/SI: Fix broken encoding of DS_WRITE_B32 The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused it to corrupt the encoding of that by clobbering the first operand with the second one. Undo that damage and only apply the SMRD logic to that. Fixes some derivates related piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188558 91177308-0d34-0410-b5e6-96231b3b80d8 Michel Danzer 7 years ago
6 changed file(s) with 25 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
1212
1313 namespace SIInstrFlags {
1414 enum {
15 MIMG = 1 << 3
15 MIMG = 1 << 3,
16 SMRD = 1 << 4
1617 };
1718 }
1819
133133 // LGKM may uses larger values
134134 if (TSFlags & SIInstrFlags::LGKM_CNT) {
135135
136 MachineOperand &Op = MI.getOperand(0);
137 if (!Op.isReg())
138 Op = MI.getOperand(1);
139 assert(Op.isReg() && "First LGKM operand must be a register!");
140
141 unsigned Reg = Op.getReg();
142 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
143 Result.Named.LGKM = Size > 4 ? 2 : 1;
136 if (TII->isSMRD(MI.getOpcode())) {
137
138 MachineOperand &Op = MI.getOperand(0);
139 assert(Op.isReg() && "First LGKM operand must be a register!");
140
141 unsigned Reg = Op.getReg();
142 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
143 Result.Named.LGKM = Size > 4 ? 2 : 1;
144
145 } else {
146 // DS
147 Result.Named.LGKM = 1;
148 }
144149
145150 } else {
146151 Result.Named.LGKM = 0;
1717 field bits<1> EXP_CNT = 0;
1818 field bits<1> LGKM_CNT = 0;
1919 field bits<1> MIMG = 0;
20 field bits<1> SMRD = 0;
2021
2122 let TSFlags{0} = VM_CNT;
2223 let TSFlags{1} = EXP_CNT;
2324 let TSFlags{2} = LGKM_CNT;
2425 let TSFlags{3} = MIMG;
26 let TSFlags{4} = SMRD;
2527 }
2628
2729 class Enc32 pattern> :
141143 let Inst{31-27} = 0x18; //encoding
142144
143145 let LGKM_CNT = 1;
146 let SMRD = 1;
144147 }
145148
146149 //===----------------------------------------------------------------------===//
228228 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
229229 }
230230
231 int SIInstrInfo::isSMRD(uint16_t Opcode) const {
232 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
233 }
234
231235 //===----------------------------------------------------------------------===//
232236 // Indirect addressing callbacks
233237 //===----------------------------------------------------------------------===//
4747
4848 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
4949 int isMIMG(uint16_t Opcode) const;
50 int isSMRD(uint16_t Opcode) const;
5051
5152 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
5253
1212 ; SI-CHECK-NEXT: .long 32768
1313
1414 ; EG-CHECK: LDS_WRITE
15 ; SI-CHECK: DS_WRITE_B32
15 ; SI-CHECK: DS_WRITE_B32 0
1616
1717 ; GROUP_BARRIER must be the last instruction in a clause
1818 ; EG-CHECK: GROUP_BARRIER
2020 ; SI-CHECK: S_BARRIER
2121
2222 ; EG-CHECK: LDS_READ_RET
23 ; SI-CHECK: DS_READ_B32
23 ; SI-CHECK: DS_READ_B32 {{VGPR[0-9]+}}, 0
2424
2525 define void @local_memory(i32 addrspace(1)* %out) {
2626 entry: