llvm.org GIT mirror llvm / eba564c
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to hang, and possibly SPEC/CINT2006/464_h264ref. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 8 years ago
6 changed file(s) with 7 addition(s) and 177 deletion(s). Raw diff Collapse all Expand all
4646 cl::desc("Check fp vmla / vmls hazard at isel time"),
4747 cl::init(true));
4848
49 static cl::opt
50 DisableARMIntABS("disable-arm-int-abs", cl::Hidden,
51 cl::desc("Enable / disable ARM integer abs transform"),
52 cl::init(false));
53
5449 //===--------------------------------------------------------------------===//
5550 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
5651 /// instructions for SelectionDAG operations.
255250 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
256251 ARMCC::CondCodes CCVal, SDValue CCR,
257252 SDValue InFlag);
258
259 // Select special operations if node forms integer ABS pattern
260 SDNode *SelectABSOp(SDNode *N);
261253
262254 SDNode *SelectConcatVector(SDNode *N);
263255
23022294 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
23032295 }
23042296
2305 /// Target-specific DAG combining for ISD::XOR.
2306 /// Target-independent combining lowers SELECT_CC nodes of the form
2307 /// select_cc setg[ge] X, 0, X, -X
2308 /// select_cc setgt X, -1, X, -X
2309 /// select_cc setl[te] X, 0, -X, X
2310 /// select_cc setlt X, 1, -X, X
2311 /// which represent Integer ABS into:
2312 /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2313 /// ARM instruction selection detects the latter and matches it to
2314 /// ARM::ABS or ARM::t2ABS machine node.
2315 SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2316 SDValue XORSrc0 = N->getOperand(0);
2317 SDValue XORSrc1 = N->getOperand(1);
2318 DebugLoc DL = N->getDebugLoc();
2319 EVT VT = N->getValueType(0);
2320
2321 if (DisableARMIntABS)
2322 return NULL;
2323
2324 if (Subtarget->isThumb1Only())
2325 return NULL;
2326
2327 if (XORSrc0.getOpcode() != ISD::ADD ||
2328 XORSrc1.getOpcode() != ISD::SRA)
2329 return NULL;
2330
2331 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2332 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2333 SDValue SRASrc0 = XORSrc1.getOperand(0);
2334 SDValue SRASrc1 = XORSrc1.getOperand(1);
2335 ConstantSDNode *SRAConstant = dyn_cast(SRASrc1);
2336 EVT XType = SRASrc0.getValueType();
2337 unsigned Size = XType.getSizeInBits() - 1;
2338
2339 if (ADDSrc1 == XORSrc1 &&
2340 ADDSrc0 == SRASrc0 &&
2341 XType.isInteger() &&
2342 SRAConstant != NULL &&
2343 Size == SRAConstant->getZExtValue()) {
2344
2345 unsigned Opcode = ARM::ABS;
2346 if (Subtarget->isThumb2())
2347 Opcode = ARM::t2ABS;
2348
2349 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2350 }
2351
2352 return NULL;
2353 }
2354
23552297 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
23562298 // The only time a CONCAT_VECTORS operation can have legal types is when
23572299 // two 64-bit vectors are concatenated to a 128-bit vector.
23882330
23892331 switch (N->getOpcode()) {
23902332 default: break;
2391 case ISD::XOR: {
2392 // Select special operations if XOR node forms integer ABS pattern
2393 SDNode *ResNode = SelectABSOp(N);
2394 if (ResNode)
2395 return ResNode;
2396 // Other cases are autogenerated.
2397 break;
2398 }
23992333 case ISD::Constant: {
24002334 unsigned Val = cast(N)->getZExtValue();
24012335 bool UseCP = true;
61806180 MI->eraseFromParent(); // The pseudo instruction is gone now.
61816181 return BB;
61826182 }
6183
6184 case ARM::ABS:
6185 case ARM::t2ABS: {
6186 // To insert an ABS instruction, we have to insert the
6187 // diamond control-flow pattern. The incoming instruction knows the
6188 // source vreg to test against 0, the destination vreg to set,
6189 // the condition code register to branch on, the
6190 // true/false values to select between, and a branch opcode to use.
6191 // It transforms
6192 // V1 = ABS V0
6193 // into
6194 // V2 = MOVS V0
6195 // BCC (branch to SinkBB if V0 >= 0)
6196 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
6197 // SinkBB: V1 = PHI(V2, V3)
6198 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6199 MachineFunction::iterator BBI = BB;
6200 ++BBI;
6201 MachineFunction *Fn = BB->getParent();
6202 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6203 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6204 Fn->insert(BBI, RSBBB);
6205 Fn->insert(BBI, SinkBB);
6206
6207 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
6208 unsigned int ABSDstReg = MI->getOperand(0).getReg();
6209 bool isThumb2 = Subtarget->isThumb2();
6210 MachineRegisterInfo &MRI = Fn->getRegInfo();
6211 // In Thumb mode S must not be specified if source register is the SP or
6212 // PC and if destination register is the SP, so restrict register class
6213 unsigned NewMovDstReg = MRI.createVirtualRegister(
6214 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6215 unsigned NewRsbDstReg = MRI.createVirtualRegister(
6216 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6217
6218 // Transfer the remainder of BB and its successor edges to sinkMBB.
6219 SinkBB->splice(SinkBB->begin(), BB,
6220 llvm::next(MachineBasicBlock::iterator(MI)),
6221 BB->end());
6222 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
6223
6224 BB->addSuccessor(RSBBB);
6225 BB->addSuccessor(SinkBB);
6226
6227 // fall through to SinkMBB
6228 RSBBB->addSuccessor(SinkBB);
6229
6230 // insert a movs at the end of BB
6231 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr),
6232 NewMovDstReg)
6233 .addReg(ABSSrcReg, RegState::Kill)
6234 .addImm((unsigned)ARMCC::AL).addReg(0)
6235 .addReg(ARM::CPSR, RegState::Define);
6236
6237 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
6238 BuildMI(BB, dl,
6239 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
6240 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
6241
6242 // insert rsbri in RSBBB
6243 // Note: BCC and rsbri will be converted into predicated rsbmi
6244 // by if-conversion pass
6245 BuildMI(*RSBBB, RSBBB->begin(), dl,
6246 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
6247 .addReg(NewMovDstReg, RegState::Kill)
6248 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
6249
6250 // insert PHI in SinkBB,
6251 // reuse ABSDstReg to not change uses of ABS instruction
6252 BuildMI(*SinkBB, SinkBB->begin(), dl,
6253 TII->get(ARM::PHI), ABSDstReg)
6254 .addReg(NewRsbDstReg).addMBB(RSBBB)
6255 .addReg(NewMovDstReg).addMBB(BB);
6256
6257 // remove ABS instruction
6258 MI->eraseFromParent();
6259
6260 // return last added BB
6261 return SinkBB;
6262 }
62636183 }
62646184 }
62656185
28472847 let Inst{15-12} = Rd;
28482848 }
28492849
2850 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2851 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2852
28532850 // A version for the smaller set of tail call registers.
28542851 let neverHasSideEffects = 1 in
28552852 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
40254022 bits<4> opt;
40264023 let Inst{31-4} = 0xf57ff06;
40274024 let Inst{3-0} = opt;
4028 }
4029
4030 // Pseudo isntruction that combines movs + predicated rsbmi
4031 // to implement integer ABS
4032 let usesCustomInserter = 1, Defs = [CPSR] in {
4033 def ABS : ARMPseudoInst<
4034 (outs GPR:$dst), (ins GPR:$src),
4035 8, NoItinerary, []>;
40364025 }
40374026
40384027 let usesCustomInserter = 1 in {
34323432 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
34333433 imm:$cp))]>,
34343434 Requires<[IsThumb2]>;
3435
3436 // Pseudo isntruction that combines movs + predicated rsbmi
3437 // to implement integer ABS
3438 let usesCustomInserter = 1, Defs = [CPSR] in {
3439 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3440 NoItinerary, []>, Requires<[IsThumb2]>;
3441 }
3442
34433435 //===----------------------------------------------------------------------===//
34443436 // Coprocessor load/store -- for disassembly only
34453437 //
0 ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
11
22 ;; Integer absolute value, should produce something as good as: ARM:
3 ;; movs r0, r0
4 ;; rsbmi r0, r0, #0
3 ;; add r3, r0, r0, asr #31
4 ;; eor r0, r3, r0, asr #31
55 ;; bx lr
66
77 define i32 @test(i32 %a) {
99 %b = icmp sgt i32 %a, -1
1010 %abs = select i1 %b, i32 %a, i32 %tmp1neg
1111 ret i32 %abs
12 ; CHECK: movs r0, r0
13 ; CHECK: rsbmi r0, r0, #0
12 ; CHECK: add r1, r0, r0, asr #31
13 ; CHECK: eor r0, r1, r0, asr #31
1414 ; CHECK: bx lr
1515 }
22
33 ;; Integer absolute value, should produce something as good as:
44 ;; Thumb:
5 ;; movs r0, r0
6 ;; bpl
7 ;; rsb r0, r0, #0 (with opitmization, bpl + rsb is if-converted into rsbmi)
5 ;; asr r2, r0, #31
6 ;; add r0, r0, r2
7 ;; eor r0, r2
88 ;; bx lr
99
1010 define i32 @test(i32 %a) {
1212 %b = icmp sgt i32 %a, -1
1313 %abs = select i1 %b, i32 %a, i32 %tmp1neg
1414 ret i32 %abs
15 ; CHECK: movs r0, r0
16 ; CHECK: bpl
17 ; CHECK: rsb r0, r0, #0
18 ; CHECK: bx lr
1915 }
2016
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