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[ARM] Correct SP/PC handling in t2MOVr PC isn't allowed in the source operand of t2MOVr, so change the register class to one without PC. SP handling is slightly trickier and changes depending on if we're in ARMv8, so do that in checkTargetMatchPredicate. Differential Revision: https://reviews.llvm.org/D30199 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295732 91177308-0d34-0410-b5e6-96231b3b80d8 John Brawn 3 years ago
2 changed file(s) with 20 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
18271827 //
18281828
18291829 let hasSideEffects = 0 in
1830 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1830 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr,
18311831 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
18321832 let Inst{31-27} = 0b11101;
18331833 let Inst{26-25} = 0b01;
18361836 let Inst{14-12} = 0b000;
18371837 let Inst{7-4} = 0b0000;
18381838 }
1839 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1839 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
18401840 pred:$p, zero_reg)>;
1841 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1841 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
18421842 pred:$p, CPSR)>;
1843 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1843 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
18441844 pred:$p, CPSR)>;
18451845
18461846 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
89318931 return Match_RequiresV6;
89328932 }
89338933
8934 // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex
8935 // than the loop below can handle, so it uses the GPRnopc register class and
8936 // we do SP handling here.
8937 if (Opc == ARM::t2MOVr && !hasV8Ops())
8938 {
8939 // SP as both source and destination is not allowed
8940 if (Inst.getOperand(0).getReg() == ARM::SP &&
8941 Inst.getOperand(1).getReg() == ARM::SP)
8942 return Match_RequiresV8;
8943 // When flags-setting SP as either source or destination is not allowed
8944 if (Inst.getOperand(4).getReg() == ARM::CPSR &&
8945 (Inst.getOperand(0).getReg() == ARM::SP ||
8946 Inst.getOperand(1).getReg() == ARM::SP))
8947 return Match_RequiresV8;
8948 }
8949
89348950 for (unsigned I = 0; I < MCID.NumOperands; ++I)
89358951 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
89368952 // rGPRRegClass excludes PC, and also excluded SP before ARMv8