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[llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI It makes more sense to print out the number of micro opcodes that are issued every cycle rather than the number of instructions issued per cycle. This behavior is also consistent with the dispatch-stats: numbers from the two views can now be easily compared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357919 91177308-0d34-0410-b5e6-96231b3b80d8 Andrea Di Biagio 6 months ago
13 changed file(s) with 44 addition(s) and 46 deletion(s). Raw diff Collapse all Expand all
497497 2, 314 (51.5%)
498498
499499
500 Schedulers - number of cycles where we saw N instructions issued:
500 Schedulers - number of cycles where we saw N micro opcodes issued:
501501 [# issued], [# cycles]
502502 0, 7 (1.1%)
503503 1, 306 (50.2%)
551551 ``-all-stats`` or ``-dispatch-stats``.
552552
553553 The next table, *Schedulers*, presents a histogram displaying a count,
554 representing the number of instructions issued on some number of cycles. In
555 this case, of the 610 simulated cycles, single instructions were issued 306
556 times (50.2%) and there were 7 cycles where no instructions were issued.
554 representing the number of micro opcodes issued on some number of cycles. In
555 this case, of the 610 simulated cycles, single opcodes were issued 306 times
556 (50.2%) and there were 7 cycles where no opcodes were issued.
557557
558558 The *Scheduler's queue usage* table shows that the average and maximum number of
559559 buffer entries (i.e., scheduler queue entries) used at runtime. Resource JFPU01
2424 # M4-NEXT: IPC: 0.50
2525 # M4-NEXT: Block RThroughput: 0.2
2626
27 # ALL: Schedulers - number of cycles where we saw N instructions issued:
27 # ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
2828 # ALL-NEXT: [# issued], [# cycles]
2929 # ALL-NEXT: 0, 1 (50.0%)
3030 # ALL-NEXT: 1, 1 (50.0%)
8989 # CHECK-NEXT: 2, 172 (83.1%)
9090 # CHECK-NEXT: 4, 14 (6.8%)
9191
92 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
92 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
9393 # CHECK-NEXT: [# issued], [# cycles]
9494 # CHECK-NEXT: 0, 7 (3.4%)
9595 # CHECK-NEXT: 2, 200 (96.6%)
202202 # CHECK-NEXT: 2, 172 (83.1%)
203203 # CHECK-NEXT: 4, 14 (6.8%)
204204
205 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
205 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
206206 # CHECK-NEXT: [# issued], [# cycles]
207207 # CHECK-NEXT: 0, 7 (3.4%)
208208 # CHECK-NEXT: 2, 200 (96.6%)
315315 # CHECK-NEXT: 2, 172 (83.1%)
316316 # CHECK-NEXT: 4, 14 (6.8%)
317317
318 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
318 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
319319 # CHECK-NEXT: [# issued], [# cycles]
320320 # CHECK-NEXT: 0, 7 (3.4%)
321321 # CHECK-NEXT: 2, 200 (96.6%)
428428 # CHECK-NEXT: 2, 172 (83.1%)
429429 # CHECK-NEXT: 4, 14 (6.8%)
430430
431 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
431 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
432432 # CHECK-NEXT: [# issued], [# cycles]
433433 # CHECK-NEXT: 0, 7 (3.4%)
434434 # CHECK-NEXT: 2, 200 (96.6%)
541541 # CHECK-NEXT: 2, 172 (83.1%)
542542 # CHECK-NEXT: 4, 14 (6.8%)
543543
544 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
544 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
545545 # CHECK-NEXT: [# issued], [# cycles]
546546 # CHECK-NEXT: 0, 7 (3.4%)
547547 # CHECK-NEXT: 2, 200 (96.6%)
654654 # CHECK-NEXT: 2, 172 (83.1%)
655655 # CHECK-NEXT: 4, 14 (6.8%)
656656
657 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
657 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
658658 # CHECK-NEXT: [# issued], [# cycles]
659659 # CHECK-NEXT: 0, 7 (3.4%)
660660 # CHECK-NEXT: 2, 200 (96.6%)
766766 # CHECK-NEXT: 0, 7 (3.4%)
767767 # CHECK-NEXT: 4, 200 (96.6%)
768768
769 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
769 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
770770 # CHECK-NEXT: [# issued], [# cycles]
771771 # CHECK-NEXT: 0, 7 (3.4%)
772 # CHECK-NEXT: 2, 200 (96.6%)
772 # CHECK-NEXT: 4, 200 (96.6%)
773773
774774 # CHECK: Scheduler's queue usage:
775775 # CHECK-NEXT: [1] Resource name.
2525 # CHECK-NEXT: 1 10 1.00 * vmulps (%rsi), %xmm0, %xmm0
2626 # CHECK-NEXT: 1 1 0.50 addq %rsi, %rsi
2727
28 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
28 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
2929 # CHECK-NEXT: [# issued], [# cycles]
3030 # CHECK-NEXT: 0, 12 (92.3%)
3131 # CHECK-NEXT: 2, 1 (7.7%)
9090 # CHECK-NEXT: 2, 1 (0.2%)
9191 # CHECK-NEXT: 4, 7 (1.7%)
9292
93 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
93 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
9494 # CHECK-NEXT: [# issued], [# cycles]
9595 # CHECK-NEXT: 0, 3 (0.7%)
9696 # CHECK-NEXT: 1, 400 (99.3%)
204204 # CHECK-NEXT: 2, 1 (0.2%)
205205 # CHECK-NEXT: 4, 7 (1.7%)
206206
207 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
207 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
208208 # CHECK-NEXT: [# issued], [# cycles]
209209 # CHECK-NEXT: 0, 3 (0.7%)
210210 # CHECK-NEXT: 1, 400 (99.3%)
318318 # CHECK-NEXT: 2, 1 (0.2%)
319319 # CHECK-NEXT: 4, 7 (1.7%)
320320
321 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
321 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
322322 # CHECK-NEXT: [# issued], [# cycles]
323323 # CHECK-NEXT: 0, 3 (0.7%)
324324 # CHECK-NEXT: 1, 400 (99.3%)
432432 # CHECK-NEXT: 2, 1 (0.2%)
433433 # CHECK-NEXT: 4, 7 (1.7%)
434434
435 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
435 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
436436 # CHECK-NEXT: [# issued], [# cycles]
437437 # CHECK-NEXT: 0, 3 (0.7%)
438438 # CHECK-NEXT: 1, 400 (99.3%)
546546 # CHECK-NEXT: 2, 1 (0.1%)
547547 # CHECK-NEXT: 4, 6 (0.7%)
548548
549 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
549 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
550550 # CHECK-NEXT: [# issued], [# cycles]
551551 # CHECK-NEXT: 0, 403 (50.2%)
552552 # CHECK-NEXT: 1, 400 (49.8%)
661661 # CHECK-NEXT: 2, 1 (0.2%)
662662 # CHECK-NEXT: 4, 7 (1.7%)
663663
664 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
664 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
665665 # CHECK-NEXT: [# issued], [# cycles]
666666 # CHECK-NEXT: 0, 3 (0.7%)
667667 # CHECK-NEXT: 1, 400 (99.3%)
773773 # CHECK-NEXT: 0, 3 (0.7%)
774774 # CHECK-NEXT: 4, 400 (99.3%)
775775
776 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
776 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
777777 # CHECK-NEXT: [# issued], [# cycles]
778778 # CHECK-NEXT: 0, 3 (0.7%)
779 # CHECK-NEXT: 1, 400 (99.3%)
779 # CHECK-NEXT: 4, 400 (99.3%)
780780
781781 # CHECK: Scheduler's queue usage:
782782 # CHECK-NEXT: [1] Resource name.
2525 # CHECK-NEXT: 1 7 1.00 * vmulps (%rsi), %xmm0, %xmm0
2626 # CHECK-NEXT: 1 1 0.50 addq %rsi, %rsi
2727
28 # CHECK: Schedulers - number of cycles where we saw N instructions issued:
28 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
2929 # CHECK-NEXT: [# issued], [# cycles]
3030 # CHECK-NEXT: 0, 9 (90.0%)
3131 # CHECK-NEXT: 2, 1 (10.0%)
4040 # FULLREPORT-NEXT: 1, 62 (60.2%)
4141 # FULLREPORT-NEXT: 2, 19 (18.4%)
4242
43 # FULLREPORT: Schedulers - number of cycles where we saw N instructions issued:
43 # FULLREPORT: Schedulers - number of cycles where we saw N micro opcodes issued:
4444 # FULLREPORT-NEXT: [# issued], [# cycles]
4545 # FULLREPORT-NEXT: 0, 3 (2.9%)
4646 # FULLREPORT-NEXT: 1, 100 (97.1%)
4141 # FULL-NEXT: 1, 62 (60.2%)
4242 # FULL-NEXT: 2, 19 (18.4%)
4343
44 # ALL: Schedulers - number of cycles where we saw N instructions issued:
44 # ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
4545 # ALL-NEXT: [# issued], [# cycles]
4646 # ALL-NEXT: 0, 3 (2.9%)
4747 # ALL-NEXT: 1, 100 (97.1%)
4242 # FULLREPORT-NEXT: 1, 62 (60.2%)
4343 # FULLREPORT-NEXT: 2, 19 (18.4%)
4444
45 # FULLREPORT: Schedulers - number of cycles where we saw N instructions issued:
45 # FULLREPORT: Schedulers - number of cycles where we saw N micro opcodes issued:
4646 # FULLREPORT-NEXT: [# issued], [# cycles]
4747 # FULLREPORT-NEXT: 0, 3 (2.9%)
4848 # FULLREPORT-NEXT: 1, 100 (97.1%)
4141 # ALL-NEXT: 1, 62 (60.2%)
4242 # ALL-NEXT: 2, 19 (18.4%)
4343
44 # ALL: Schedulers - number of cycles where we saw N instructions issued:
44 # ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
4545 # ALL-NEXT: [# issued], [# cycles]
4646 # ALL-NEXT: 0, 3 (2.9%)
4747 # ALL-NEXT: 1, 100 (97.1%)
1212
1313 xor %eax, %ebx
1414
15 # ALL: Schedulers - number of cycles where we saw N instructions issued:
15 # ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
1616 # ALL-NEXT: [# issued], [# cycles]
1717 # ALL-NEXT: 0, 3 (75.0%)
1818 # ALL-NEXT: 1, 1 (25.0%)
2121 : SM(STI.getSchedModel()), LQResourceID(0), SQResourceID(0), NumIssued(0),
2222 NumCycles(0), MostRecentLoadDispatched(~0U),
2323 MostRecentStoreDispatched(~0U),
24 IssuedPerCycle(STI.getSchedModel().NumProcResourceKinds, 0),
2524 Usage(STI.getSchedModel().NumProcResourceKinds, {0, 0, 0}) {
2625 if (SM.hasExtraProcessorInfo()) {
2726 const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
4241 // In future we should add a new "memory queue" event type, so that we stop
4342 // making assumptions on how LSUnit internally works (See PR39828).
4443 void SchedulerStatistics::onEvent(const HWInstructionEvent &Event) {
45 if (Event.Type == HWInstructionEvent::Issued)
46 ++NumIssued;
47 else if (Event.Type == HWInstructionEvent::Dispatched) {
44 if (Event.Type == HWInstructionEvent::Issued) {
45 const Instruction &Inst = *Event.IR.getInstruction();
46 NumIssued += Inst.getDesc().NumMicroOps;
47 } else if (Event.Type == HWInstructionEvent::Dispatched) {
4848 const Instruction &Inst = *Event.IR.getInstruction();
4949 const unsigned Index = Event.IR.getSourceIndex();
5050 if (LQResourceID && Inst.getDesc().MayLoad &&
9494 BU.MaxUsedSlots = std::max(BU.MaxUsedSlots, BU.SlotsInUse);
9595 }
9696
97 IssuedPerCycle[NumIssued]++;
97 IssueWidthPerCycle[NumIssued]++;
9898 NumIssued = 0;
9999 }
100100
101101 void SchedulerStatistics::printSchedulerStats(raw_ostream &OS) const {
102102 OS << "\n\nSchedulers - "
103 << "number of cycles where we saw N instructions issued:\n";
103 << "number of cycles where we saw N micro opcodes issued:\n";
104104 OS << "[# issued], [# cycles]\n";
105105
106 bool HasColors = OS.has_colors();
106107 const auto It =
107 std::max_element(IssuedPerCycle.begin(), IssuedPerCycle.end());
108 unsigned Index = std::distance(IssuedPerCycle.begin(), It);
109
110 bool HasColors = OS.has_colors();
111 for (unsigned I = 0, E = IssuedPerCycle.size(); I < E; ++I) {
112 unsigned IPC = IssuedPerCycle[I];
113 if (!IPC)
114 continue;
115
116 if (I == Index && HasColors)
108 std::max_element(IssueWidthPerCycle.begin(), IssueWidthPerCycle.end());
109 for (const std::pair &Entry : IssueWidthPerCycle) {
110 unsigned NumIssued = Entry.first;
111 if (NumIssued == It->first && HasColors)
117112 OS.changeColor(raw_ostream::SAVEDCOLOR, true, false);
118113
119 OS << " " << I << ", " << IPC << " ("
114 unsigned IPC = Entry.second;
115 OS << " " << NumIssued << ", " << IPC << " ("
120116 << format("%.1f", ((double)IPC / NumCycles) * 100) << "%)\n";
121117 if (HasColors)
122118 OS.resetColor();
6161 uint64_t CumulativeNumUsedSlots;
6262 };
6363
64 std::vector IssuedPerCycle;
64 using Histogram = std::map;
65 Histogram IssueWidthPerCycle;
66
6567 std::vector Usage;
6668
6769 void updateHistograms();