llvm.org GIT mirror llvm / eae1d34
Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 7 years ago
6 changed file(s) with 131 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
37093709 if (fieldFromInstruction(Insn, 6, 1))
37103710 return MCDisassembler::Fail; // UNDEFINED
37113711 index = fieldFromInstruction(Insn, 7, 1);
3712 if (fieldFromInstruction(Insn, 4, 2) != 0)
3713 align = 4;
3712
3713 switch (fieldFromInstruction(Insn, 4, 2)) {
3714 case 0 :
3715 align = 0; break;
3716 case 3:
3717 align = 4; break;
3718 default:
3719 return MCDisassembler::Fail;
3720 }
3721 break;
37143722 }
37153723
37163724 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
37683776 if (fieldFromInstruction(Insn, 6, 1))
37693777 return MCDisassembler::Fail; // UNDEFINED
37703778 index = fieldFromInstruction(Insn, 7, 1);
3771 if (fieldFromInstruction(Insn, 4, 2) != 0)
3772 align = 4;
3779
3780 switch (fieldFromInstruction(Insn, 4, 2)) {
3781 case 0:
3782 align = 0; break;
3783 case 3:
3784 align = 4; break;
3785 default:
3786 return MCDisassembler::Fail;
3787 }
3788 break;
37733789 }
37743790
37753791 if (Rm != 0xF) { // Writeback
40894105 inc = 2;
40904106 break;
40914107 case 2:
4092 if (fieldFromInstruction(Insn, 4, 2))
4093 align = 4 << fieldFromInstruction(Insn, 4, 2);
4108 switch (fieldFromInstruction(Insn, 4, 2)) {
4109 case 0:
4110 align = 0; break;
4111 case 3:
4112 return MCDisassembler::Fail;
4113 default:
4114 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4115 }
4116
40944117 index = fieldFromInstruction(Insn, 7, 1);
40954118 if (fieldFromInstruction(Insn, 6, 1))
40964119 inc = 2;
41634186 inc = 2;
41644187 break;
41654188 case 2:
4166 if (fieldFromInstruction(Insn, 4, 2))
4167 align = 4 << fieldFromInstruction(Insn, 4, 2);
4189 switch (fieldFromInstruction(Insn, 4, 2)) {
4190 case 0:
4191 align = 0; break;
4192 case 3:
4193 return MCDisassembler::Fail;
4194 default:
4195 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4196 }
4197
41684198 index = fieldFromInstruction(Insn, 7, 1);
41694199 if (fieldFromInstruction(Insn, 6, 1))
41704200 inc = 2;
0 # RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
1
2 0xa0 0xf9 0x10 0x08
3 # CHECK: invalid instruction encoding
0 # RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
1
2 0xa0 0xf9 0x30 0x0b
3 # CHECK: invalid instruction encoding
0 # RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
1
2 0x80 0xf9 0x10 0x08
3 # CHECK: invalid instruction encoding
0 # RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
1
2 0x80 0xf9 0x30 0x0b
3 # CHECK: invalid instruction encoding
0 # RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s | FileCheck %s
1
2 0xa0 0xf9 0x00 0x00
3 0xa0 0xf9 0x20 0x00
4 0xa0 0xf9 0x40 0x00
5 0xa0 0xf9 0x60 0x00
6 0xa0 0xf9 0x80 0x00
7 0xa0 0xf9 0xa0 0x00
8 0xa0 0xf9 0xc0 0x00
9 0xa0 0xf9 0xe0 0x00
10
11 # CHECK: vld1.8 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x00]
12 # CHECK: vld1.8 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x00]
13 # CHECK: vld1.8 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x00]
14 # CHECK: vld1.8 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0x60,0x00]
15 # CHECK: vld1.8 {d0[4]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x00]
16 # CHECK: vld1.8 {d0[5]}, [r0], r0 @ encoding: [0xa0,0xf9,0xa0,0x00]
17 # CHECK: vld1.8 {d0[6]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x00]
18 # CHECK: vld1.8 {d0[7]}, [r0], r0 @ encoding: [0xa0,0xf9,0xe0,0x00]
19
20 0xa0 0xf9 0x00 0x04
21 0xa0 0xf9 0x10 0x04
22 0xa0 0xf9 0x40 0x04
23 0xa0 0xf9 0x50 0x04
24 0xa0 0xf9 0x80 0x04
25 0xa0 0xf9 0x90 0x04
26 0xa0 0xf9 0xc0 0x04
27 0xa0 0xf9 0xd0 0x04
28
29 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
30 # CHECK: vld1.16 {d0[0]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
31 # CHECK: vld1.16 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x04]
32 # CHECK: vld1.16 {d0[1]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x50,0x04]
33 # CHECK: vld1.16 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x04]
34 # CHECK: vld1.16 {d0[2]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x90,0x04]
35 # CHECK: vld1.16 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x04]
36 # CHECK: vld1.16 {d0[3]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0xd0,0x04]
37
38 0xa0 0xf9 0x00 0x08
39 0xa0 0xf9 0x30 0x08
40 0xa0 0xf9 0x80 0x08
41 0xa0 0xf9 0xb0 0x08
42
43 # CHECK: vld1.32 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x08]
44 # CHECK: vld1.32 {d0[0]}, [r0, :32], r0 @ encoding: [0xa0,0xf9,0x30,0x08]
45 # CHECK: vld1.32 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x08]
46 # CHECK: vld1.32 {d0[1]}, [r0, :32], r0 @ encoding: [0xa0,0xf9,0xb0,0x08]
47
48 0xa0 0xf9 0x1f 0x04
49 0xa0 0xf9 0x8f 0x00
50
51 # CHECK: vld1.16 {d0[0]}, [r0, :16] @ encoding: [0xa0,0xf9,0x1f,0x04]
52 # CHECK: vld1.8 {d0[4]}, [r0] @ encoding: [0xa0,0xf9,0x8f,0x00]
53
54 0xa0 0xf9 0x1d 0x04
55 0xa0 0xf9 0x8d 0x00
56
57 # CHECK: vld1.16 {d0[0]}, [r0, :16]! @ encoding: [0xa0,0xf9,0x1d,0x04]
58 # CHECK: vld1.8 {d0[4]}, [r0]! @ encoding: [0xa0,0xf9,0x8d,0x00]
59
60 0xa5 0xf9 0x10 0x04
61 0xa5 0xf9 0x1a 0x04
62 0xae 0xf9 0x1a 0x04
63 0xa5 0xf9 0x1a 0x94
64
65 # CHECK: vld1.16 {d0[0]}, [r5, :16], r0 @ encoding: [0xa5,0xf9,0x10,0x04]
66 # CHECK: vld1.16 {d0[0]}, [r5, :16], r10 @ encoding: [0xa5,0xf9,0x1a,0x04]
67 # CHECK: vld1.16 {d0[0]}, [lr, :16], r10 @ encoding: [0xae,0xf9,0x1a,0x04]
68 # CHECK: vld1.16 {d9[0]}, [r5, :16], r10 @ encoding: [0xa5,0xf9,0x1a,0x94]
69
70 0xa0 0xf9 0x20 0x0b
71 0xa0 0xf9 0x20 0x07
72 0xa0 0xf9 0x20 0x03
73
74 # CHECK: vld4.32 {d0[0], d1[0], d2[0], d3[0]}, [r0, :128], r0 @ encoding: [0xa0,0xf9,0x20,0x0b]
75 # CHECK: vld4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x07]
76 # CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x03]