llvm.org GIT mirror llvm / ead7590
Add option to turn on register scavenger; By default, spills kills the register being stored. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34514 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
2 changed file(s) with 20 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
3030 #include "llvm/ADT/BitVector.h"
3131 #include "llvm/ADT/SmallVector.h"
3232 #include "llvm/ADT/STLExtras.h"
33 #include "llvm/Support/CommandLine.h"
3334 #include
3435 using namespace llvm;
36
37 static cl::opt EnableScavenging("enable-arm-reg-scavenging", cl::Hidden,
38 cl::desc("Enable register scavenging on ARM"));
3539
3640 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
3741 using namespace ARM;
9094 return false;
9195
9296 MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
93 for (unsigned i = CSI.size(); i != 0; --i)
94 MIB.addReg(CSI[i-1].getReg());
97 for (unsigned i = CSI.size(); i != 0; --i) {
98 unsigned Reg = CSI[i-1].getReg();
99 // Add the callee-saved register as live-in. It's killed at the spill.
100 MBB.addLiveIn(Reg);
101 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
102 }
95103 return true;
96104 }
97105
129137 MachineFunction &MF = *MBB.getParent();
130138 ARMFunctionInfo *AFI = MF.getInfo();
131139 if (AFI->isThumbFunction())
132 BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg)
140 BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true)
133141 .addFrameIndex(FI).addImm(0);
134142 else
135 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg)
143 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
136144 .addFrameIndex(FI).addReg(0).addImm(0);
137145 } else if (RC == ARM::DPRRegisterClass) {
138 BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg)
146 BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
139147 .addFrameIndex(FI).addImm(0);
140148 } else {
141149 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
142 BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg)
150 BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
143151 .addFrameIndex(FI).addImm(0);
144152 }
145153 }
317325 ///
318326 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
319327 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
328 }
329
330 bool ARMRegisterInfo::requiresRegisterScavenging() const {
331 return EnableScavenging;
320332 }
321333
322334 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
6868
6969 BitVector getReservedRegs(const MachineFunction &MF) const;
7070
71 bool requiresRegisterScavenging() const;
72
7173 bool hasFP(const MachineFunction &MF) const;
7274
7375 void eliminateCallFramePseudoInstr(MachineFunction &MF,