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[AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instructions s_set_gpr_idx_on and s_set_gpr_idx_mode See bug 39331: https://bugs.llvm.org/show_bug.cgi?id=39331 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D58288 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354969 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitry Preobrazhensky 1 year, 7 months ago
15 changed file(s) with 261 addition(s) and 70 deletion(s). Raw diff Collapse all Expand all
172172 ImmTyNegLo,
173173 ImmTyNegHi,
174174 ImmTySwizzle,
175 ImmTyGprIdxMode,
175176 ImmTyHigh
176177 };
177178
693694 case ImmTyNegLo: OS << "NegLo"; break;
694695 case ImmTyNegHi: OS << "NegHi"; break;
695696 case ImmTySwizzle: OS << "Swizzle"; break;
697 case ImmTyGprIdxMode: OS << "GprIdxMode"; break;
696698 case ImmTyHigh: OS << "High"; break;
697699 }
698700 }
11271129 bool parseSwizzleBroadcast(int64_t &Imm);
11281130 bool parseSwizzleSwap(int64_t &Imm);
11291131 bool parseSwizzleReverse(int64_t &Imm);
1132
1133 OperandMatchResultTy parseGPRIdxMode(OperandVector &Operands);
1134 int64_t parseGPRIdxMacro();
11301135
11311136 void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); }
11321137 void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); }
46484653 }
46494654
46504655 //===----------------------------------------------------------------------===//
4656 // VGPR Index Mode
4657 //===----------------------------------------------------------------------===//
4658
4659 int64_t AMDGPUAsmParser::parseGPRIdxMacro() {
4660
4661 using namespace llvm::AMDGPU::VGPRIndexMode;
4662
4663 if (trySkipToken(AsmToken::RParen)) {
4664 return OFF;
4665 }
4666
4667 int64_t Imm = 0;
4668
4669 while (true) {
4670 unsigned Mode = 0;
4671 SMLoc S = Parser.getTok().getLoc();
4672
4673 for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
4674 if (trySkipId(IdSymbolic[ModeId])) {
4675 Mode = 1 << ModeId;
4676 break;
4677 }
4678 }
4679
4680 if (Mode == 0) {
4681 Error(S, (Imm == 0)?
4682 "expected a VGPR index mode or a closing parenthesis" :
4683 "expected a VGPR index mode");
4684 break;
4685 }
4686
4687 if (Imm & Mode) {
4688 Error(S, "duplicate VGPR index mode");
4689 break;
4690 }
4691 Imm |= Mode;
4692
4693 if (trySkipToken(AsmToken::RParen))
4694 break;
4695 if (!skipToken(AsmToken::Comma,
4696 "expected a comma or a closing parenthesis"))
4697 break;
4698 }
4699
4700 return Imm;
4701 }
4702
4703 OperandMatchResultTy
4704 AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {
4705
4706 int64_t Imm = 0;
4707 SMLoc S = Parser.getTok().getLoc();
4708
4709 if (getLexer().getKind() == AsmToken::Identifier &&
4710 Parser.getTok().getString() == "gpr_idx" &&
4711 getLexer().peekTok().is(AsmToken::LParen)) {
4712
4713 Parser.Lex();
4714 Parser.Lex();
4715
4716 // If parse failed, trigger an error but do not return error code
4717 // to avoid excessive error messages.
4718 Imm = parseGPRIdxMacro();
4719
4720 } else {
4721 if (getParser().parseAbsoluteExpression(Imm))
4722 return MatchOperand_NoMatch;
4723 if (Imm < 0 || !isUInt<4>(Imm)) {
4724 Error(S, "invalid immediate: only 4-bit values are legal");
4725 }
4726 }
4727
4728 Operands.push_back(
4729 AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyGprIdxMode));
4730 return MatchOperand_Success;
4731 }
4732
4733 bool AMDGPUOperand::isGPRIdxMode() const {
4734 return isImmTy(ImmTyGprIdxMode);
4735 }
4736
4737 //===----------------------------------------------------------------------===//
46514738 // sopp branch targets
46524739 //===----------------------------------------------------------------------===//
46534740
52865373 (Imm == DppCtrl::BCAST31);
52875374 }
52885375 return false;
5289 }
5290
5291 bool AMDGPUOperand::isGPRIdxMode() const {
5292 return isImm() && isUInt<4>(getImm());
52935376 }
52945377
52955378 bool AMDGPUOperand::isS16Imm() const {
933933 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
934934 const MCSubtargetInfo &STI,
935935 raw_ostream &O) {
936 using namespace llvm::AMDGPU::VGPRIndexMode;
936937 unsigned Val = MI->getOperand(OpNo).getImm();
937 if (Val == 0) {
938 O << " 0";
939 return;
940 }
941
942 if (Val & VGPRIndexMode::DST_ENABLE)
943 O << " dst";
944
945 if (Val & VGPRIndexMode::SRC0_ENABLE)
946 O << " src0";
947
948 if (Val & VGPRIndexMode::SRC1_ENABLE)
949 O << " src1";
950
951 if (Val & VGPRIndexMode::SRC2_ENABLE)
952 O << " src2";
938
939 if ((Val & ~ENABLE_MASK) != 0) {
940 O << " " << formatHex(static_cast(Val));
941 } else {
942 O << " gpr_idx(";
943 bool NeedComma = false;
944 for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
945 if (Val & (1 << ModeId)) {
946 if (NeedComma)
947 O << ',';
948 O << IdSymbolic[ModeId];
949 NeedComma = true;
950 }
951 }
952 O << ')';
953 }
953954 }
954955
955956 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
179179 };
180180 }
181181
182 namespace AMDGPU {
182183 namespace VGPRIndexMode {
183 enum {
184 SRC0_ENABLE = 1 << 0,
185 SRC1_ENABLE = 1 << 1,
186 SRC2_ENABLE = 1 << 2,
187 DST_ENABLE = 1 << 3
188 };
189 }
184
185 enum Id { // id of symbolic names
186 ID_SRC0 = 0,
187 ID_SRC1,
188 ID_SRC2,
189 ID_DST,
190
191 ID_MIN = ID_SRC0,
192 ID_MAX = ID_DST
193 };
194
195 enum EncBits {
196 OFF = 0,
197 SRC0_ENABLE = 1 << ID_SRC0,
198 SRC1_ENABLE = 1 << ID_SRC1,
199 SRC2_ENABLE = 1 << ID_SRC2,
200 DST_ENABLE = 1 << ID_DST,
201 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE
202 };
203
204 } // namespace VGPRIndexMode
205 } // namespace AMDGPU
190206
191207 namespace AMDGPUAsmVariants {
192208 enum {
29102910 .addImm(Offset);
29112911 }
29122912 unsigned IdxMode = IsIndirectSrc ?
2913 VGPRIndexMode::SRC0_ENABLE : VGPRIndexMode::DST_ENABLE;
2913 AMDGPU::VGPRIndexMode::SRC0_ENABLE : AMDGPU::VGPRIndexMode::DST_ENABLE;
29142914 MachineInstr *SetOn =
29152915 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
29162916 .addReg(IdxReg, RegState::Kill)
30413041
30423042 if (UseGPRIdxMode) {
30433043 unsigned IdxMode = IsIndirectSrc ?
3044 VGPRIndexMode::SRC0_ENABLE : VGPRIndexMode::DST_ENABLE;
3044 AMDGPU::VGPRIndexMode::SRC0_ENABLE : AMDGPU::VGPRIndexMode::DST_ENABLE;
30453045 if (Offset == 0) {
30463046 MachineInstr *SetOn =
30473047 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
88 def GPRIdxModeMatchClass : AsmOperandClass {
99 let Name = "GPRIdxMode";
1010 let PredicateMethod = "isGPRIdxMode";
11 let ParserMethod = "parseGPRIdxMode";
1112 let RenderMethod = "addImmOperands";
1213 }
1314
8484 };
8585
8686 } // namespace Swizzle
87
88 namespace VGPRIndexMode {
89
90 // This must be in sync with llvm::AMDGPU::VGPRIndexMode::Id enum members, see SIDefines.h.
91 const char* const IdSymbolic[] = {
92 "SRC0",
93 "SRC1",
94 "SRC2",
95 "DST",
96 };
97
98 } // namespace VGPRIndexMode
99
87100 } // namespace AMDGPU
88101 } // namespace llvm
2929 extern const char* const IdSymbolic[];
3030
3131 } // namespace Swizzle
32
33 namespace VGPRIndexMode { // Symbolic names for the gpr_idx(...) syntax.
34
35 extern const char* const IdSymbolic[];
36
37 } // namespace VGPRIndexMode
38
3239 } // namespace AMDGPU
3340 } // namespace llvm
3441
2323 ; MOVREL: s_mov_b32 m0, [[READLANE]]
2424 ; MOVREL-NEXT: v_movreld_b32_e32 v[[VEC_ELT0]], [[INS0]]
2525
26 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], dst
26 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(DST)
2727 ; IDXMODE-NEXT: v_mov_b32_e32 v[[VEC_ELT0]], [[INS0]]
2828 ; IDXMODE: s_set_gpr_idx_off
2929
4343 ; MOVREL: s_mov_b32 m0, [[READLANE]]
4444 ; MOVREL-NEXT: v_movreld_b32_e32 v{{[0-9]+}}, 63
4545
46 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], dst
46 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(DST)
4747 ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, 63
4848 ; IDXMODE: s_set_gpr_idx_off
4949
2626 ; MOVREL: s_mov_b32 m0, [[READLANE]]
2727 ; MOVREL-NEXT: v_movreld_b32_e32 v[[VEC_ELT0]], [[INS0]]
2828
29 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], dst
29 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(DST)
3030 ; IDXMODE-NEXT: v_mov_b32_e32 v[[VEC_ELT0]], [[INS0]]
3131 ; IDXMODE: s_set_gpr_idx_off
3232
4646 ; MOVREL: s_mov_b32 m0, [[READLANE]]
4747 ; MOVREL-NEXT: v_movreld_b32_e32 v{{[0-9]+}}, 63
4848
49 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], dst
49 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(DST)
5050 ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, 63
5151 ; IDXMODE: s_set_gpr_idx_off
5252
1616 ; MOVREL-DAG: s_mov_b32 m0, [[IN]]
1717 ; MOVREL: v_movrels_b32_e32 v{{[0-9]+}}, [[BASEREG]]
1818
19 ; IDXMODE: s_set_gpr_idx_on [[IN]], src0{{$}}
19 ; IDXMODE: s_set_gpr_idx_on [[IN]], gpr_idx(SRC0){{$}}
2020 ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, [[BASEREG]]
2121 ; IDXMODE-NEXT: s_set_gpr_idx_off
2222 define amdgpu_kernel void @extract_w_offset(float addrspace(1)* %out, i32 %in) {
4242
4343 ; MOVREL: v_movrels_b32_e32
4444
45 ; IDXMODE: s_set_gpr_idx_on s{{[0-9]+}}, src0{{$}}
45 ; IDXMODE: s_set_gpr_idx_on s{{[0-9]+}}, gpr_idx(SRC0){{$}}
4646 ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
4747 ; IDXMODE-NEXT: s_set_gpr_idx_off
4848 define amdgpu_kernel void @extract_w_offset_salu_use_vector(i32 addrspace(1)* %out, i32 %in, <16 x i32> %or.val) {
6464 ; MOVREL-DAG: s_mov_b32 m0, [[IN]]
6565 ; MOVREL: v_movrels_b32_e32 v{{[0-9]+}}, [[BASEREG]]
6666
67 ; IDXMODE: s_set_gpr_idx_on [[IN]], src0{{$}}
67 ; IDXMODE: s_set_gpr_idx_on [[IN]], gpr_idx(SRC0){{$}}
6868 ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, [[BASEREG]]
6969 ; IDXMODE-NEXT: s_set_gpr_idx_off
7070 define amdgpu_kernel void @extract_wo_offset(float addrspace(1)* %out, i32 %in) {
8282 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}}
8383 ; IDXMODE: v_mov_b32_e32 v14, 15
8484 ; IDXMODE: v_mov_b32_e32 v15, 16
85 ; IDXMODE-NEXT: s_set_gpr_idx_on [[ADD_IDX]], src0{{$}}
85 ; IDXMODE-NEXT: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(SRC0){{$}}
8686 ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
8787 ; IDXMODE-NEXT: s_set_gpr_idx_off
8888 define amdgpu_kernel void @extract_neg_offset_sgpr(i32 addrspace(1)* %out, i32 %offset) {
115115 ; IDXMODE: v_mov_b32_e32 v13,
116116 ; IDXMODE: v_mov_b32_e32 v14,
117117 ; IDXMODE: v_mov_b32_e32 v15,
118 ; IDXMODE-NEXT: s_set_gpr_idx_on [[ADD_IDX]], src0{{$}}
118 ; IDXMODE-NEXT: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(SRC0){{$}}
119119 ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
120120 ; IDXMODE-NEXT: s_set_gpr_idx_off
121121 define amdgpu_kernel void @extract_neg_offset_sgpr_loaded(i32 addrspace(1)* %out, <16 x i32> %vec0, <16 x i32> %vec1, i32 %offset) {
140140 ; MOVREL: v_movrels_b32_e32 [[RESULT:v[0-9]+]], v1
141141
142142 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00
143 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], src0
143 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(SRC0)
144144 ; IDXMODE: v_mov_b32_e32 [[RESULT:v[0-9]+]], v1
145145 ; IDXMODE: s_set_gpr_idx_off
146146
206206 ; MOVREL: s_mov_b32 m0, [[BASE]]
207207 ; MOVREL: v_movreld_b32_e32 [[ELT1]], v{{[0-9]+}}
208208
209 ; IDXMODE: s_set_gpr_idx_on [[BASE]], dst
209 ; IDXMODE: s_set_gpr_idx_on [[BASE]], gpr_idx(DST)
210210 ; IDXMODE-NEXT: v_mov_b32_e32 [[ELT1]], v{{[0-9]+}}
211211 ; IDXMODE-NEXT: s_set_gpr_idx_off
212212 define amdgpu_kernel void @insert_unsigned_base_plus_offset(<16 x float> addrspace(1)* %out, i16 %in) {
229229 ; MOVREL: s_mov_b32 m0, [[BASE_PLUS_OFFSET]]
230230 ; MOVREL: v_movreld_b32_e32 [[ELT0]], v{{[0-9]+}}
231231
232 ; IDXMODE: s_set_gpr_idx_on [[BASE_PLUS_OFFSET]], dst
232 ; IDXMODE: s_set_gpr_idx_on [[BASE_PLUS_OFFSET]], gpr_idx(DST)
233233 ; IDXMODE-NEXT: v_mov_b32_e32 [[ELT0]], v{{[0-9]+}}
234234 ; IDXMODE-NEXT: s_set_gpr_idx_off
235235 define amdgpu_kernel void @insert_signed_base_plus_offset(<16 x float> addrspace(1)* %out, i16 %in) {
248248 ; MOVREL: s_mov_b32 m0, [[IN]]
249249 ; MOVREL: v_movreld_b32_e32 v[[ELT0:[0-9]+]]
250250
251 ; IDXMODE: s_set_gpr_idx_on [[IN]], dst
251 ; IDXMODE: s_set_gpr_idx_on [[IN]], gpr_idx(DST)
252252 ; IDXMODE-NEXT: v_mov_b32_e32 v[[ELT0:[0-9]+]], v{{[0-9]+}}
253253 ; IDXMODE-NEXT: s_set_gpr_idx_off
254254
266266 ; MOVREL: v_movreld_b32_e32 v0, 16
267267
268268 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}}
269 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], dst
269 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(DST)
270270 ; IDXMODE-NEXT: v_mov_b32_e32 v0, 16
271271 ; IDXMODE-NEXT: s_set_gpr_idx_off
272272 define amdgpu_kernel void @insert_neg_offset_sgpr(i32 addrspace(1)* %in, <16 x i32> addrspace(1)* %out, i32 %offset) {
286286 ; MOVREL: v_movreld_b32_e32 v0, 5
287287
288288 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}}
289 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], dst
289 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(DST)
290290 ; IDXMODE-NEXT: v_mov_b32_e32 v0, 5
291291 ; IDXMODE-NEXT: s_set_gpr_idx_off
292292 define amdgpu_kernel void @insert_neg_offset_sgpr_loadreg(i32 addrspace(1)* %in, <16 x i32> addrspace(1)* %out, <16 x i32> %vec, i32 %offset) {
326326 ; MOVREL: v_movreld_b32_e32 [[VEC_ELT0]], 33
327327
328328 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}}
329 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], dst
329 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(DST)
330330 ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 33
331331 ; IDXMODE: s_set_gpr_idx_off
332332
372372 ; MOVREL: v_movreld_b32_e32 [[VEC_ELT0]], [[VAL]]
373373
374374 ; IDXMODE: s_add_i32 [[ADD_IDX:s[0-9]+]], [[READLANE]], -16
375 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], dst
375 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(DST)
376376 ; IDXMODE: v_mov_b32_e32 [[VEC_ELT0]], [[VAL]]
377377 ; IDXMODE: s_set_gpr_idx_off
378378
414414 ; MOVREL: s_mov_b32 m0, [[READLANE]]
415415 ; MOVREL: v_movrels_b32_e32 [[MOVREL0:v[0-9]+]], [[VEC_ELT0]]
416416
417 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], src0
417 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(SRC0)
418418 ; IDXMODE: v_mov_b32_e32 [[MOVREL0:v[0-9]+]], [[VEC_ELT0]]
419419 ; IDXMODE: s_set_gpr_idx_off
420420
436436 ; MOVREL: s_mov_b32 m0, [[READLANE]]
437437 ; MOVREL-NEXT: v_movrels_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT0_2]]
438438
439 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], src0
439 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(SRC0)
440440 ; IDXMODE-NEXT: v_mov_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT0_2]]
441441 ; IDXMODE: s_set_gpr_idx_off
442442
515515 ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 0x41900000
516516 ; IDXMODE: s_waitcnt
517517 ; IDXMODE: s_add_i32 [[ARG]], [[ARG]], -16
518 ; IDXMODE: s_set_gpr_idx_on [[ARG]], dst
518 ; IDXMODE: s_set_gpr_idx_on [[ARG]], gpr_idx(DST)
519519 ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 4.0
520520 ; IDXMODE: s_set_gpr_idx_off
521521 ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 0x41b0cccd
522 ; IDXMODE: s_set_gpr_idx_on [[ARG]], dst
522 ; IDXMODE: s_set_gpr_idx_on [[ARG]], gpr_idx(DST)
523523 ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, -4.0
524524 ; IDXMODE: s_set_gpr_idx_off
525525
550550 ; MOVREL: s_mov_b32 m0, [[IDX]]
551551 ; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
552552
553 ; IDXMODE: s_set_gpr_idx_on [[IDX]], src0
553 ; IDXMODE: s_set_gpr_idx_on [[IDX]], gpr_idx(SRC0)
554554 ; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
555555 ; IDXMODE: s_set_gpr_idx_off
556556
572572 ; MOVREL: s_mov_b32 m0, [[ADD_IDX]]
573573 ; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
574574
575 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], src0
575 ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(SRC0)
576576 ; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
577577 ; IDXMODE: s_set_gpr_idx_off
578578
594594 ; MOVREL: s_mov_b32 m0, [[IDX_FIN]]
595595 ; MOVREL: v_movrels_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
596596
597 ; IDXMODE: s_set_gpr_idx_on [[IDX_FIN]], src0
597 ; IDXMODE: s_set_gpr_idx_on [[IDX_FIN]], gpr_idx(SRC0)
598598 ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
599599 ; IDXMODE: s_set_gpr_idx_off
600600 define amdgpu_kernel void @extractelement_v16i32_or_index(i32 addrspace(1)* %out, <16 x i32> addrspace(1)* %in, i32 %idx.in) {
615615 ; MOVREL: s_mov_b32 m0, [[IDX_FIN]]
616616 ; MOVREL: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
617617
618 ; IDXMODE: s_set_gpr_idx_on [[IDX_FIN]], dst
618 ; IDXMODE: s_set_gpr_idx_on [[IDX_FIN]], gpr_idx(DST)
619619 ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
620620 ; IDXMODE: s_set_gpr_idx_off
621621 define amdgpu_kernel void @insertelement_v16f32_or_index(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %idx.in) nounwind {
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
11
22 s_set_gpr_idx_on s0, s1
3 // GCN: error: invalid operand for instruction
3 // VI: error: expected absolute expression
44
55 s_set_gpr_idx_on s0, 16
6 // GCN: error: invalid operand for instruction
6 // VI: error: invalid immediate: only 4-bit values are legal
77
88 s_set_gpr_idx_on s0, -1
9 // GCN: error: invalid operand for instruction
9 // VI: error: invalid immediate: only 4-bit values are legal
10
11 s_set_gpr_idx_on s0, gpr_idx
12 // VI: error: expected absolute expression
13
14 s_set_gpr_idx_on s0, gpr_idx(
15 // VI: error: expected a VGPR index mode or a closing parenthesis
16
17 s_set_gpr_idx_on s0, gpr_idx(X)
18 // VI: error: expected a VGPR index mode
19
20 s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC1,DST)
21 // VI: error: duplicate VGPR index mode
22
23 s_set_gpr_idx_on s0, gpr_idx(DST
24 // VI: error: expected a comma or a closing parenthesis
25
26 s_set_gpr_idx_on s0, gpr_idx(SRC0,
27 // VI: error: expected a VGPR index mode
1028
1129 s_cmp_eq_i32 0x12345678, 0x12345679
1230 // GCN: error: only one literal operand is allowed
7070 // VI: s_cmp_lg_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x13,0xbf]
7171 // NOSICI: error: instruction not supported on this GPU
7272
73 gpr_idx = 1
74 s_set_gpr_idx_on s0, gpr_idx
75 // VI: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf]
76 // NOSICI: error:
77
78 gpr_idx_mode = 10
79 s_set_gpr_idx_on s0, gpr_idx_mode + 5
80 // VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf]
81 // NOSICI: error:
82
7383 s_set_gpr_idx_on s0, 0
74 // VI: s_set_gpr_idx_on s0, 0 ; encoding: [0x00,0x00,0x11,0xbf]
75 // NOSICI: error: instruction not supported on this GPU
84 // VI: s_set_gpr_idx_on s0, gpr_idx() ; encoding: [0x00,0x00,0x11,0xbf]
85 // NOSICI: error:
86
87 s_set_gpr_idx_on s0, gpr_idx()
88 // VI: s_set_gpr_idx_on s0, gpr_idx() ; encoding: [0x00,0x00,0x11,0xbf]
89 // NOSICI: error:
7690
7791 s_set_gpr_idx_on s0, 1
78 // VI: s_set_gpr_idx_on s0, src0 ; encoding: [0x00,0x01,0x11,0xbf]
79 // NOSICI: error: instruction not supported on this GPU
92 // VI: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf]
93 // NOSICI: error:
94
95 s_set_gpr_idx_on s0, gpr_idx(SRC0)
96 // VI: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf]
97 // NOSICI: error:
8098
8199 s_set_gpr_idx_on s0, 3
82 // VI: s_set_gpr_idx_on s0, src0 src1 ; encoding: [0x00,0x03,0x11,0xbf]
83 // NOSICI: error: instruction not supported on this GPU
100 // VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1) ; encoding: [0x00,0x03,0x11,0xbf]
101 // NOSICI: error:
102
103 s_set_gpr_idx_on s0, gpr_idx(SRC1,SRC0)
104 // VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1) ; encoding: [0x00,0x03,0x11,0xbf]
105 // NOSICI: error:
84106
85107 s_set_gpr_idx_on s0, 15
86 // VI: s_set_gpr_idx_on s0, dst src0 src1 src2 ; encoding: [0x00,0x0f,0x11,0xbf]
87 // NOSICI: error: instruction not supported on this GPU
108 // VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf]
109 // NOSICI: error:
110
111 s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC2,SRC1)
112 // VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf]
113 // NOSICI: error:
231231
232232 s_set_gpr_idx_off
233233 // VI: s_set_gpr_idx_off ; encoding: [0x00,0x00,0x9c,0xbf]
234 // NOSICI: error: instruction not supported on this GPU
234 // NOSICI: error:
235235
236236 s_set_gpr_idx_mode 0
237 // VI: s_set_gpr_idx_mode 0 ; encoding: [0x00,0x00,0x9d,0xbf]
238 // NOSICI: error: instruction not supported on this GPU
237 // VI: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf]
238 // NOSICI: error:
239
240 s_set_gpr_idx_mode gpr_idx()
241 // VI: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf]
242 // NOSICI: error:
239243
240244 s_set_gpr_idx_mode 15
241 // VI: s_set_gpr_idx_mode dst src0 src1 src2 ; encoding: [0x0f,0x00,0x9d,0xbf]
242 // NOSICI: error: instruction not supported on this GPU
245 // VI: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
246 // NOSICI: error:
247
248 s_set_gpr_idx_mode gpr_idx(SRC2,SRC1,SRC0,DST)
249 // VI: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
250 // NOSICI: error:
243251
244252 s_endpgm_saved
245253 // VI: s_endpgm_saved ; encoding: [0x00,0x00,0x9b,0xbf]
5252
5353 # GCN: s_bitcmp0_b32 0xafaaffff, 0xafaaffff ; encoding: [0xff,0xff,0x0c,0xbf,0xff,0xff,0xaa,0xaf]
5454 0xff 0xff 0x0c 0xbf 0xff 0xff 0xaa 0xaf
55
56 # GCN: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf]
57 0x00,0x01,0x11,0xbf
58
59 # GCN: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf]
60 0x00,0x0f,0x11,0xbf
61
62 # GCN: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf]
63 0x00,0x0f,0x11,0xbf
64
65 # GCN: s_set_gpr_idx_on s0, 0xff ; encoding: [0x00,0xff,0x11,0xbf]
66 0x00,0xff,0x11,0xbf
124124
125125 # GCN: s_ttracedata ; encoding: [0x00,0x00,0x96,0xbf]
126126 0x00 0x00 0x96 0xbf
127
128 # GCN: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf]
129 0x00,0x00,0x9d,0xbf
130
131 # GCN: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
132 0x0f,0x00,0x9d,0xbf