llvm.org GIT mirror llvm / ea7da50
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47795 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Lenharth 12 years ago
5 changed file(s) with 88 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
114114 "hasREX_WPrefix",
115115 "ImmTypeBits",
116116 "FPFormBits",
117 "hasLockPrefix",
117118 "Opcode"];
118119 let TSFlagsShifts = [0,
119120 6,
122123 12,
123124 13,
124125 16,
126 19,
125127 24];
126128 }
127129
538538 void Emitter::emitInstruction(const MachineInstr &MI,
539539 const TargetInstrDesc *Desc) {
540540 unsigned Opcode = Desc->Opcode;
541
542 // Emit the lock opcode prefix as needed.
543 if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
541544
542545 // Emit the repeat opcode prefix as needed.
543546 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
6161 class OpSize { bit hasOpSizePrefix = 1; }
6262 class AdSize { bit hasAdSizePrefix = 1; }
6363 class REX_W { bit hasREX_WPrefix = 1; }
64 class LOCK { bit hasLockPrefix = 1; }
6465 class TB { bits<4> Prefix = 1; }
6566 class REP { bits<4> Prefix = 2; }
6667 class D8 { bits<4> Prefix = 3; }
101102 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
102103 FPFormat FPForm; // What flavor of FP instruction is this?
103104 bits<3> FPFormBits = 0;
105 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
104106 }
105107
106108 class I o, Format f, dag outs, dag ins, string asm, list pattern>
215215 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
216216 SpecialFP = 7 << FPTypeShift,
217217
218 // Bits 19 -> 23 are unused
218 // Lock prefix
219 LOCKShift = 19,
220 LOCK = 1 << LOCKShift,
221
222 // Bits 20 -> 23 are unused
219223 OpcodeShift = 24,
220224 OpcodeMask = 0xFF << OpcodeShift
221225 };
25372537 //===----------------------------------------------------------------------===//
25382538 // Atomic support
25392539 //
2540 let Defs = [EAX] in
2541 def LCMPXCHGL : I<0, Pseudo, (outs GR32:$dst),
2542 (ins GR32:$ptr, GR32:$cmp, GR32:$swap),
2543 "movl $cmp, %eax ; lock cmpxchgl $swap,($ptr) ; movl %eax, $dst",
2544 [(set GR32:$dst, (atomic_lcs_32 GR32:$ptr, GR32:$cmp, GR32:$swap))]>;
2540
2541 //FIXME: Please check the format
2542
2543 let Defs = [EAX], Uses = [EAX] in {
2544 def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR32:$swap),
2545 "cmpxchgl $swap,($ptr)", []>, TB;
2546 def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR32:$swap),
2547 "lock cmpxchgl $swap,($ptr)", []>, TB, LOCK;
2548 }
2549 let Defs = [AX], Uses = [AX] in {
2550 def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR16:$swap),
2551 "cmpxchgw $swap,($ptr)", []>, TB, OpSize;
2552 def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR16:$swap),
2553 "cmpxchgw $swap,($ptr)", []>, TB, OpSize, LOCK;
2554 }
2555 let Defs = [AL], Uses = [AL] in {
2556 def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins GR32:$ptr, GR8:$swap),
2557 "cmpxchgb $swap,($ptr)", []>, TB;
2558 def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins GR32:$ptr, GR8:$swap),
2559 "cmpxchgb $swap,($ptr)", []>, TB, LOCK;
2560 }
2561
2562 let Constraints = "$val = $dst" in {
2563 def LXADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2564 "lock xadd $val, $ptr",
2565 [(set GR32:$dst, (atomic_las_32 addr:$ptr, GR32:$val))]>,
2566 TB, LOCK;
2567 def LXADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2568 "lock xadd $val, $ptr",
2569 [(set GR16:$dst, (atomic_las_16 addr:$ptr, GR16:$val))]>,
2570 TB, OpSize, LOCK;
2571 def LXADD8 : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2572 "lock xadd $val, $ptr",
2573 [(set GR8:$dst, (atomic_las_8 addr:$ptr, GR8:$val))]>,
2574 TB, LOCK;
2575 def XADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2576 "lock xadd $val, $ptr", []>, TB;
2577 def XADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2578 "lock xadd $val, $ptr", []>, TB, OpSize;
2579 def XADD8 : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2580 "lock xadd $val, $ptr", []>, TB;
2581
2582 def LXCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2583 "lock xchg $val, $ptr",
2584 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>, LOCK;
2585 def LXCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2586 "lock xchg $val, $ptr",
2587 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2588 OpSize, LOCK;
2589 def LXCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2590 "lock xchg $val, $ptr",
2591 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>, LOCK;
2592 def XCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2593 "lock xchg $val, $ptr", []>;
2594 def XCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2595 "lock xchg $val, $ptr", []>, OpSize;
2596 def XCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2597 "lock xchg $val, $ptr", []>;
2598 }
2599
2600 //FIXME: these are a hack until the patterns using the LCMPXCHG written
2601 let Defs = [EAX], Uses = [EAX] in
2602 def PLCMPXCHG32 : I<0, Pseudo, (outs GR32:$dst),
2603 (ins i32mem:$ptr, GR32:$cmp, GR32:$swap),
2604 "movl $cmp, %eax \n lock \n cmpxchgl $swap,$ptr \n movl %eax, $dst",
2605 [(set GR32:$dst, (atomic_lcs_32 addr:$ptr, GR32:$cmp, GR32:$swap))]>;
2606 let Defs = [AX] in
2607 def PLCMPXCHG16 : I<0, Pseudo, (outs GR16:$dst),
2608 (ins i16mem:$ptr, GR16:$cmp, GR16:$swap),
2609 "movw $cmp, %ax \n lock \n cmpxchgw $swap,$ptr \n movw %ax, $dst",
2610 [(set GR16:$dst, (atomic_lcs_16 addr:$ptr, GR16:$cmp, GR16:$swap))]>;
2611 let Defs = [AL] in
2612 def PLCMPXCHG8 : I<0, Pseudo, (outs GR8:$dst),
2613 (ins i8mem:$ptr, GR8:$cmp, GR8:$swap),
2614 "movb $cmp, %al \n lock cmpxchgb $swap,$ptr \n movb %al, $dst",
2615 [(set GR8:$dst, (atomic_lcs_8 addr:$ptr, GR8:$cmp, GR8:$swap))]>;
25452616
25462617 //===----------------------------------------------------------------------===//
25472618 // Non-Instruction Patterns