llvm.org GIT mirror llvm / ea50fab
Remove a bunch more SparcV9 specific stuff git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28093 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 14 years ago
14 changed file(s) with 29 addition(s) and 147 deletion(s). Raw diff Collapse all Expand all
5656 //
5757 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
5858 // MachineInstr* minstr will point to the instruction that computes reg.
59 //
60 // - %sp will be of virtual register type MO_MachineReg.
61 // The field regNum identifies the machine register.
6259 //
6360 // - NumElements will be of virtual register type MO_VirtualReg.
6461 // The field Value* value identifies the value.
7471 enum {
7572 DEFFLAG = 0x01, // this is a def of the operand
7673 USEFLAG = 0x02, // this is a use of the operand
77 PCRELATIVE = 0x40 // Operand is relative to PC, not a global address
7874 };
7975
8076 public:
9288
9389 enum MachineOperandType {
9490 MO_VirtualRegister, // virtual register for *value
95 MO_MachineRegister, // pre-assigned machine register `regNum'
9691 MO_SignExtendedImmed,
9792 MO_UnextendedImmed,
9893 MO_MachineBasicBlock, // MachineBasicBlock reference
151146 extra.regNum = Reg;
152147 }
153148
154 MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy,
155 bool isPCRelative = false)
156 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
157 assert(OpTy != MachineOperand::MO_GlobalAddress);
158 zeroContents();
159 contents.value = V;
160 extra.regNum = -1;
161 }
162
163149 MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy,
164 bool isPCRelative = false, int Offset = 0)
165 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
150 int Offset = 0)
151 : flags(UseTy), opType(OpTy) {
166152 assert(OpTy == MachineOperand::MO_GlobalAddress);
167153 zeroContents ();
168154 contents.value = (Value*)V;
176162 extra.regNum = -1;
177163 }
178164
179 MachineOperand(const char *SymName, bool isPCRelative, int Offset)
180 : flags(isPCRelative?PCRELATIVE:0), opType(MO_ExternalSymbol) {
165 MachineOperand(const char *SymName, int Offset)
166 : flags(0), opType(MO_ExternalSymbol) {
181167 zeroContents ();
182168 contents.SymbolName = SymName;
183169 extra.offset = Offset;
191177 extra = M.extra;
192178 }
193179
194
195180 ~MachineOperand() {}
196181
197182 const MachineOperand &operator=(const MachineOperand &MO) {
217202 /// Note: The sparc backend should not use this method.
218203 ///
219204 bool isRegister() const {
220 return opType == MO_MachineRegister || opType == MO_VirtualRegister;
205 return opType == MO_VirtualRegister;
221206 }
222207
223208 /// Accessors that tell you what kind of MachineOperand you're looking at.
246231 assert(opType == MO_VirtualRegister && "Wrong MachineOperand accessor");
247232 return contents.value;
248233 }
249 int getMachineRegNum() const {
250 assert(opType == MO_MachineRegister && "Wrong MachineOperand accessor");
251 return extra.regNum;
252 }
253234 int64_t getImmedValue() const {
254235 assert(isImmediate() && "Wrong MachineOperand accessor");
255236 return contents.immedVal;
300281 /// allocated to this operand.
301282 ///
302283 bool hasAllocatedReg() const {
303 return (extra.regNum >= 0 &&
304 (opType == MO_VirtualRegister || opType == MO_MachineRegister));
284 return extra.regNum >= 0 && opType == MO_VirtualRegister;
305285 }
306286
307287 /// getReg - Returns the register number. It is a runtime error to call this
444424 // Accessors to add operands when building up machine instructions
445425 //
446426
447 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
448 /// operands list...
449 ///
450 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
451 assert(!OperandsComplete() &&
452 "Trying to add an operand to a machine instr that is already done!");
453 operands.push_back(
454 MachineOperand(V, MachineOperand::MO_VirtualRegister,
455 !isDef ? MachineOperand::Use :
456 (isDefAndUse ? MachineOperand::UseAndDef :
457 MachineOperand::Def)));
458 }
459
460 void addRegOperand(Value *V,
461 MachineOperand::UseType UTy = MachineOperand::Use,
462 bool isPCRelative = false) {
463 assert(!OperandsComplete() &&
464 "Trying to add an operand to a machine instr that is already done!");
465 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
466 UTy, isPCRelative));
467 }
468
469427 /// addRegOperand - Add a symbolic virtual register reference...
470428 ///
471429 void addRegOperand(int reg, bool isDef) {
486444 MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy));
487445 }
488446
489 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
490 ///
491 void addMachineRegOperand(int reg, bool isDef) {
492 assert(!OperandsComplete() &&
493 "Trying to add an operand to a machine instr that is already done!");
494 operands.push_back(
495 MachineOperand(reg, MachineOperand::MO_MachineRegister,
496 isDef ? MachineOperand::Def : MachineOperand::Use));
497 }
498
499 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
500 ///
501 void addMachineRegOperand(int reg,
502 MachineOperand::UseType UTy = MachineOperand::Use) {
503 assert(!OperandsComplete() &&
504 "Trying to add an operand to a machine instr that is already done!");
505 operands.push_back(
506 MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy));
507 }
508
509447 /// addZeroExtImmOperand - Add a zero extended constant argument to the
510448 /// machine instruction.
511449 ///
568506 operands.push_back(MachineOperand(I, MachineOperand::MO_JumpTableIndex));
569507 }
570508
571 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative, int Offset) {
509 void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
572510 assert(!OperandsComplete() &&
573511 "Trying to add an operand to a machine instr that is already done!");
574512 operands.push_back(
575513 MachineOperand(GV, MachineOperand::MO_GlobalAddress,
576 MachineOperand::Use, isPCRelative, Offset));
514 MachineOperand::Use, Offset));
577515 }
578516
579517 /// addExternalSymbolOperand - Add an external symbol operand to this instr
580518 ///
581 void addExternalSymbolOperand(const char *SymName, bool isPCRelative) {
582 operands.push_back(MachineOperand(SymName, isPCRelative, 0));
519 void addExternalSymbolOperand(const char *SymName) {
520 operands.push_back(MachineOperand(SymName, 0));
583521 }
584522
585523 //===--------------------------------------------------------------------===//
4343 MachineOperand::UseType Ty = MachineOperand::Use) const {
4444 MI->addRegOperand(RegNo, Ty);
4545 return *this;
46 }
47
48 /// addReg - Add an LLVM value that is to be used as a register...
49 ///
50 const MachineInstrBuilder &addReg(
51 Value *V,
52 MachineOperand::UseType Ty = MachineOperand::Use) const {
53 MI->addRegOperand(V, Ty);
54 return *this;
55 }
56
57 /// addRegDef - Add an LLVM value that is to be defined as a register... this
58 /// is the same as addReg(V, MachineOperand::Def).
59 ///
60 const MachineInstrBuilder &addRegDef(Value *V) const {
61 return addReg(V, MachineOperand::Def);
6246 }
6347
6448 /// addImm - Add a new immediate operand.
11195 }
11296
11397 const MachineInstrBuilder &addGlobalAddress(GlobalValue *GV,
114 bool isPCRelative = false,
11598 int Offset = 0) const {
116 MI->addGlobalAddressOperand(GV, isPCRelative, Offset);
99 MI->addGlobalAddressOperand(GV, Offset);
117100 return *this;
118101 }
119102
120 const MachineInstrBuilder &addExternalSymbol(const char *FnName,
121 bool isPCRelative = false) const{
122 MI->addExternalSymbolOperand(FnName, isPCRelative);
103 const MachineInstrBuilder &addExternalSymbol(const char *FnName) const{
104 MI->addExternalSymbolOperand(FnName);
123105 return *this;
124106 }
125107 };
140140 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
141141 assert(i < getNumOperands()); // must be explicit op
142142
143 operands[i].opType = MachineOperand::MO_MachineRegister;
143 operands[i].opType = MachineOperand::MO_VirtualRegister;
144144 operands[i].contents.value = NULL;
145145 operands[i].extra.regNum = regNum;
146146 }
186186 if (MO.hasAllocatedReg())
187187 OutputReg(OS, MO.getReg(), MRI);
188188 break;
189 case MachineOperand::MO_MachineRegister:
190 OutputReg(OS, MO.getMachineRegNum(), MRI);
191 break;
192189 case MachineOperand::MO_SignExtendedImmed:
193190 OS << (long)MO.getImmedValue();
194191 break;
296293 OutputValue(OS, MO.getVRegValue());
297294 }
298295 break;
299 case MachineOperand::MO_MachineRegister:
300 OutputReg(OS, MO.getMachineRegNum());
301 break;
302296 case MachineOperand::MO_SignExtendedImmed:
303297 OS << (long)MO.getImmedValue();
304298 break;
109109 MI->addRegOperand(R->getReg(), MachineOperand::Use);
110110 } else if (GlobalAddressSDNode *TGA =
111111 dyn_cast(Op)) {
112 MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
112 MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
113113 } else if (BasicBlockSDNode *BB =
114114 dyn_cast(Op)) {
115115 MI->addMachineBasicBlockOperand(BB->getBasicBlock());
142142 MI->addConstantPoolIndexOperand(Idx, Offset);
143143 } else if (ExternalSymbolSDNode *ES =
144144 dyn_cast(Op)) {
145 MI->addExternalSymbolOperand(ES->getSymbol(), false);
145 MI->addExternalSymbolOperand(ES->getSymbol());
146146 } else {
147147 assert(Op.getValueType() != MVT::Other &&
148148 Op.getValueType() != MVT::Flag &&
295295 // Add the asm string as an external symbol operand.
296296 const char *AsmStr =
297297 cast(Node->getOperand(1))->getSymbol();
298 MI->addExternalSymbolOperand(AsmStr, false);
298 MI->addExternalSymbolOperand(AsmStr);
299299
300300 // Add all of the operand registers to the instruction.
301301 for (unsigned i = 2; i != NumOps;) {
310310 case 1: // Use of register.
311311 for (; NumVals; --NumVals, ++i) {
312312 unsigned Reg = cast(Node->getOperand(i))->getReg();
313 MI->addMachineRegOperand(Reg, MachineOperand::Use);
313 MI->addRegOperand(Reg, MachineOperand::Use);
314314 }
315315 break;
316316 case 2: // Def of register.
317317 for (; NumVals; --NumVals, ++i) {
318318 unsigned Reg = cast(Node->getOperand(i))->getReg();
319 MI->addMachineRegOperand(Reg, MachineOperand::Def);
319 MI->addRegOperand(Reg, MachineOperand::Def);
320320 }
321321 break;
322322 case 3: { // Immediate.
7676 void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
7777 {
7878 const MachineOperand &MO = MI->getOperand(opNum);
79 if (MO.getType() == MachineOperand::MO_MachineRegister) {
79 if (MO.getType() == MachineOperand::MO_VirtualRegister) {
8080 assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
8181 O << TM.getRegisterInfo()->get(MO.getReg()).Name;
8282 } else if (MO.isImmediate()) {
9393
9494 switch (MO.getType()) {
9595 case MachineOperand::MO_VirtualRegister:
96 if (Value *V = MO.getVRegValueOrNull()) {
97 O << "<" << V->getName() << ">";
98 return;
99 }
100 // FALLTHROUGH
101 case MachineOperand::MO_MachineRegister:
10296 O << RI.get(MO.getReg()).Name;
10397 return;
10498
262262 .addReg(Alpha::R29).addImm(curgpdist);
263263
264264 //evil const_cast until MO stuff setup to handle const
265 BuildMI(MBB, MBBI, Alpha::ALTENT, 1).addGlobalAddress(const_cast(MF.getFunction()), true);
265 BuildMI(MBB, MBBI, Alpha::ALTENT, 1)
266 .addGlobalAddress(const_cast(MF.getFunction()));
266267
267268 // Get the number of bytes to allocate from the FrameInfo
268269 long NumBytes = MFI->getStackSize();
6565 // This method is used by the tablegen'erated instruction printer.
6666 void printOperand(const MachineInstr *MI, unsigned OpNo){
6767 const MachineOperand &MO = MI->getOperand(OpNo);
68 if (MO.getType() == MachineOperand::MO_MachineRegister) {
68 if (MO.getType() == MachineOperand::MO_VirtualRegister) {
6969 assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
7070 //XXX Bug Workaround: See note in Printer::doInitialization about %.
7171 O << TM.getRegisterInfo()->get(MO.getReg()).Name;
173173 const MRegisterInfo &RI = *TM.getRegisterInfo();
174174 switch (MO.getType()) {
175175 case MachineOperand::MO_VirtualRegister:
176 if (Value *V = MO.getVRegValueOrNull()) {
177 O << "<" << V->getName() << ">";
178 return;
179 }
180 // FALLTHROUGH
181 case MachineOperand::MO_MachineRegister:
182176 O << RI.get(MO.getReg()).Name;
183177 return;
184178
8585
8686 void printOperand(const MachineInstr *MI, unsigned OpNo) {
8787 const MachineOperand &MO = MI->getOperand(OpNo);
88 if (MO.getType() == MachineOperand::MO_MachineRegister) {
88 if (MO.getType() == MachineOperand::MO_VirtualRegister) {
8989 assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
9090 O << TM.getRegisterInfo()->get(MO.getReg()).Name;
9191 } else if (MO.isImmediate()) {
352352 int new_symbol;
353353
354354 switch (MO.getType()) {
355 case MachineOperand::MO_VirtualRegister:
356 if (Value *V = MO.getVRegValueOrNull()) {
357 O << "<" << V->getName() << ">";
358 return;
359 }
360 // FALLTHROUGH
361 case MachineOperand::MO_MachineRegister:
362355 O << RI.get(MO.getReg()).Name;
363356 return;
364357
146146 }
147147 switch (MO.getType()) {
148148 case MachineOperand::MO_VirtualRegister:
149 if (Value *V = MO.getVRegValueOrNull()) {
150 O << "<" << V->getName() << ">";
151 break;
152 }
153 // FALLTHROUGH
154 case MachineOperand::MO_MachineRegister:
155149 if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
156150 O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
157151 else
194188
195189 MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
196190
197 if ((OpTy == MachineOperand::MO_VirtualRegister ||
198 OpTy == MachineOperand::MO_MachineRegister) &&
191 if (OpTy == MachineOperand::MO_VirtualRegister &&
199192 MI->getOperand(opNum+1).getReg() == SP::G0)
200193 return; // don't print "+%g0"
201194 if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
108108 const MRegisterInfo &RI = *TM.getRegisterInfo();
109109 switch (MO.getType()) {
110110 case MachineOperand::MO_VirtualRegister:
111 case MachineOperand::MO_MachineRegister:
112111 assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
113112 "Virtual registers should not make it this far!");
114113 O << '%';
9292 assert (0);
9393 MIB.addZImm(AM.Scale).addReg(AM.IndexReg);
9494 if (AM.GV)
95 return MIB.addGlobalAddress(AM.GV, false, AM.Disp);
95 return MIB.addGlobalAddress(AM.GV, AM.Disp);
9696 else
9797 return MIB.addSImm(AM.Disp);
9898 }
114114 const MRegisterInfo &RI = *TM.getRegisterInfo();
115115 switch (MO.getType()) {
116116 case MachineOperand::MO_VirtualRegister:
117 if (Value *V = MO.getVRegValueOrNull()) {
118 O << "<" << V->getName() << ">";
119 return;
120 }
121 // FALLTHROUGH
122 case MachineOperand::MO_MachineRegister:
123117 if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
124118 O << RI.get(MO.getReg()).Name;
125119 else
3636 void printOperand(const MachineInstr *MI, unsigned OpNo,
3737 const char *Modifier = 0) {
3838 const MachineOperand &MO = MI->getOperand(OpNo);
39 if (MO.getType() == MachineOperand::MO_MachineRegister) {
40 assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
39 if (MO.getType() == MachineOperand::MO_VirtualRegister) {
40 assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??");
4141 O << TM.getRegisterInfo()->get(MO.getReg()).Name;
4242 } else {
4343 printOp(MO, Modifier);
149149 else if (MI->getOperand(1).isGlobalAddress())
150150 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
151151 .addGlobalAddress(MI->getOperand(1).getGlobal(),
152 false, MI->getOperand(1).getOffset());
152 MI->getOperand(1).getOffset());
153153 else if (MI->getOperand(1).isJumpTableIndex())
154154 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
155155 .addJumpTableIndex(MI->getOperand(1).getJumpTableIndex());