llvm.org GIT mirror llvm / ea42b4f
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306341 91177308-0d34-0410-b5e6-96231b3b80d8 Eugene Zelenko 3 years ago
18 changed file(s) with 361 addition(s) and 233 deletion(s). Raw diff Collapse all Expand all
None //===-- llvm/CodeGen/GlobalISel/CallLowering.h - Call lowering --*- C++ -*-===//
0 //===- llvm/CodeGen/GlobalISel/CallLowering.h - Call lowering ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1414 #ifndef LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
1515 #define LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
1616
17 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/ArrayRef.h"
1818 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/ValueTypes.h"
20 #include "llvm/IR/Function.h"
19 #include "llvm/CodeGen/MachineValueType.h"
20 #include "llvm/IR/CallSite.h"
21 #include "llvm/IR/CallingConv.h"
22 #include "llvm/Support/ErrorHandling.h"
2123 #include "llvm/Target/TargetCallingConv.h"
24 #include
25 #include
2226
2327 namespace llvm {
24 // Forward declarations.
28
29 class DataLayout;
30 class Function;
2531 class MachineIRBuilder;
2632 class MachineOperand;
33 struct MachinePointerInfo;
34 class MachineRegisterInfo;
2735 class TargetLowering;
36 class Type;
2837 class Value;
2938
3039 class CallLowering {
3140 const TargetLowering *TLI;
41
3242 public:
3343 struct ArgInfo {
3444 unsigned Reg;
4858 /// arugment should go, exactly what happens can vary slightly. This
4959 /// class abstracts the differences.
5060 struct ValueHandler {
61 ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
62 CCAssignFn *AssignFn)
63 : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn) {}
64
65 virtual ~ValueHandler() = default;
66
5167 /// Materialize a VReg containing the address of the specified
5268 /// stack-based object. This is either based on a FrameIndex or
5369 /// direct SP manipulation, depending on the context. \p MPO
88104 return AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
89105 }
90106
91 ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
92 CCAssignFn *AssignFn)
93 : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn) {}
94
95 virtual ~ValueHandler() {}
96
97107 MachineIRBuilder &MIRBuilder;
98108 MachineRegisterInfo &MRI;
99109 CCAssignFn *AssignFn;
111121 return static_cast(TLI);
112122 }
113123
114
115124 template
116125 void setArgFlags(ArgInfo &Arg, unsigned OpNum, const DataLayout &DL,
117126 const FuncInfoTy &FuncInfo) const;
125134
126135 public:
127136 CallLowering(const TargetLowering *TLI) : TLI(TLI) {}
128 virtual ~CallLowering() {}
137 virtual ~CallLowering() = default;
129138
130139 /// This hook must be implemented to lower outgoing return values, described
131140 /// by \p Val, into the specified virtual register \p VReg.
199208 unsigned ResReg, ArrayRef ArgRegs,
200209 std::function GetCalleeReg) const;
201210 };
202 } // End namespace llvm.
203
204 #endif
211
212 } // end namespace llvm
213
214 #endif // LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
None //===-- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ---*- C++ -*-===//
0 //===- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1818 #ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
1919 #define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
2020
21 #include "Types.h"
2221 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/SetVector.h"
22 #include "llvm/ADT/SmallVector.h"
2423 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
24 #include "llvm/CodeGen/GlobalISel/Types.h"
2525 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/IR/Intrinsics.h"
27 #include
28 #include
2629
2730 namespace llvm {
28 // Forward declarations.
31
32 class AllocaInst;
2933 class BasicBlock;
34 class CallInst;
3035 class CallLowering;
3136 class Constant;
37 class DataLayout;
3238 class Instruction;
3339 class MachineBasicBlock;
3440 class MachineFunction;
3541 class MachineInstr;
42 class MachineRegisterInfo;
3643 class OptimizationRemarkEmitter;
37 class MachineRegisterInfo;
44 class PHINode;
3845 class TargetPassConfig;
46 class User;
47 class Value;
3948
4049 // Technically the pass should run on an hypothetical MachineModule,
4150 // since it should translate Global into some sort of MachineGlobal.
5261 private:
5362 /// Interface used to lower the everything related to calls.
5463 const CallLowering *CLI;
64
5565 /// Mapping of the values of the current LLVM IR function
5666 /// to the related virtual registers.
5767 ValueToVReg ValToVReg;
6676 // a mapping between the edges arriving at the BasicBlock to the corresponding
6777 // created MachineBasicBlocks. Some BasicBlocks that get translated to a
6878 // single MachineBasicBlock may also end up in this Map.
69 typedef std::pair CFGEdge;
79 using CFGEdge = std::pair;
7080 DenseMap> MachinePreds;
7181
7282 // List of stubbed PHI instructions, for values and basic blocks to be filled
164174 return translateCompare(U, MIRBuilder);
165175 }
166176
167
168177 /// Add remaining operands onto phis we've translated. Executed after all
169178 /// MachineBasicBlocks for the function have been created.
170179 void finishPendingPhis();
355364 MachineFunction *MF;
356365
357366 /// MachineRegisterInfo used to create virtual registers.
358 MachineRegisterInfo *MRI;
367 MachineRegisterInfo *MRI = nullptr;
359368
360369 const DataLayout *DL;
361370
429438 bool runOnMachineFunction(MachineFunction &MF) override;
430439 };
431440
432 } // End namespace llvm.
433 #endif
441 } // end namespace llvm
442
443 #endif // LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
None //==-- llvm/CodeGen/GlobalISel/InstructionSelector.h -------------*- C++ -*-==//
0 //===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1515 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
1616 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
1717
18 #include "llvm/ADT/Optional.h"
1918 #include
19 #include
2020 #include
2121 #include
22 #include
2223
2324 namespace llvm {
25
2426 class MachineInstr;
2527 class MachineInstrBuilder;
26 class MachineFunction;
2728 class MachineOperand;
2829 class MachineRegisterInfo;
2930 class RegisterBankInfo;
5960 /// Provides the logic to select generic machine instructions.
6061 class InstructionSelector {
6162 public:
62 virtual ~InstructionSelector() {}
63 virtual ~InstructionSelector() = default;
6364
6465 /// Select the (possibly generic) instruction \p I to only use target-specific
6566 /// opcodes. It is OK to insert multiple instructions, but they cannot be
7576 virtual bool select(MachineInstr &I) const = 0;
7677
7778 protected:
78 typedef std::function ComplexRendererFn;
79 using ComplexRendererFn = std::function;
7980
8081 InstructionSelector();
8182
109110 bool isObviouslySafeToFold(MachineInstr &MI) const;
110111 };
111112
112 } // End namespace llvm.
113 } // end namespace llvm
113114
114 #endif
115 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
None //==-- llvm/CodeGen/GlobalISel/LegalizerInfo.h -------------------*- C++ -*-==//
0 //===- llvm/CodeGen/GlobalISel/LegalizerInfo.h ------------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZER_H
15 #define LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZER_H
14 #ifndef LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H
15 #define LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H
1616
1717 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/CodeGen/LowLevelType.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/Optional.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/Support/LowLevelTypeImpl.h"
1923 #include "llvm/Target/TargetOpcodes.h"
20
2124 #include
22 #include <functional>
25 #include <cassert>
26 #include
27 #include
2328
2429 namespace llvm {
25 class LLVMContext;
30
2631 class MachineInstr;
2732 class MachineIRBuilder;
2833 class MachineRegisterInfo;
29 class Type;
30 class VectorType;
3134
3235 /// Legalization is decided based on an instruction's opcode, which type slot
3336 /// we're considering, and what the existing type is. These aspects are gathered
3437 /// together for convenience in the InstrAspect class.
3538 struct InstrAspect {
3639 unsigned Opcode;
37 unsigned Idx;
40 unsigned Idx = 0;
3841 LLT Type;
3942
40 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Idx(0), Type(Type) {}
43 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {}
4144 InstrAspect(unsigned Opcode, unsigned Idx, LLT Type)
4245 : Opcode(Opcode), Idx(Idx), Type(Type) {}
4346
123126 assert(!ScalarTy.isVector());
124127 ScalarInVectorActions[std::make_pair(Opcode, ScalarTy)] = Action;
125128 }
126
127129
128130 /// Determine what action should be taken to legalize the given generic
129131 /// instruction opcode, type-index and type. Requires computeTables to have
202204 static const int FirstOp = TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START;
203205 static const int LastOp = TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
204206
205 typedef DenseMap TypeMap;
206 typedef DenseMap, LegalizeAction> SIVActionMap;
207 using TypeMap = DenseMap;
208 using SIVActionMap = DenseMap, LegalizeAction>;
207209
208210 SmallVector Actions[LastOp - FirstOp + 1];
209211 SIVActionMap ScalarInVectorActions;
210212 DenseMap, uint16_t> MaxLegalVectorElts;
211213 DenseMap DefaultActions;
212214
213 bool TablesInitialized;
215 bool TablesInitialized = false;
214216 };
215217
216
217 } // End namespace llvm.
218
219 #endif
218 } // end namespace llvm
219
220 #endif // LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H
None //== llvm/CodeGen/GlobalISel/RegBankSelect.h - Reg Bank Selector -*- C++ -*-==//
0 //=- llvm/CodeGen/GlobalISel/RegBankSelect.h - Reg Bank Selector --*- C++ -*-=//
11 //
22 // The LLVM Compiler Infrastructure
33 //
6363 #ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H
6464 #define LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H
6565
66 #include "llvm/ADT/SmallVector.h"
6667 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
6768 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
69 #include "llvm/CodeGen/MachineBasicBlock.h"
6870 #include "llvm/CodeGen/MachineFunctionPass.h"
6971 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
72 #include
73 #include
74 #include
7075
7176 namespace llvm {
72 // Forward declarations.
77
7378 class BlockFrequency;
79 class MachineBlockFrequencyInfo;
7480 class MachineBranchProbabilityInfo;
75 class MachineBlockFrequencyInfo;
81 class MachineOperand;
7682 class MachineRegisterInfo;
83 class Pass;
84 class raw_ostream;
7785 class TargetPassConfig;
7886 class TargetRegisterInfo;
79 class raw_ostream;
8087
8188 /// This pass implements the reg bank selector pass used in the GlobalISel
8289 /// pipeline. At the end of this pass, all register operands have been assigned
104111 protected:
105112 /// Tell if the insert point has already been materialized.
106113 bool WasMaterialized = false;
114
107115 /// Materialize the insertion point.
108116 ///
109117 /// If isSplit() is true, this involves actually splitting
127135 virtual MachineBasicBlock::iterator getPointImpl() = 0;
128136
129137 public:
130 virtual ~InsertPoint() {}
138 virtual ~InsertPoint() = default;
131139
132140 /// The first call to this method will cause the splitting to
133141 /// happen if need be, then sub sequent calls just return
196204 private:
197205 /// Insertion point.
198206 MachineInstr &Instr;
207
199208 /// Does the insertion point is before or after Instr.
200209 bool Before;
201210
215224 public:
216225 /// Create an insertion point before (\p Before=true) or after \p Instr.
217226 InstrInsertPoint(MachineInstr &Instr, bool Before = true);
227
218228 bool isSplit() const override;
219229 uint64_t frequency(const Pass &P) const override;
220230
227237 private:
228238 /// Insertion point.
229239 MachineBasicBlock &MBB;
240
230241 /// Does the insertion point is at the beginning or end of MBB.
231242 bool Beginning;
232243
251262 assert((Beginning || MBB.getFirstTerminator() == MBB.end()) &&
252263 "Invalid end point");
253264 }
265
254266 bool isSplit() const override { return false; }
255267 uint64_t frequency(const Pass &P) const override;
256268 bool canMaterialize() const override { return true; };
261273 private:
262274 /// Source of the edge.
263275 MachineBasicBlock &Src;
276
264277 /// Destination of the edge.
265278 /// After the materialization is done, this hold the basic block
266279 /// that resulted from the splitting.
267280 MachineBasicBlock *DstOrSplit;
281
268282 /// P is used to update the analysis passes as applicable.
269283 Pass &P;
270284
285299 public:
286300 EdgeInsertPoint(MachineBasicBlock &Src, MachineBasicBlock &Dst, Pass &P)
287301 : InsertPoint(), Src(Src), DstOrSplit(&Dst), P(P) {}
302
288303 bool isSplit() const override {
289304 return Src.succ_size() > 1 && DstOrSplit->pred_size() > 1;
290305 }
306
291307 uint64_t frequency(const Pass &P) const override;
292308 bool canMaterialize() const override;
293309 };
310326
311327 /// \name Convenient types for a list of insertion points.
312328 /// @{
313 typedef SmallVector, 2> InsertionPoints;
314 typedef InsertionPoints::iterator insertpt_iterator;
315 typedef InsertionPoints::const_iterator const_insertpt_iterator;
329 using InsertionPoints = SmallVector, 2>;
330 using insertpt_iterator = InsertionPoints::iterator;
331 using const_insertpt_iterator = InsertionPoints::const_iterator;
316332 /// @}
317333
318334 private:
323339 /// Are all the insert points materializeable?
324340 bool CanMaterialize;
325341 /// Is there any of the insert points needing splitting?
326 bool HasSplit;
342 bool HasSplit = false;
327343 /// Insertion point for the repair code.
328344 /// The repairing code needs to happen just before these points.
329345 InsertionPoints InsertPoints;
406422 private:
407423 /// Cost of the local instructions.
408424 /// This cost is free of basic block frequency.
409 uint64_t LocalCost;
425 uint64_t LocalCost = 0;
410426 /// Cost of the non-local instructions.
411427 /// This cost should include the frequency of the related blocks.
412 uint64_t NonLocalCost;
428 uint64_t NonLocalCost = 0;
413429 /// Frequency of the block where the local instructions live.
414430 uint64_t LocalFreq;
415431
467483
468484 /// Interface to the target lowering info related
469485 /// to register banks.
470 const RegisterBankInfo *RBI;
486 const RegisterBankInfo *RBI = nullptr;
471487
472488 /// MRI contains all the register class/bank information that this
473489 /// pass uses and updates.
474 MachineRegisterInfo *MRI;
490 MachineRegisterInfo *MRI = nullptr;
475491
476492 /// Information on the register classes for the current function.
477 const TargetRegisterInfo *TRI;
493 const TargetRegisterInfo *TRI = nullptr;
478494
479495 /// Get the frequency of blocks.
480496 /// This is required for non-fast mode.
481 MachineBlockFrequencyInfo *MBFI;
497 MachineBlockFrequencyInfo *MBFI = nullptr;
482498
483499 /// Get the frequency of the edges.
484500 /// This is required for non-fast mode.
485 MachineBranchProbabilityInfo *MBPI;
501 MachineBranchProbabilityInfo *MBPI = nullptr;
486502
487503 /// Current optimization remark emitter. Used to report failures.
488504 std::unique_ptr MORE;
643659 bool runOnMachineFunction(MachineFunction &MF) override;
644660 };
645661
646 } // End namespace llvm.
647
648 #endif
662 } // end namespace llvm
663
664 #endif // LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H
None //==-- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ----------------*- C++ -*-==//
0 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ---------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H
15 #define LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H
16
17 #include "llvm/ADT/APInt.h"
14 #ifndef LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
15 #define LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
16
1817 #include "llvm/ADT/DenseMap.h"
1918 #include "llvm/ADT/Hashing.h"
2019 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
22 #include "llvm/CodeGen/MachineValueType.h" // For SimpleValueType.
20 #include "llvm/ADT/iterator_range.h"
2321 #include "llvm/Support/ErrorHandling.h"
24
2522 #include
26 #include <memory> // For unique_ptr.
23 #include <initializer_list>
24 #include
2725
2826 namespace llvm {
27
2928 class MachineInstr;
3029 class MachineRegisterInfo;
30 class raw_ostream;
31 class RegisterBank;
3132 class TargetInstrInfo;
33 class TargetRegisterClass;
3234 class TargetRegisterInfo;
33 class raw_ostream;
3435
3536 /// Holds all the information related to register banks.
3637 class RegisterBankInfo {
4748 /// original value. The bits are counted from less significant
4849 /// bits to most significant bits.
4950 unsigned StartIdx;
51
5052 /// Length of this mapping in bits. This is how many bits this
5153 /// partial mapping covers in the original value:
5254 /// from StartIdx to StartIdx + Length -1.
5355 unsigned Length;
56
5457 /// Register bank where the partial value lives.
5558 const RegisterBank *RegBank;
5659
179182 /// Identifier of the mapping.
180183 /// This is used to communicate between the target and the optimizers
181184 /// which mapping should be realized.
182 unsigned ID;
185 unsigned ID = InvalidMappingID;
186
183187 /// Cost of this mapping.
184 unsigned Cost;
188 unsigned Cost = 0;
189
185190 /// Mapping of all the operands.
186191 const ValueMapping *OperandsMapping;
192
187193 /// Number of operands.
188 unsigned NumOperands;
194 unsigned NumOperands = 0;
189195
190196 const ValueMapping &getOperandMapping(unsigned i) {
191197 assert(i < getNumOperands() && "Out of bound operand");
212218
213219 /// Default constructor.
214220 /// Use this constructor to express that the mapping is invalid.
215 InstructionMapping() : ID(InvalidMappingID), Cost(0), NumOperands(0) {}
221 InstructionMapping() = default;
216222
217223 /// Get the cost.
218224 unsigned getCost() const { return Cost; }
263269 /// Convenient type to represent the alternatives for mapping an
264270 /// instruction.
265271 /// \todo When we move to TableGen this should be an array ref.
266 typedef SmallVector InstructionMappings;
272 using InstructionMappings = SmallVector;
267273
268274 /// Helper class used to get/create the virtual registers that will be used
269275 /// to replace the MachineOperand when applying a mapping.
272278 /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
273279 /// Note: We use a SmallVector to avoid heap allocation for most cases.
274280 SmallVector OpToNewVRegIdx;
281
275282 /// Hold the registers that will be used to map MI with InstrMapping.
276283 SmallVector NewVRegs;
284
277285 /// Current MachineRegisterInfo, used to create new virtual registers.
278286 MachineRegisterInfo &MRI;
287
279288 /// Instruction being remapped.
280289 MachineInstr &MI;
290
281291 /// New mapping of the instruction.
282292 const InstructionMapping &InstrMapping;
283293
372382 protected:
373383 /// Hold the set of supported register banks.
374384 RegisterBank **RegBanks;
385
375386 /// Total number of register banks.
376387 unsigned NumRegBanks;
377388
728739 /// Hashing function for PartialMapping.
729740 /// It is required for the hashing of ValueMapping.
730741 hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
731 } // End namespace llvm.
732
733 #endif
742
743 } // end namespace llvm
744
745 #endif // LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
None //===-- llvm/CodeGen/GlobalISel/Types.h - Types used by GISel ----*- C++ -*-===//
0 //===- llvm/CodeGen/GlobalISel/Types.h - Types used by GISel ----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1515 #define LLVM_CODEGEN_GLOBALISEL_TYPES_H
1616
1717 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/IR/Value.h"
1918
2019 namespace llvm {
20
21 class Value;
2122
2223 /// Map a value to a virtual register.
2324 /// For now, we chose to map aggregate types to on single virtual
2526 /// PR26161 tracks that.
2627 /// Note: We need to expose this type to the target hooks for thing like
2728 /// ABI lowering that would be used during IRTranslation.
28 typedef DenseMap ValueToVReg;
29 using ValueToVReg = DenseMap;
2930
30 } // End namespace llvm.
31 #endif
31 } // end namespace llvm
32
33 #endif // LLVM_CODEGEN_GLOBALISEL_TYPES_H
None //===-- llvm/CodeGen/MachinePassRegistry.h ----------------------*- C++ -*-===//
0 //===- llvm/CodeGen/MachinePassRegistry.h -----------------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1717 #ifndef LLVM_CODEGEN_MACHINEPASSREGISTRY_H
1818 #define LLVM_CODEGEN_MACHINEPASSREGISTRY_H
1919
20 #include "llvm/ADT/StringRef.h"
2021 #include "llvm/CodeGen/Passes.h"
2122 #include "llvm/Support/CommandLine.h"
2223
2324 namespace llvm {
2425
25 typedef void *(*MachinePassCtor)();
26
26 using MachinePassCtor = void *(*)();
2727
2828 //===----------------------------------------------------------------------===//
2929 ///
3333 //===----------------------------------------------------------------------===//
3434 class MachinePassRegistryListener {
3535 virtual void anchor();
36
3637 public:
37 MachinePassRegistryListener() {}
38 virtual ~MachinePassRegistryListener() {}
38 MachinePassRegistryListener() = default;
39 virtual ~MachinePassRegistryListener() = default;
40
3941 virtual void NotifyAdd(StringRef N, MachinePassCtor C, StringRef D) = 0;
4042 virtual void NotifyRemove(StringRef N) = 0;
4143 };
42
4344
4445 //===----------------------------------------------------------------------===//
4546 ///
4748 ///
4849 //===----------------------------------------------------------------------===//
4950 class MachinePassRegistryNode {
50
5151 private:
52
53 MachinePassRegistryNode *Next; // Next function pass in list.
52 MachinePassRegistryNode *Next = nullptr; // Next function pass in list.
5453 StringRef Name; // Name of function pass.
5554 StringRef Description; // Description string.
5655 MachinePassCtor Ctor; // Function pass creator.
5756
5857 public:
59
6058 MachinePassRegistryNode(const char *N, const char *D, MachinePassCtor C)
61 : Next(nullptr)
62 , Name(N)
63 , Description(D)
64 , Ctor(C)
65 {}
59 : Name(N), Description(D), Ctor(C) {}
6660
6761 // Accessors
6862 MachinePassRegistryNode *getNext() const { return Next; }
7165 StringRef getDescription() const { return Description; }
7266 MachinePassCtor getCtor() const { return Ctor; }
7367 void setNext(MachinePassRegistryNode *N) { Next = N; }
74
7568 };
76
7769
7870 //===----------------------------------------------------------------------===//
7971 ///
8173 ///
8274 //===----------------------------------------------------------------------===//
8375 class MachinePassRegistry {
84
8576 private:
86
8777 MachinePassRegistryNode *List; // List of registry nodes.
8878 MachinePassCtor Default; // Default function pass creator.
89 MachinePassRegistryListener* Listener;// Listener for list adds are removes.
79 MachinePassRegistryListener *Listener; // Listener for list adds are removes.
9080
9181 public:
92
9382 // NO CONSTRUCTOR - we don't want static constructor ordering to mess
9483 // with the registry.
9584
10897 /// Remove - Removes a function pass from the registration list.
10998 ///
11099 void Remove(MachinePassRegistryNode *Node);
111
112100 };
113
114101
115102 //===----------------------------------------------------------------------===//
116103 ///
141128 }
142129
143130 // Implement the MachinePassRegistryListener callbacks.
144 //
145131 void NotifyAdd(StringRef N, MachinePassCtor C, StringRef D) override {
146132 this->addLiteralOption(N, (typename RegistryClass::FunctionPassCtor)C, D);
147133 }
150136 }
151137 };
152138
153
154139 } // end namespace llvm
155140
156 #endif
141 #endif // LLVM_CODEGEN_MACHINEPASSREGISTRY_H
1717 #include "llvm/ADT/iterator_range.h"
1818 #include "llvm/Support/ErrorHandling.h"
1919 #include "llvm/Support/MathExtras.h"
20 #include
2021
2122 namespace llvm {
2223
231232 Any = 255
232233 };
233234
234 SimpleValueType SimpleTy;
235
235 SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE;
236236
237237 // A class to represent the number of elements in a vector
238238 //
269269 }
270270 };
271271
272 constexpr MVT() : SimpleTy(INVALID_SIMPLE_VALUE_TYPE) {}
272 constexpr MVT() = default;
273273 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {}
274274
275275 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
779779 return getSizeInBits() <= VT.getSizeInBits();
780780 }
781781
782
783782 static MVT getFloatingPointVT(unsigned BitWidth) {
784783 switch (BitWidth) {
785784 default:
981980 /// A simple iterator over the MVT::SimpleValueType enum.
982981 struct mvt_iterator {
983982 SimpleValueType VT;
983
984984 mvt_iterator(SimpleValueType VT) : VT(VT) {}
985
985986 MVT operator*() const { return VT; }
986987 bool operator!=(const mvt_iterator &LHS) const { return VT != LHS.VT; }
988
987989 mvt_iterator& operator++() {
988990 VT = (MVT::SimpleValueType)((int)VT + 1);
989991 assert((int)VT <= MVT::MAX_ALLOWED_VALUETYPE &&
991993 return *this;
992994 }
993995 };
996
994997 /// A range of the MVT::SimpleValueType enum.
995 typedef iterator_range mvt_range;
998 using mvt_range = iterator_range;
996999
9971000 public:
9981001 /// SimpleValueType Iteration
10001003 static mvt_range all_valuetypes() {
10011004 return mvt_range(MVT::FIRST_VALUETYPE, MVT::LAST_VALUETYPE);
10021005 }
1006
10031007 static mvt_range integer_valuetypes() {
10041008 return mvt_range(MVT::FIRST_INTEGER_VALUETYPE,
10051009 (MVT::SimpleValueType)(MVT::LAST_INTEGER_VALUETYPE + 1));
10061010 }
1011
10071012 static mvt_range fp_valuetypes() {
10081013 return mvt_range(MVT::FIRST_FP_VALUETYPE,
10091014 (MVT::SimpleValueType)(MVT::LAST_FP_VALUETYPE + 1));
10101015 }
1016
10111017 static mvt_range vector_valuetypes() {
10121018 return mvt_range(MVT::FIRST_VECTOR_VALUETYPE,
10131019 (MVT::SimpleValueType)(MVT::LAST_VECTOR_VALUETYPE + 1));
10141020 }
1021
10151022 static mvt_range integer_vector_valuetypes() {
10161023 return mvt_range(
10171024 MVT::FIRST_INTEGER_VECTOR_VALUETYPE,
10181025 (MVT::SimpleValueType)(MVT::LAST_INTEGER_VECTOR_VALUETYPE + 1));
10191026 }
1027
10201028 static mvt_range fp_vector_valuetypes() {
10211029 return mvt_range(
10221030 MVT::FIRST_FP_VECTOR_VALUETYPE,
10231031 (MVT::SimpleValueType)(MVT::LAST_FP_VECTOR_VALUETYPE + 1));
10241032 }
1033
10251034 static mvt_range integer_scalable_vector_valuetypes() {
10261035 return mvt_range(MVT::FIRST_INTEGER_SCALABLE_VALUETYPE,
10271036 (MVT::SimpleValueType)(MVT::LAST_INTEGER_SCALABLE_VALUETYPE + 1));
10281037 }
1038
10291039 static mvt_range fp_scalable_vector_valuetypes() {
10301040 return mvt_range(MVT::FIRST_FP_SCALABLE_VALUETYPE,
10311041 (MVT::SimpleValueType)(MVT::LAST_FP_SCALABLE_VALUETYPE + 1));
10331043 /// @}
10341044 };
10351045
1036 } // End llvm namespace
1037
1038 #endif
1046 } // end namespace llvm
1047
1048 #endif // LLVM_CODEGEN_MACHINEVALUETYPE_H
None //===- MacroFusion.h - Macro Fusion ------------------------===//
0 //===- MacroFusion.h - Macro Fusion -----------------------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_CODEGEN_MACROFUSION_H
15 #define LLVM_CODEGEN_MACROFUSION_H
16
1417 #include
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/CodeGen/MachineScheduler.h"
18 #include
1719
1820 namespace llvm {
21
22 class MachineInstr;
23 class ScheduleDAGMutation;
24 class TargetInstrInfo;
25 class TargetSubtargetInfo;
1926
2027 /// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
2128 /// together. Given SecondMI, when FirstMI is unspecified, then check if
2229 /// SecondMI may be part of a fused pair at all.
23 typedef std::function
24 const TargetSubtargetInfo &TSI,
25 const MachineInstr *FirstMI,
26 const MachineInstr &SecondMI)> ShouldSchedulePredTy;
30 using ShouldSchedulePredTy = std::function
31 const TargetSubtargetInfo &TSI,
32 const MachineInstr *FirstMI,
33 const MachineInstr &SecondMI)>;
2734
2835 /// \brief Create a DAG scheduling mutation to pair instructions back to back
2936 /// for instructions that benefit according to the target-specific
3845 createBranchMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
3946
4047 } // end namespace llvm
48
49 #endif // LLVM_CODEGEN_MACROFUSION_H
None //===-- TargetPassConfig.h - Code Generation pass options -------*- C++ -*-===//
0 //===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1515
1616 #include "llvm/Pass.h"
1717 #include "llvm/Support/CodeGen.h"
18 #include
1819 #include
1920
2021 namespace llvm {
2122
23 class LLVMTargetMachine;
24 struct MachineSchedContext;
2225 class PassConfigImpl;
2326 class ScheduleDAGInstrs;
24 class LLVMTargetMachine;
25 struct MachineSchedContext;
2627
2728 // The old pass manager infrastructure is hidden in a legacy namespace now.
2829 namespace legacy {
30
2931 class PassManagerBase;
30 }
32
33 } // end namespace legacy
34
3135 using legacy::PassManagerBase;
3236
3337 /// Discriminated union of Pass ID types.
4953 AnalysisID ID;
5054 Pass *P;
5155 };
52 bool IsInstance;
56 bool IsInstance = false;
57
5358 public:
54 IdentifyingPassPtr() : P(nullptr), IsInstance(false) {}
55 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
59 IdentifyingPassPtr() : P(nullptr) {}
60 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
5661 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
5762
5863 bool isValid() const { return P; }
6267 assert(!IsInstance && "Not a Pass ID");
6368 return ID;
6469 }
70
6571 Pass *getInstance() const {
6672 assert(IsInstance && "Not a Pass Instance");
6773 return P;
9298 static char PostRAMachineLICMID;
9399
94100 private:
95 PassManagerBase *PM;
101 PassManagerBase *PM = nullptr;
96102 AnalysisID StartBefore = nullptr;
97103 AnalysisID StartAfter = nullptr;
98104 AnalysisID StopBefore = nullptr;
99105 AnalysisID StopAfter = nullptr;
100 bool Started;
101 bool Stopped;
102 bool AddingMachinePasses;
106 bool Started = true;
107 bool Stopped = false;
108 bool AddingMachinePasses = false;
103109
104110 protected:
105111 LLVMTargetMachine *TM;
106 PassConfigImpl *Impl; // Internal data structures
107 bool Initialized; // Flagged after all passes are configured.
112 PassConfigImpl *Impl = nullptr; // Internal data structures
113 bool Initialized = false; // Flagged after all passes are configured.
108114
109115 // Target Pass Options
110116 // Targets provide a default setting, user flags override.
111 //
112 bool DisableVerify;
117 bool DisableVerify = false;
113118
114119 /// Default setting for -enable-tail-merge on this target.
115 bool EnableTailMerge;
120 bool EnableTailMerge = true;
116121
117122 /// Require processing of functions such that callees are generated before
118123 /// callers.
119 bool RequireCodeGenSCCOrder;
124 bool RequireCodeGenSCCOrder = false;
120125
121126 /// Add the actual instruction selection passes. This does not include
122127 /// preparation passes on IR.
295300
296301 /// printAndVerify - Add a pass to dump then verify the machine function, if
297302 /// those steps are enabled.
298 ///
299303 void printAndVerify(const std::string &Banner);
300304
301305 /// Add a pass to print the machine function if printing is enabled.
429433
430434 } // end namespace llvm
431435
432 #endif
436 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H
1616 #define LLVM_CODEGEN_VALUETYPES_H
1717
1818 #include "llvm/CodeGen/MachineValueType.h"
19 #include "llvm/Support/Compiler.h"
20 #include "llvm/Support/MathExtras.h"
1921 #include
22 #include
2023 #include
2124
2225 namespace llvm {
2932 /// can represent.
3033 struct EVT {
3134 private:
32 MVT V;
33 Type *LLVMTy;
35 MVT V = MVT::INVALID_SIMPLE_VALUE_TYPE;
36 Type *LLVMTy = nullptr;
3437
3538 public:
36 constexpr EVT() : V(MVT::INVALID_SIMPLE_VALUE_TYPE), LLVMTy(nullptr) {}
37 constexpr EVT(MVT::SimpleValueType SVT) : V(SVT), LLVMTy(nullptr) {}
38 constexpr EVT(MVT S) : V(S), LLVMTy(nullptr) {}
39 constexpr EVT() = default;
40 constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {}
41 constexpr EVT(MVT S) : V(S) {}
3942
4043 bool operator==(EVT VT) const {
4144 return !(*this != VT);
244247 if (EVT::operator==(VT)) return true;
245248 return getSizeInBits() <= VT.getSizeInBits();
246249 }
247
248250
249251 /// Return the SimpleValueType held in the specified simple EVT.
250252 MVT getSimpleVT() const {
429431 unsigned getExtendedSizeInBits() const LLVM_READONLY;
430432 };
431433
432 } // End llvm namespace
433
434 #endif
434 } // end namespace llvm
435
436 #endif // LLVM_CODEGEN_VALUETYPES_H
None //===-- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator --*- C++ -*-==//
0 //===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1010 //===----------------------------------------------------------------------===//
1111
1212 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
13
13 #include "llvm/ADT/STLExtras.h"
1414 #include "llvm/ADT/ScopeExit.h"
1515 #include "llvm/ADT/SmallSet.h"
1616 #include "llvm/ADT/SmallVector.h"
1717 #include "llvm/Analysis/OptimizationDiagnosticInfo.h"
1818 #include "llvm/CodeGen/Analysis.h"
1919 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
20 #include "llvm/CodeGen/LowLevelType.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
2022 #include "llvm/CodeGen/MachineFrameInfo.h"
2123 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/MachineOperand.h"
2327 #include "llvm/CodeGen/MachineRegisterInfo.h"
2428 #include "llvm/CodeGen/TargetPassConfig.h"
29 #include "llvm/IR/BasicBlock.h"
2530 #include "llvm/IR/Constant.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DataLayout.h"
2633 #include "llvm/IR/DebugInfo.h"
34 #include "llvm/IR/DerivedTypes.h"
2735 #include "llvm/IR/Function.h"
2836 #include "llvm/IR/GetElementPtrTypeIterator.h"
37 #include "llvm/IR/InlineAsm.h"
38 #include "llvm/IR/InstrTypes.h"
39 #include "llvm/IR/Instructions.h"
2940 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Metadata.h"
3044 #include "llvm/IR/Type.h"
45 #include "llvm/IR/User.h"
3146 #include "llvm/IR/Value.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/Pass.h"
49 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/CodeGen.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/LowLevelTypeImpl.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Support/raw_ostream.h"
3256 #include "llvm/Target/TargetFrameLowering.h"
3357 #include "llvm/Target/TargetIntrinsicInfo.h"
3458 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetMachine.h"
60 #include "llvm/Target/TargetRegisterInfo.h"
61 #include "llvm/Target/TargetSubtargetInfo.h"
62 #include
63 #include
64 #include
65 #include
66 #include
67 #include
68 #include
3569
3670 #define DEBUG_TYPE "irtranslator"
3771
3872 using namespace llvm;
3973
4074 char IRTranslator::ID = 0;
75
4176 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
4277 false, false)
4378 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
6196 ORE.emit(R);
6297 }
6398
64 IRTranslator::IRTranslator() : MachineFunctionPass(ID), MRI(nullptr) {
99 IRTranslator::IRTranslator() : MachineFunctionPass(ID) {
65100 initializeIRTranslatorPass(*PassRegistry::getPassRegistry());
66101 }
67102
69104 AU.addRequired();
70105 MachineFunctionPass::getAnalysisUsage(AU);
71106 }
72
73107
74108 unsigned IRTranslator::getOrCreateVReg(const Value &Val) {
75109 unsigned &ValReg = ValToVReg[&Val];
832866 // FIXME: support Windows exception handling.
833867 if (!isa(EHPadBB->front()))
834868 return false;
835
836869
837870 // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
838871 // the region covered by the try.
11941227 MRI = &MF->getRegInfo();
11951228 DL = &F.getParent()->getDataLayout();
11961229 TPC = &getAnalysis();
1197 ORE = make_unique(&F);
1230 ORE = llvm::make_unique(&F);
11981231
11991232 assert(PendingPHIs.empty() && "stale PHIs");
12001233
None //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp -----------*- C++ -*-==//
0 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1010 //===----------------------------------------------------------------------===//
1111
1212 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
13 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
1413 #include "llvm/CodeGen/GlobalISel/Utils.h"
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/CodeGen/MachineFunction.h"
1516 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 #include "llvm/IR/Constants.h"
18 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/CodeGen/MachineOperand.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/raw_ostream.h"
1921 #include "llvm/Target/TargetRegisterInfo.h"
22 #include
2023
2124 #define DEBUG_TYPE "instructionselector"
2225
2326 using namespace llvm;
2427
25 InstructionSelector::InstructionSelector() {}
28 InstructionSelector::InstructionSelector() = default;
2629
2730 bool InstructionSelector::constrainOperandRegToRegClass(
2831 MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
3235 MachineFunction &MF = *MBB.getParent();
3336 MachineRegisterInfo &MRI = MF.getRegInfo();
3437
35 return llvm::constrainRegToClass(MRI, TII, RBI, I,
36 I.getOperand(OpIdx).getReg(), RC);
38 return
39 constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC);
3740 }
3841
3942 bool InstructionSelector::constrainSelectedInstRegOperands(
8386 bool InstructionSelector::isOperandImmEqual(
8487 const MachineOperand &MO, int64_t Value,
8588 const MachineRegisterInfo &MRI) const {
86
8789 if (MO.isReg() && MO.getReg())
8890 if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
8991 return *VRegVal == Value;
None //===---- lib/CodeGen/GlobalISel/LegalizerInfo.cpp - Legalizer -------==//
0 //===- lib/CodeGen/GlobalISel/LegalizerInfo.cpp - Legalizer ---------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1717 //===----------------------------------------------------------------------===//
1818
1919 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
20
2120 #include "llvm/ADT/SmallBitVector.h"
2221 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineOperand.h"
2323 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/IR/Type.h"
24 #include "llvm/MC/MCInstrDesc.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/LowLevelTypeImpl.h"
27 #include "llvm/Support/MathExtras.h"
2628 #include "llvm/Target/TargetOpcodes.h"
29 #include
30 #include
31 #include
32 #include
33
2734 using namespace llvm;
2835
29 LegalizerInfo::LegalizerInfo() : TablesInitialized(false) {
36 LegalizerInfo::LegalizerInfo() {
3037 // FIXME: these two can be legalized to the fundamental load/store Jakob
3138 // proposed. Once loads & stores are supported.
3239 DefaultActions[TargetOpcode::G_ANYEXT] = Legal;
170177 case Libcall:
171178 case Custom:
172179 return Aspect.Type;
173 case NarrowScalar: {
180 case NarrowScalar:
174181 return findLegalType(Aspect,
175182 [](LLT Ty) -> LLT { return Ty.halfScalarSize(); });
176 }
177 case WidenScalar: {
183 case WidenScalar:
178184 return findLegalType(Aspect, [](LLT Ty) -> LLT {
179185 return Ty.getSizeInBits() < 8 ? LLT::scalar(8) : Ty.doubleScalarSize();
180186 });
181 }
182 case FewerElements: {
187 case FewerElements:
183188 return findLegalType(Aspect,
184189 [](LLT Ty) -> LLT { return Ty.halfElements(); });
185 }
186 case MoreElements: {
190 case MoreElements:
187191 return findLegalType(Aspect,
188192 [](LLT Ty) -> LLT { return Ty.doubleElements(); });
189 }
190193 }
191194 }
192195
None //===- llvm/CodeGen/GlobalISel/RegBankSelect.cpp - RegBankSelect -*- C++ -*-==//
0 //==- llvm/CodeGen/GlobalISel/RegBankSelect.cpp - RegBankSelect --*- C++ -*-==//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1111
1212 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
1313 #include "llvm/ADT/PostOrderIterator.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
1416 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
1517 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
18 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
1619 #include "llvm/CodeGen/GlobalISel/Utils.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
1721 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
1822 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineOperand.h"
26 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
1927 #include "llvm/CodeGen/MachineRegisterInfo.h"
2028 #include "llvm/CodeGen/TargetPassConfig.h"
2129 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/Pass.h"
2232 #include "llvm/Support/BlockFrequency.h"
2333 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
2435 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOpcodes.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
2540 #include "llvm/Target/TargetSubtargetInfo.h"
41 #include
42 #include
43 #include
44 #include
45 #include
46 #include
2647
2748 #define DEBUG_TYPE "regbankselect"
2849
3657 "Use the Greedy mode (best local mapping)")));
3758
3859 char RegBankSelect::ID = 0;
60
3961 INITIALIZE_PASS_BEGIN(RegBankSelect, DEBUG_TYPE,
4062 "Assign register bank of generic virtual registers",
4163 false, false);
4769 false)
4870
4971 RegBankSelect::RegBankSelect(Mode RunningMode)
50 : MachineFunctionPass(ID), RBI(nullptr), MRI(nullptr), TRI(nullptr),
51 MBFI(nullptr), MBPI(nullptr), OptMode(RunningMode) {
72 : MachineFunctionPass(ID), OptMode(RunningMode) {
5273 initializeRegBankSelectPass(*PassRegistry::getPassRegistry());
5374 if (RegBankSelectMode.getNumOccurrences() != 0) {
5475 OptMode = RegBankSelectMode;
7192 MBPI = nullptr;
7293 }
7394 MIRBuilder.setMF(MF);
74 MORE = make_unique(MF, MBFI);
95 MORE = llvm::make_unique(MF, MBFI);
7596 }
7697
7798 void RegBankSelect::getAnalysisUsage(AnalysisUsage &AU) const {
201222 RBI->copyCost(*DesiredRegBrank, *CurRegBank,
202223 RegisterBankInfo::getSizeInBits(MO.getReg(), *MRI, *TRI));
203224 // TODO: use a dedicated constant for ImpossibleCost.
204 if (Cost != UINT_MAX)
225 if (Cost != std::numeric_limits::max())
205226 return Cost;
206227 // Return the legalization cost of that repairing.
207228 }
208 return UINT_MAX;
229 return std::numeric_limits::max();
209230 }
210231
211232 const RegisterBankInfo::InstructionMapping &RegBankSelect::findBestMapping(
351372 // the repairing cost because of the PHIs already proceeded
352373 // as already stated.
353374 // Though the code will be correct.
354 assert(0 && "Repairing cost may not be accurate");
375 assert(false && "Repairing cost may not be accurate");
355376 } else {
356377 // We need to do non-local repairing. Basically, patch all
357378 // the uses (i.e., phis) that we already proceeded.
449470 uint64_t RepairCost = getRepairCost(MO, ValMapping);
450471
451472 // This is an impossible to repair cost.
452 if (RepairCost == UINT_MAX)
473 if (RepairCost == std::numeric_limits::max())
453474 continue;
454475
455476 // Bias used for splitting: 5%.
637658 MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P,
638659 RepairingPlacement::RepairingKind Kind)
639660 // Default is, we are going to insert code to repair OpIdx.
640 : Kind(Kind),
641 OpIdx(OpIdx),
642 CanMaterialize(Kind != RepairingKind::Impossible),
643 HasSplit(false),
644 P(P) {
661 : Kind(Kind), OpIdx(OpIdx),
662 CanMaterialize(Kind != RepairingKind::Impossible), P(P) {
645663 const MachineOperand &MO = MI.getOperand(OpIdx);
646664 assert(MO.isReg() && "Trying to repair a non-reg operand");
647665
846864 }
847865
848866 RegBankSelect::MappingCost::MappingCost(const BlockFrequency &LocalFreq)
849 : LocalCost(0), NonLocalCost(0), LocalFreq(LocalFreq.getFrequency()) {}
867 : LocalFreq(LocalFreq.getFrequency()) {}
850868
851869 bool RegBankSelect::MappingCost::addLocalCost(uint64_t Cost) {
852870 // Check if this overflows.
919937 OtherLocalAdjust = Cost.LocalCost - LocalCost;
920938 else
921939 ThisLocalAdjust = LocalCost - Cost.LocalCost;
922
923940 } else {
924941 ThisLocalAdjust = LocalCost;
925942 OtherLocalAdjust = Cost.LocalCost;
None //===- MacroFusion.cpp - Macro Fusion ----------------------===//
0 //===- MacroFusion.cpp - Macro Fusion -------------------------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1212 //===----------------------------------------------------------------------===//
1313
1414 #include "llvm/CodeGen/MacroFusion.h"
15 #include "llvm/ADT/STLExtras.h"
1516 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/CodeGen/ScheduleDAG.h"
20 #include "llvm/CodeGen/ScheduleDAGMutation.h"
1621 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
1724 #include "llvm/Target/TargetInstrInfo.h"
1825
1926 #define DEBUG_TYPE "misched"
2431
2532 static cl::opt EnableMacroFusion("misched-fusion", cl::Hidden,
2633 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
27
28 namespace {
2934
3035 static void fuseInstructionPair(ScheduleDAGMI &DAG, SUnit &FirstSU,
3136 SUnit &SecondSU) {
6570 ++NumFused;
6671 }
6772
73 namespace {
6874
6975 /// \brief Post-process the DAG to create cluster edges between instrs that may
7076 /// be fused by the processor into a single operation.
7985
8086 void apply(ScheduleDAGInstrs *DAGInstrs) override;
8187 };
88
89 } // end anonymous namespace
8290
8391 void MacroFusion::apply(ScheduleDAGInstrs *DAGInstrs) {
8492 ScheduleDAGMI *DAG = static_cast(DAGInstrs);
127135 return false;
128136 }
129137
130 } // end anonymous namespace
131
132
133 namespace llvm {
134
135138 std::unique_ptr
136 createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent) {
139 llvm::createMacroFusionDAGMutation(
140 ShouldSchedulePredTy shouldScheduleAdjacent) {
137141 if(EnableMacroFusion)
138142 return llvm::make_unique(shouldScheduleAdjacent, true);
139143 return nullptr;
140144 }
141145
142146 std::unique_ptr
143 createBranchMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent) {
147 llvm::createBranchMacroFusionDAGMutation(
148 ShouldSchedulePredTy shouldScheduleAdjacent) {
144149 if(EnableMacroFusion)
145150 return llvm::make_unique(shouldScheduleAdjacent, false);
146151 return nullptr;
147152 }
148
149 } // end namespace llvm
None //===-- TargetPassConfig.cpp - Target independent code generation passes --===//
0 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1212 //===---------------------------------------------------------------------===//
1313
1414 #include "llvm/CodeGen/TargetPassConfig.h"
15
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
1618 #include "llvm/Analysis/BasicAliasAnalysis.h"
1719 #include "llvm/Analysis/CFLAndersAliasAnalysis.h"
1820 #include "llvm/Analysis/CFLSteensAliasAnalysis.h"
1921 #include "llvm/Analysis/CallGraphSCCPass.h"
20 #include "llvm/Analysis/Passes.h"
2122 #include "llvm/Analysis/ScopedNoAliasAA.h"
2223 #include "llvm/Analysis/TargetTransformInfo.h"
2324 #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
2425 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachinePassRegistry.h"
27 #include "llvm/CodeGen/Passes.h"
2528 #include "llvm/CodeGen/RegAllocRegistry.h"
26 #include "llvm/CodeGen/RegisterUsageInfo.h"
2729 #include "llvm/IR/IRPrintingPasses.h"
2830 #include "llvm/IR/LegacyPassManager.h"
2931 #include "llvm/IR/Verifier.h"
3032 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCTargetOptions.h"
34 #include "llvm/Pass.h"
35 #include "llvm/Support/CodeGen.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Compiler.h"
3138 #include "llvm/Support/Debug.h"
3239 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Support/Threading.h"
3441 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Transforms/Instrumentation.h"
3642 #include "llvm/Transforms/Scalar.h"
3743 #include "llvm/Transforms/Utils/SymbolRewriter.h"
44 #include
45 #include
3846
3947 using namespace llvm;
4048
224232 char TargetPassConfig::PostRAMachineLICMID = 0;
225233
226234 namespace {
235
227236 struct InsertedPass {
228237 AnalysisID TargetPassID;
229238 IdentifyingPassPtr InsertedPassID;
244253 return NP;
245254 }
246255 };
247 }
256
257 } // end anonymous namespace
248258
249259 namespace llvm {
260
250261 class PassConfigImpl {
251262 public:
252263 // List of passes explicitly substituted by this target. Normally this is
262273 /// is inserted after each instance of the first one.
263274 SmallVector InsertedPasses;
264275 };
265 } // namespace llvm
276
277 } // end namespace llvm
266278
267279 // Out of line virtual method.
268280 TargetPassConfig::~TargetPassConfig() {
272284 // Out of line constructor provides default values for pass options and
273285 // registers all common codegen passes.
274286 TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
275 : ImmutablePass(ID), PM(&pm), Started(true), Stopped(false),
276 AddingMachinePasses(false), TM(&TM), Impl(nullptr), Initialized(false),
277 DisableVerify(false), EnableTailMerge(true),
278 RequireCodeGenSCCOrder(false) {
279
287 : ImmutablePass(ID), PM(&pm), TM(&TM) {
280288 Impl = new PassConfigImpl();
281289
282290 // Register all target independent codegen passes to activate their PassIDs,
324332 }
325333
326334 TargetPassConfig::TargetPassConfig()
327 : ImmutablePass(ID), PM(nullptr) {
335 : ImmutablePass(ID) {
328336 report_fatal_error("Trying to construct TargetPassConfig without a target "
329337 "machine. Scheduling a CodeGen pass without a target "
330338 "triple set?");