llvm.org GIT mirror llvm / e9e97c8
[ARM] Tidy up ARMBaseRegisterInfo implementation. NFC Clean up ARMBaseRegisterInfo implementation a bit. Differential Revision: https://reviews.llvm.org/D35116 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307531 91177308-0d34-0410-b5e6-96231b3b80d8 Javed Absar 3 years ago
1 changed file(s) with 8 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
192192 for (unsigned R = 0; R < 16; ++R)
193193 markSuperRegs(Reserved, ARM::D16 + R);
194194 }
195 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
196 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
197 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
198 if (Reserved.test(*SI)) markSuperRegs(Reserved, *I);
195 const TargetRegisterClass &RC = ARM::GPRPairRegClass;
196 for (unsigned Reg : RC)
197 for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
198 if (Reserved.test(*SI))
199 markSuperRegs(Reserved, Reg);
199200
200201 assert(checkAllSuperRegsMarked(Reserved));
201202 return Reserved;
314315 Hints.push_back(PairedPhys);
315316
316317 // Then prefer even or odd registers.
317 for (unsigned I = 0, E = Order.size(); I != E; ++I) {
318 unsigned Reg = Order[I];
318 for (unsigned Reg : Order) {
319319 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
320320 continue;
321321 // Don't provide hints that are paired to a reserved register.
658658 const MCInstrDesc &Desc = MI->getDesc();
659659 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
660660 unsigned i = 0;
661
662 while (!MI->getOperand(i).isFI()) {
663 ++i;
664 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
665 }
661 for (; !MI->getOperand(i).isFI(); ++i)
662 assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
666663
667664 // AddrMode4 and AddrMode6 cannot handle any offset.
668665 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)