llvm.org GIT mirror llvm / e9a7ea6
Keep track of incoming argument's location while emitting LiveIns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8 Devang Patel 9 years ago
13 changed file(s) with 144 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
280280
281281 /// addLiveIn - Add the specified physical register as a live-in value and
282282 /// create a corresponding virtual register for it.
283 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
283 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC, DebugLoc DL);
284284
285285 //===--------------------------------------------------------------------===//
286286 // BasicBlock accessor functions.
1616 #include "llvm/Target/TargetRegisterInfo.h"
1717 #include "llvm/ADT/BitVector.h"
1818 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/DebugLoc.h"
1921 #include
2022
2123 namespace llvm {
6365 /// stored in the second element.
6466 std::vector > LiveIns;
6567 std::vector LiveOuts;
66
68
69 /// LiveInLocs - Keep track of location livein registers.
70 DenseMap LiveInLocs;
71
6772 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
6873 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
6974 public:
270275 LiveIns.push_back(std::make_pair(Reg, vreg));
271276 }
272277 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
273
278
279 /// addLiveInLoc - Keep track of location info for live in reg.
280 void addLiveInLoc(unsigned VReg, DebugLoc DL) {
281 LiveInLocs[VReg] = DL;
282 }
283
274284 // Iteration support for live in/out sets. These sets are kept in sorted
275285 // order by their register number.
276286 typedef std::vector >::const_iterator
395395 /// addLiveIn - Add the specified physical register as a live-in value and
396396 /// create a corresponding virtual register for it.
397397 unsigned MachineFunction::addLiveIn(unsigned PReg,
398 const TargetRegisterClass *RC) {
398 const TargetRegisterClass *RC,
399 DebugLoc DL) {
399400 MachineRegisterInfo &MRI = getRegInfo();
400401 unsigned VReg = MRI.getLiveInVirtReg(PReg);
401402 if (VReg) {
404405 }
405406 VReg = MRI.createVirtualRegister(RC);
406407 MRI.addLiveIn(PReg, VReg);
408 MRI.addLiveInLoc(VReg, DL);
407409 return VReg;
408410 }
409411
209209 LiveIns.erase(LiveIns.begin() + i);
210210 --i; --e;
211211 } else {
212 DebugLoc DL;
213 // If there is a location for this live in then use it.
214 DenseMap::iterator DLI =
215 LiveInLocs.find(LiveIns[i].second);
216 if (DLI != LiveInLocs.end())
217 DL = DLI->second;
218
212219 // Emit a copy.
213 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
220 BuildMI(*EntryMBB, EntryMBB->begin(), DL,
214221 TII.get(TargetOpcode::COPY), LiveIns[i].second)
215222 .addReg(LiveIns[i].first);
216223
347347 SDValue getControlRoot();
348348
349349 DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
350
350 void setCurDebugLoc(DebugLoc dl){ CurDebugLoc = dl; }
351351 unsigned getSDNodeOrder() const { return SDNodeOrder; }
352352
353353 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
850850 PrepareEHLandingPad();
851851
852852 // Lower any arguments needed in this block if this is the entry block.
853 if (LLVMBB == &Fn.getEntryBlock())
853 if (LLVMBB == &Fn.getEntryBlock()) {
854 for (BasicBlock::const_iterator DBI = LLVMBB->begin(), DBE = LLVMBB->end();
855 DBI != DBE; ++DBI) {
856 if (const DbgInfoIntrinsic *DI = dyn_cast(DBI)) {
857 const DebugLoc DL = DI->getDebugLoc();
858 SDB->setCurDebugLoc(DL);
859 break;
860 }
861 }
854862 LowerArguments(LLVMBB);
863 }
855864
856865 // Before doing SelectionDAG ISel, see if FastISel has been requested.
857866 if (FastIS) {
22112211 RC = ARM::GPRRegisterClass;
22122212
22132213 // Transform the arguments stored in physical registers into virtual ones.
2214 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2214 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC, dl);
22152215 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
22162216
22172217 SDValue ArgValue2;
22252225 MachinePointerInfo::getFixedStack(FI),
22262226 false, false, 0);
22272227 } else {
2228 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2228 Reg = MF.addLiveIn(NextVA.getLocReg(), RC, dl);
22292229 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
22302230 }
22312231
23062306 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
23072307
23082308 // Transform the arguments in physical registers into virtual ones.
2309 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2309 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC, dl);
23102310 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
23112311 }
23122312
23832383 else
23842384 RC = ARM::GPRRegisterClass;
23852385
2386 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2386 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC, dl);
23872387 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
23882388 SDValue Store =
23892389 DAG.getStore(Val.getValue(1), dl, Val, FIN,
28382838 }
28392839
28402840 // Return LR, which contains the return address. Mark it an implicit live-in.
2841 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2841 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32), dl);
28422842 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
28432843 }
28442844
12181218 FuncInfo->setVarArgsFrameIndex(
12191219 MFI->CreateFixedObject(StackSlotSize, ArgOffset, true));
12201220 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1221 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass);
1221 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass, dl);
12221222 SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
12231223 SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, MachinePointerInfo(),
12241224 false, false, 0);
906906
907907 // Transform the arguments stored on
908908 // physical registers into virtual ones
909 unsigned Reg = MF.addLiveIn(ArgRegEnd, RC);
909 unsigned Reg = MF.addLiveIn(ArgRegEnd, RC, dl);
910910 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
911911
912912 // If this is an 8 or 16-bit value, it has been passed promoted
972972
973973 for (; Start <= End; ++Start, ++StackLoc) {
974974 unsigned Reg = MBlazeRegisterInfo::getRegisterFromNumbering(Start);
975 unsigned LiveReg = MF.addLiveIn(Reg, RC);
975 unsigned LiveReg = MF.addLiveIn(Reg, RC, dl);
976976 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32);
977977
978978 int FI = MFI->CreateFixedObject(4, 0, true);
15961596 }
15971597
15981598 // Transform the arguments stored in physical registers into virtual ones.
1599 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1599 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC, dl);
16001600 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
16011601
16021602 InVals.push_back(ArgValue);
16881688 // Get an existing live-in vreg, or add a new one.
16891689 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
16901690 if (!VReg)
1691 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1691 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass, dl);
16921692
16931693 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
16941694 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
17071707 // Get an existing live-in vreg, or add a new one.
17081708 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
17091709 if (!VReg)
1710 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1710 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass, dl);
17111711
17121712 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
17131713 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
18711871 InVals.push_back(FIN);
18721872 if (ObjSize==1 || ObjSize==2) {
18731873 if (GPR_idx != Num_GPR_Regs) {
1874 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1874 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass, dl);
18751875 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
18761876 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
18771877 MachinePointerInfo(),
18901890 // to memory. ArgVal will be address of the beginning of
18911891 // the object.
18921892 if (GPR_idx != Num_GPR_Regs) {
1893 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1893 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass, dl);
18941894 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
18951895 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
18961896 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
19131913 case MVT::i32:
19141914 if (!isPPC64) {
19151915 if (GPR_idx != Num_GPR_Regs) {
1916 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1916 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass, dl);
19171917 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
19181918 ++GPR_idx;
19191919 } else {
19271927 // FALLTHROUGH
19281928 case MVT::i64: // PPC64
19291929 if (GPR_idx != Num_GPR_Regs) {
1930 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1930 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass, dl);
19311931 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
19321932
19331933 if (ObjectVT == MVT::i32) {
19651965 unsigned VReg;
19661966
19671967 if (ObjectVT == MVT::f32)
1968 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1968 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass, dl);
19691969 else
1970 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1970 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass, dl);
19711971
19721972 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
19731973 ++FPR_idx;
19851985 // Note that vector arguments in registers don't reserve stack space,
19861986 // except in varargs functions.
19871987 if (VR_idx != Num_VR_Regs) {
1988 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
1988 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass, dl);
19891989 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
19901990 if (isVarArg) {
19911991 while ((ArgOffset % 16) != 0) {
20632063 unsigned VReg;
20642064
20652065 if (isPPC64)
2066 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2066 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass, dl);
20672067 else
2068 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2068 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass, dl);
20692069
20702070 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
20712071 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
193193 false, false, 0);
194194 } else {
195195 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
196 &SP::IntRegsRegClass);
196 &SP::IntRegsRegClass, dl);
197197 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
198198 }
199199 SDValue WholeValue =
15751575 else
15761576 llvm_unreachable("Unknown argument type!");
15771577
1578 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1578 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC, dl);
15791579 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
15801580
15811581 // If this is an 8 or 16-bit value, it is really passed promoted to 32
17071707 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
17081708 DAG.getIntPtrConstant(Offset));
17091709 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1710 X86::GR64RegisterClass);
1710 X86::GR64RegisterClass, dl);
17111711 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
17121712 SDValue Store =
17131713 DAG.getStore(Val.getValue(1), dl, Val, FIN,
17231723 SmallVector SaveXMMOps;
17241724 SaveXMMOps.push_back(Chain);
17251725
1726 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1726 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass, dl);
17271727 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
17281728 SaveXMMOps.push_back(ALVal);
17291729
17341734
17351735 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
17361736 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1737 X86::VR128RegisterClass);
1737 X86::VR128RegisterClass, dl);
17381738 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
17391739 SaveXMMOps.push_back(Val);
17401740 }
0 ; RUN: llc < %s | FileCheck %s
1 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
2 target triple = "x86_64-apple-darwin10.0.0"
3
4 @str = internal constant [3 x i8] c"Hi\00"
5
6 define void @foo() nounwind ssp {
7 entry:
8 %puts = tail call i32 @puts(i8* getelementptr inbounds ([3 x i8]* @str, i64 0, i64 0))
9 ret void, !dbg !17
10 }
11
12 ; CHECK: arg.c:5:14
13
14 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp {
15 entry:
16 tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !9), !dbg !19
17 tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !10), !dbg !20
18 %cmp = icmp sgt i32 %argc, 1, !dbg !21
19 br i1 %cmp, label %cond.end, label %for.body.lr.ph, !dbg !21
20
21 cond.end: ; preds = %entry
22 %arrayidx = getelementptr inbounds i8** %argv, i64 1, !dbg !21
23 %tmp2 = load i8** %arrayidx, align 8, !dbg !21, !tbaa !22
24 %call = tail call i32 (...)* @atoi(i8* %tmp2) nounwind, !dbg !21
25 tail call void @llvm.dbg.value(metadata !{i32 %call}, i64 0, metadata !16), !dbg !21
26 tail call void @llvm.dbg.value(metadata !25, i64 0, metadata !14), !dbg !26
27 %cmp57 = icmp sgt i32 %call, 0, !dbg !26
28 br i1 %cmp57, label %for.body.lr.ph, label %for.end, !dbg !26
29
30 for.body.lr.ph: ; preds = %entry, %cond.end
31 %cond10 = phi i32 [ %call, %cond.end ], [ 300, %entry ]
32 br label %for.body
33
34 for.body: ; preds = %for.body, %for.body.lr.ph
35 %i.08 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
36 %puts.i = tail call i32 @puts(i8* getelementptr inbounds ([3 x i8]* @str, i64 0, i64 0)) nounwind
37 %inc = add nsw i32 %i.08, 1, !dbg !27
38 %exitcond = icmp eq i32 %inc, %cond10
39 br i1 %exitcond, label %for.end, label %for.body, !dbg !26
40
41 for.end: ; preds = %for.body, %cond.end
42 ret i32 0, !dbg !29
43 }
44
45 declare i32 @atoi(...)
46
47 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
48
49 declare i32 @puts(i8* nocapture) nounwind
50
51 !llvm.dbg.sp = !{!0, !5}
52 !llvm.dbg.lv.main = !{!9, !10, !14, !16}
53
54 !0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, void ()* @foo} ; [ DW_TAG_subprogram ]
55 !1 = metadata !{i32 589865, metadata !"arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
56 !2 = metadata !{i32 589841, i32 0, i32 12, metadata !"arg.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 124504)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
57 !3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
58 !4 = metadata !{null}
59 !5 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main} ; [ DW_TAG_subprogram ]
60 !6 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
61 !7 = metadata !{metadata !8}
62 !8 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
63 !9 = metadata !{i32 590081, metadata !5, metadata !"argc", metadata !1, i32 5, metadata !8, i32 0} ; [ DW_TAG_arg_variable ]
64 !10 = metadata !{i32 590081, metadata !5, metadata !"argv", metadata !1, i32 5, metadata !11, i32 0} ; [ DW_TAG_arg_variable ]
65 !11 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ]
66 !12 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !13} ; [ DW_TAG_pointer_type ]
67 !13 = metadata !{i32 589860, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
68 !14 = metadata !{i32 590080, metadata !15, metadata !"i", metadata !1, i32 7, metadata !8, i32 0} ; [ DW_TAG_auto_variable ]
69 !15 = metadata !{i32 589835, metadata !5, i32 6, i32 1, metadata !1, i32 1} ; [ DW_TAG_lexical_block ]
70 !16 = metadata !{i32 590080, metadata !15, metadata !"iterations", metadata !1, i32 8, metadata !8, i32 0} ; [ DW_TAG_auto_variable ]
71 !17 = metadata !{i32 4, i32 1, metadata !18, null}
72 !18 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
73 !19 = metadata !{i32 5, i32 14, metadata !5, null}
74 !20 = metadata !{i32 5, i32 26, metadata !5, null}
75 !21 = metadata !{i32 8, i32 51, metadata !15, null}
76 !22 = metadata !{metadata !"any pointer", metadata !23}
77 !23 = metadata !{metadata !"omnipotent char", metadata !24}
78 !24 = metadata !{metadata !"Simple C/C++ TBAA", null}
79 !25 = metadata !{i32 0}
80 !26 = metadata !{i32 9, i32 2, metadata !15, null}
81 !27 = metadata !{i32 9, i32 30, metadata !28, null}
82 !28 = metadata !{i32 589835, metadata !15, i32 9, i32 2, metadata !1, i32 2} ; [ DW_TAG_lexical_block ]
83 !29 = metadata !{i32 12, i32 9, metadata !15, null}