llvm.org GIT mirror llvm / e94ac88
Add support for the ARM GHC calling convention, this patch was in 3.0, but somehow managed to be dropped later. Patch by Karel Gardas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161226 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 8 years ago
5 changed file(s) with 54 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
6161
6262 const uint16_t*
6363 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
64 bool ghcCall = false;
65
66 if (MF) {
67 const Function *F = MF->getFunction();
68 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
69 }
70
71 if (ghcCall) {
72 return CSR_GHC_SaveList;
73 }
74 else {
6475 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
6576 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
77 }
6678 }
6779
6880 const uint32_t*
7878 CCDelegateTo
7979 ]>;
8080
81 //===----------------------------------------------------------------------===//
82 // ARM APCS Calling Convention for GHC
83 //===----------------------------------------------------------------------===//
84
85 def CC_ARM_APCS_GHC : CallingConv<[
86 // Handle all vector types as either f64 or v2f64.
87 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>,
88 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>,
89
90 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
91 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
92 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
93
94 // Promote i8/i16 arguments to i32.
95 CCIfType<[i8, i16], CCPromoteToType>,
96
97 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
98 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
99 ]>;
81100
82101 //===----------------------------------------------------------------------===//
83102 // ARM AAPCS (EABI) Calling Convention, common parts
170189 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
171190 // Also save R7-R4 first to match the stack frame fixed spill areas.
172191 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
192
193 // GHC set of callee saved regs is empty as all those regs are
194 // used for passing STG regs around
195 // add is a workaround for not being able to compile empty list:
196 // def CSR_GHC : CalleeSavedRegs<()>;
197 def CSR_GHC : CalleeSavedRegs<(add)>;
18411841 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
18421842 case CallingConv::ARM_APCS:
18431843 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1844 case CallingConv::GHC:
1845 if (Return)
1846 llvm_unreachable("Can't return in GHC call convention");
1847 else
1848 return CC_ARM_APCS_GHC;
18441849 }
18451850 }
18461851
1414 #include "ARMBaseInstrInfo.h"
1515 #include "ARMBaseRegisterInfo.h"
1616 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Function.h"
1719 #include "MCTargetDesc/ARMAddressingModes.h"
1820 #include "llvm/Function.h"
1921 #include "llvm/CodeGen/MachineFrameInfo.h"
149151 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
150152 int FramePtrSpillFI = 0;
151153 int D8SpillFI = 0;
154
155 // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.
156 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
157 return;
152158
153159 // Allocate the vararg register save area. This is not counted in NumBytes.
154160 if (VARegSaveSize)
352358 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
353359 int NumBytes = (int)MFI->getStackSize();
354360 unsigned FramePtr = RegInfo->getFrameRegister(MF);
361
362 // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.
363 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
364 return;
355365
356366 if (!AFI->hasStackFrame()) {
357367 if (NumBytes != 0)
11701170 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
11711171 case CallingConv::ARM_APCS:
11721172 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1173 case CallingConv::GHC:
1174 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
11731175 }
11741176 }
11751177