llvm.org GIT mirror llvm / e927841
[AARCH64] Enable AARCH64 lit tests on windows dev machines As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows This will hopefully help stop cases where windows developers break the aarch64 target Differential Revision: https://reviews.llvm.org/D22191 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275973 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 3 years ago
177 changed file(s) with 193 addition(s) and 212 deletion(s). Raw diff Collapse all Expand all
None ; RUN: llc -O3 -march=aarch64 < %s | FileCheck %s
0 ; RUN: llc < %s -O3 -mtriple=aarch64-eabi | FileCheck %s
11
22 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
33 @end_of_array = common global i8* null, align 8
None ; RUN: llc < %s -march=arm64
0 ; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu
11 ; Make sure we are not crashing on this test.
22
33 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
4 target triple = "aarch64-unknown-linux-gnu"
54
65 declare void @extern(i8*)
76
None ; RUN: llc -march=aarch64 -aarch64-neon-syntax=generic < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=generic | FileCheck %s
11
22 define i8 @add_B(<16 x i8>* %arr) {
33 ; CHECK-LABEL: add_B
None ; RUN: llc -march=aarch64 -aarch64-neon-syntax=generic < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-linu--gnu -aarch64-neon-syntax=generic | FileCheck %s
11
22 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
3 target triple = "aarch64-linu--gnu"
43
54 ; CHECK-LABEL: smax_B
65 ; CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11 define void @foo(i64 %val) {
22 ; CHECK: foo
33 ; The stack frame store is not 64-bit aligned. Make sure we use an
None ; RUN: llc < %s -march=arm64
0 ; RUN: llc < %s -mtriple=arm64-eabi
11
22 ; The target lowering for integer comparisons was replacing some DAG nodes
33 ; during operation legalization, which resulted in dangling pointers,
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 define i32 @foo(<4 x i32> %a, i32 %n) nounwind {
33 ; CHECK-LABEL: foo:
None ; RUN: llc < %s -march arm64 -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s
11 ;
22
33 @b = private unnamed_addr constant [3 x i32] [i32 1768775988, i32 1685481784, i32 1836253201], align 4
None ; RUN: llc -march=arm64 -O0 -verify-machineinstrs < %s | FileCheck %s
1 ; RUN: llc -march=arm64 -O3 -verify-machineinstrs < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -O0 -verify-machineinstrs | FileCheck %s
1 ; RUN: llc < %s -mtriple=arm64-eabi -O3 -verify-machineinstrs | FileCheck %s
22
33 @.str = private unnamed_addr constant [9 x i8] c"%lf %lu\0A\00", align 1
44 @.str1 = private unnamed_addr constant [8 x i8] c"%lf %u\0A\00", align 1
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -fp-contract=fast | FileCheck %s --check-prefix=FAST
0 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -aarch64-neon-syntax=apple | FileCheck %s
1 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -aarch64-neon-syntax=apple -fp-contract=fast | FileCheck %s --check-prefix=FAST
22
33 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
4 target triple = "arm64-apple-ios7.0.0"
54
65 ;FAST-LABEL: _Z9example25v:
76 ;FAST: fcmgt.4s
None ; RUN: llc < %s -march=arm64
0 ; RUN: llc < %s -mtriple=arm64-eabi
11 ; Make sure we are not crashing on this test.
22
33 define void @autogen_SD13158() {
None ; RUN: llc < %s -march=arm64
0 ; RUN: llc < %s -mtriple=arm64-eabi
11
22 ; Make sure we are not crashing on this test.
33
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple
11
22 ;CHECK-LABEL: Shuff:
33 ;CHECK: tbl.8b
None ; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-NOOPT
1 ; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-OPT
2 ; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-NOOPT
3 ; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-OPT
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-NOOPT
1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-OPT
2 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-NOOPT
3 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-OPT
44
55 define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
66 ; CHECK-LABEL: bar:
None ; RUN: llc < %s -march=arm64
0 ; RUN: llc < %s -mtriple=arm64-eabi
11
22 ; This test case tests an infinite loop bug in DAG combiner.
33 ; It just tries to do the following replacing endlessly:
None ; RUN: llc -O0 -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs < %s | FileCheck %s
0 ; RUN: llc -O0 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs < %s | FileCheck %s
11
22 ; The following 2 test cases test shufflevector with beginning UNDEF mask.
33 define <8 x i16> @test_vext_undef_traverse(<8 x i16> %in) {
None ; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s
1 target triple = "arm64-apple-ios7.0.0"
0 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -mcpu=cyclone -enable-misched=false | FileCheck %s
21
32 ; rdar://13625505
43 ; Here we have 9 fixed integer arguments the 9th argument in on stack, the
None ; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false -disable-fp-elim | FileCheck %s
1 ; RUN: llc < %s -O0 -disable-fp-elim | FileCheck -check-prefix=FAST %s
2 target triple = "arm64-apple-darwin"
0 ; RUN: llc < %s -mtriple=arm64-apple-darwin -mcpu=cyclone -enable-misched=false -disable-fp-elim | FileCheck %s
1 ; RUN: llc < %s -mtriple=arm64-apple-darwin -O0 -disable-fp-elim | FileCheck -check-prefix=FAST %s
32
43 ; rdar://12648441
54 ; Generated from arm64-arguments.c with -O2.
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
11
22 define double @foo(<2 x double> %a) nounwind {
33 ; CHECK-LABEL: foo:
None ; RUN: llc -march arm64 < %s -aarch64-collect-loh=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-apple-ios3.0.0 -aarch64-collect-loh=false | FileCheck %s
11 ; rdar://13452552
22 ; Disable the collecting of LOH so that the labels do not get in the
33 ; way of the NEXT patterns.
44 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
5 target triple = "arm64-apple-ios3.0.0"
65
76 @block = common global i8* null, align 8
87
None ; RUN: llc -march=arm64 < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm64-eabi < %s | FileCheck %s
11 ; rdar://10232252
22
33 @object = external hidden global i64, section "__DATA, __objc_ivar", align 8
None ; RUN: llc -march=arm64 -mcpu=cyclone < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm64-eabi -mcpu=cyclone < %s | FileCheck %s
11
22 ; CHECK: foo
33 ; CHECK: str w[[REG0:[0-9]+]], [x19, #264]
None ; RUN: llc -O1 -march=arm64 -enable-andcmp-sinking=true < %s | FileCheck %s
0 ; RUN: llc -O1 -mtriple=arm64-apple-ios7.0.0 -enable-andcmp-sinking=true < %s | FileCheck %s
11 ; ModuleID = 'and-cbz-extr-mr.bc'
22 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
3 target triple = "arm64-apple-ios7.0.0"
43
54 define zeroext i1 @foo(i1 %IsEditable, i1 %isTextField, i8* %str1, i8* %str2, i8* %str3, i8* %str4, i8* %str5, i8* %str6, i8* %str7, i8* %str8, i8* %str9, i8* %str10, i8* %str11, i8* %str12, i8* %str13, i32 %int1, i8* %str14) unnamed_addr #0 align 2 {
65 ; CHECK: _foo:
None ; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s
11
22 define i32 @qadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
33 ; CHECK-LABEL: qadds:
None ; RUN: llc < %s -march=arm64 -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false | FileCheck %s
11
22 define i32 @t1(i32 %a, i32 %b) nounwind readnone ssp {
33 entry:
None ; RUN: llc -march=arm64 -aarch64-dead-def-elimination=false < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm64-apple-ios7.0.0 -aarch64-dead-def-elimination=false < %s | FileCheck %s
11
22 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
3 target triple = "arm64-apple-ios7.0.0"
43
54 ; Function Attrs: nounwind ssp uwtable
65 define i32 @test1() #0 {
None ; RUN: llc < %s -march=arm64 -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone | FileCheck %s
11
22 @var = global i128 0
33
None ; RUN: llc < %s -march=arm64 -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
11
22 define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 {
33 ; CHECK-LABEL: val_compare_and_swap:
None ; RUN: llc -march=arm64 < %s
0 ; RUN: llc -mtriple=arm64-eabi < %s
11
22
33 ; Make sure large offsets aren't mistaken for valid immediate offsets.
0 ; RUN: opt -codegenprepare -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s
1 ; RUN: llc < %s -march=arm64 | FileCheck %s
1 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
22 %struct.X = type { i8, i8, [2 x i8] }
33 %struct.Y = type { i32, i8 }
44 %struct.Z = type { i8, i8, [2 x i8], i16 }
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 ; Check that building up a vector w/ only one non-zero lane initializes
33 ; intelligently.
None ; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
11
22 ; Function Attrs: nounwind readnone
33 declare i8* @llvm.thread.pointer() #1
None ; RUN: llc -O3 -march=arm64 -mtriple arm64-apple-ios5.0.0 < %s | FileCheck %s
0 ; RUN: llc -O3 -mtriple arm64-apple-ios5.0.0 < %s | FileCheck %s
11 ;
22 ; Zero truncation is not necessary when the values are extended properly
33 ; already.
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 | FileCheck %s
11
22 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
3 target triple = "arm64-apple-ios7.0.0"
43
54 ; Function Attrs: nounwind readnone
65 declare i32 @llvm.ctlz.i32(i32, i1) #0
None ; RUN: llc -march=arm64 -mtriple=arm64-apple-darwin < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm64-apple-darwin < %s | FileCheck %s
11 ; Check that the peephole optimizer knows about sext and zext instructions.
22 ; CHECK: test1sext
33 define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
None ; RUN: llc -march=arm64 -o - %s | FileCheck %s
0 ; RUN: llc -mtriple=arm64-eabi -o - %s | FileCheck %s
11
22 define { i192, i192, i21, i192 } @foo(i192) {
33 ; CHECK-LABEL: foo:
None ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22
33 define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) {
None ; RUN: llc -march=arm64 -mattr=+crc -o - %s | FileCheck %s
0 ; RUN: llc -mtriple=arm64-eabi -mattr=+crc -o - %s | FileCheck %s
11
22 define i32 @test_crc32b(i32 %cur, i8 %next) {
33 ; CHECK-LABEL: test_crc32b:
None ; RUN: llc -march=arm64 -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s
0 ; RUN: llc -mtriple=arm64-eabi -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s
11
22 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
33 declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 ;
33 ; Floating-point scalar convert to signed integer (to nearest with ties to away)
None ; RUN: llc -march=arm64 < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 | FileCheck %s
11
22 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
3 target triple = "arm64-apple-ios7.0.0"
43
54 ; Function Attrs: nounwind ssp uwtable
65 define i32 @test1() #0 {
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
11
22 define <8 x i8> @v_dup8(i8 %A) nounwind {
33 ;CHECK-LABEL: v_dup8:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: test_vextd:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <4 x float> @foo(<4 x i16> %a) nounwind {
33 ; CHECK-LABEL: foo:
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11 ; rdar://12771555
22
33 define void @foo(i16* %ptr, i32 %a) nounwind {
None ; RUN: llc -verify-machineinstrs < %s \
1 ; RUN: -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s
21
32 define i64 @ror_i64(i64 %in) {
43 ; CHECK-LABEL: ror_i64:
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 ; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn.
33
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 define void @caller(i32* nocapture %p, i32 %a, i32 %b) nounwind optsize ssp {
33 ; CHECK-NOT: stp
None ; RUN: llc < %s -march=arm64 -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
11 ; rdar://10263824
22
33 define i1 @fcmp_float1(float %a) nounwind ssp {
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 ; DAGCombine to transform a conversion of an extract_vector_elt to an
33 ; extract_vector_elt of a conversion, which saves a round trip of copies
None ; RUN: llc -march=arm64 < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm64-eabi < %s | FileCheck %s
11
22 define float @fma32(float %a, float %b, float %c) nounwind readnone ssp {
33 entry:
None ; RUN: llc -march=arm64 < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 define double @test_direct(float %in) {
33 ; CHECK-LABEL: test_direct:
None ; RUN: llc -march=arm64 -enable-no-nans-fp-math < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -enable-no-nans-fp-math | FileCheck %s
11
22 define double @test_direct(float %in) {
33 ; CHECK-LABEL: test_direct:
None ; RUN: llc -asm-verbose=false < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -asm-verbose=false -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define float @test_f32(float* %A, float* %B, float* %C) nounwind {
33 ;CHECK-LABEL: test_f32:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11 ;
22 ;
33
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 define float @t1(i1 %a, float %b, float %c) nounwind {
33 ; CHECK: t1
None ; RUN: llc -march=arm64 -verify-machineinstrs < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s
11 declare void @bar(i8*, i8*, i32*)
22
33 ; SelectionDAG used to try to fold some fp128 operations using the ppc128 type,
None ; RUN: llc -march=arm64 -mtriple=arm64-apple-ios -aarch64-atomic-cfg-tidy=0 < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-atomic-cfg-tidy=0 | FileCheck %s
11 ; rdar://11935841
22
33 define void @t1() nounwind ssp {
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define i32 @foo(<4 x i16>* %__a) nounwind {
33 ; CHECK-LABEL: foo:
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 ; Optimize (x > -1) to (x >= 0) etc.
33 ; Optimize (cmp (add / sub), 0): eliminate the subs used to update flag
None ; RUN: llc < %s -march=arm64 -aarch64-redzone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-redzone | FileCheck %s
11
22 define void @store64(i64** nocapture %out, i64 %index, i64 %spacing) nounwind noinline ssp {
33 ; CHECK-LABEL: store64:
None ; RUN: not llc -march=arm64 < %s 2> %t
0 ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
11 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
22
33 ; Check for at least one invalid constant.
None ; RUN: not llc -march=arm64 < %s 2> %t
0 ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
11 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
22
33 ; Check for at least one invalid constant.
None ; RUN: not llc -march=arm64 < %s 2> %t
0 ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
11 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
22
33 ; Check for at least one invalid constant.
None ; RUN: not llc -march=arm64 < %s 2> %t
0 ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
11 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
22
33 ; Check for at least one invalid constant.
None ; RUN: not llc -march=arm64 < %s 2> %t
0 ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
11 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
22
33 ; Check for at least one invalid constant.
None ; RUN: not llc -march=arm64 < %s 2> %t
0 ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
11 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
22
33 ; Check for at least one invalid constant.
None ; RUN: not llc < %s -march=arm64 2>&1 | FileCheck %s
0 ; RUN: not llc < %s -mtriple=arm64-eabi 2>&1 | FileCheck %s
11
22
33 ; The 'z' constraint allocates either xzr or wzr, but obviously an input of 1 is
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -asm-verbose=false | FileCheck %s
11
22 %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
33 %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
None ; RUN: llc < %s -march=arm64 -enable-misched=false -verify-machineinstrs | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -enable-misched=false -verify-machineinstrs | FileCheck %s
11
22 ; The next set of tests makes sure we can combine the second instruction into
33 ; the first.
None ; RUN: llc < %s -march=arm64 -verify-machineinstrs | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s
11
22 ; CHECK-LABEL: ldp_int
33 ; CHECK: ldp
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 define i64 @_f0(i64* %p) {
33 ; CHECK: f0:
None ; RUN: llc -march=arm64 -mtriple=arm64-apple-ios < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
11 ; rdar://12829704
22
33 define void @t8() nounwind ssp {
None ; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s
11
22 define i128 @shl(i128 %r, i128 %s) nounwind readnone {
33 ; CHECK-LABEL: shl:
None ; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s
11
22 %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
33
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 define void @t1(i8* nocapture %c) nounwind optsize {
33 entry:
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 ;==--------------------------------------------------------------------------==
33 ; Tests for MOV-immediate implemented with ORR-immediate.
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 ; rdar://9296808
33 ; rdar://9349137
None ; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V8a
1 ; RUN: llc < %s -verify-machineinstrs -march=arm64 -mattr=+v8.1a -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V81a
2 ; RUN: llc < %s -verify-machineinstrs -march=arm64 -mattr=+v8.1a -aarch64-neon-syntax=apple | FileCheck %s --check-prefix=CHECK-V81a-apple
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V8a
1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+v8.1a -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V81a
2 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+v8.1a -aarch64-neon-syntax=apple | FileCheck %s --check-prefix=CHECK-V81a-apple
33
44 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
55 declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
1 ; RUN: llc < %s -march=aarch64 -mattr -neon -aarch64-neon-syntax=apple | FileCheck -check-prefix=CHECK-NONEON %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
1 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr -neon -aarch64-neon-syntax=apple | FileCheck -check-prefix=CHECK-NONEON %s
22
33 define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
44 %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
None ; RUN: llc %s -march arm64 -o - | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 @a = common global i32* null, align 8
33
None ; RUN: llc < %s -march=arm64 -aarch64-redzone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-redzone | FileCheck %s
11
22 define i32 @foo(i32 %a, i32 %b) nounwind ssp {
33 ; CHECK-LABEL: foo:
None ; RUN: llc -march=arm64 -verify-machineinstrs < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s
11
22 ; We used to not mark NZCV as being used in the continuation basic-block
33 ; when lowering a 128-bit "select" to branches. This meant a subsequent use
None ; RUN: llc -march=arm64 -o - %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 ; This is mostly a "don't assert" test. The type of the RHS of a shift depended
33 ; on the phase of legalization, which led to the creation of an unexpected and
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 ; 2x64 vector should be returned in Q0.
33
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 define i8* @rt0(i32 %x) nounwind readnone {
33 entry:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define i32 @test_rev_w(i32 %a) nounwind {
33 entry:
None ; RUN: llc < %s -march=arm64 -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
1 ; RUN: llc < %s -march=arm64 -mcpu=cortex-a57 | FileCheck --check-prefix=CHECK-A57 %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
1 ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cortex-a57 | FileCheck --check-prefix=CHECK-A57 %s
22 ; rdar://13082402
33
44 define float @t1(i32* nocapture %src) nounwind ssp {
None ; RUN: llc -march=arm64 -mtriple=arm64-apple-ios < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
11 ;
22 ;
33
None ; RUN: llc -march=arm64 < %s
0 ; RUN: llc < %s -mtriple=arm64-eabi
11
22 ; The DAGCombiner tries to do following shrink:
33 ; Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
22
33 define <16 x i8> @foo(<16 x i8> %a) nounwind optsize readnone ssp {
44 ; CHECK: uaddlv.16b h0, v0
None ; RUN: llc -march=arm64 -o - %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 ; ARM64ISelLowering.cpp was creating a new (floating-point) load for efficiency
33 ; but not updating chain-successors of the old one. As a result, the two memory
None ; RUN: llc -aarch64-shift-insert-generation=true -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
0 ; RUN: llc < %s -aarch64-shift-insert-generation=true -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define void @testLeftGood(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
33 ; CHECK-LABEL: testLeftGood:
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
11
22 define signext i8 @test_vmaxv_s8(<8 x i8> %a1) {
33 ; CHECK: test_vmaxv_s8
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
11
22 define signext i8 @test_vminv_s8(<8 x i8> %a1) {
33 ; CHECK: test_vminv_s8
None ; RUN: llc < %s -verify-machineinstrs -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi | FileCheck %s
11
22 ; Check if sqshl/uqshl with constant shift amout can be selected.
33 define i64 @test_vqshld_s64_i(i64 %a) {
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
11
22 define void @st1lane_16b(<16 x i8> %A, i8* %D) {
33 ; CHECK-LABEL: st1lane_16b
None ; RUN: llc < %s -march=arm64 -enable-misched=false -aarch64-stp-suppress=false -verify-machineinstrs | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -enable-misched=false -aarch64-stp-suppress=false -verify-machineinstrs | FileCheck %s
11
22 ; The next set of tests makes sure we can combine the second instruction into
33 ; the first.
None ; RUN: llc < %s -march=arm64 -aarch64-stp-suppress=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-stp-suppress=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
11
22 ; CHECK-LABEL: stp_int
33 ; CHECK: stp w0, w1, [x2]
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
11 %struct.X = type <{ i32, i64, i64 }>
22
33 define void @foo1(i32* %p, i64 %val) nounwind {
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
11
22 ; Test efficient codegen of vector extends up from legal type to 128 bit
33 ; and 256 bit vector types.
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @tbl1_8b(<16 x i8> %A, <8 x i8> %B) nounwind {
33 ; CHECK: tbl1_8b
None ; RUN: llc < %s -march=arm64 -aarch64-this-return-forwarding | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-this-return-forwarding | FileCheck %s
11
22 %struct.A = type { i8 }
33 %struct.B = type { i32 }
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11 define void @foo() nounwind {
22 ; CHECK: foo
33 ; CHECK: brk #0x1
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vtrni8:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
11
22 define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp {
33 ; CHECK-LABEL: vmax_u8x8:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
11
22 define i32 @vmin_u8x8(<8 x i8> %a) nounwind ssp {
33 ; CHECK-LABEL: vmin_u8x8:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define zeroext i8 @f1(<16 x i8> %a) {
33 ; CHECK-LABEL: f1:
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11 ; rdar://r11231896
22
33 define void @t1(i8* nocapture %a, i8* nocapture %b) nounwind {
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vuzpi8:
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-apple-darwin11.0.0 | FileCheck %s
11 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64"
2 target triple = "arm64-apple-darwin11.0.0"
32
43 define float @t1(i8* nocapture %fmt, ...) nounwind ssp {
54 entry:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22
33 define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
11
22 define <8 x i8> @addhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
33 ;CHECK-LABEL: addhn8b:
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define i64 @test_vaddlv_s32(<2 x i32> %a1) nounwind readnone {
33 ; CHECK: test_vaddlv_s32
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -asm-verbose=false -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false -mcpu=cyclone | FileCheck %s
11
22 define signext i8 @test_vaddv_s8(<8 x i8> %a1) {
33 ; CHECK-LABEL: test_vaddv_s8:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @rbit_8b(<8 x i8>* %A) nounwind {
33 ;CHECK-LABEL: rbit_8b:
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @test_vclz_u8(<8 x i8> %a) nounwind readnone ssp {
33 ; CHECK-LABEL: test_vclz_u8:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22
33 define void @fcmltz_4s(<4 x float> %a, <4 x i16>* %p) nounwind {
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind {
33 ;CHECK-LABEL: cls_8b:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 ; LowerCONCAT_VECTORS() was reversing the order of two parts.
33 ; rdar://11558157
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <2 x i32> @fcvtas_2s(<2 x float> %A) nounwind {
33 ;CHECK-LABEL: fcvtas_2s:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
1 ; RUN: llc < %s -O0 -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
1 ; RUN: llc < %s -O0 -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
22
33 define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {
44 ; CHECK-LABEL: test_vcvt_f64_f32:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <2 x float> @ucvt(<2 x i32> %a) nounwind readnone ssp {
33 ; CHECK-LABEL: ucvt:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <2 x float> @cvtf32fxpu(<2 x i32> %a) nounwind readnone ssp {
33 ; CHECK-LABEL: cvtf32fxpu:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <2 x i32> @c1(<2 x float> %a) nounwind readnone ssp {
33 ; CHECK: c1
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 define float @fcvtxn(double %a) {
33 ; CHECK-LABEL: fcvtxn:
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-apple-ios3.0.0 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
11 ; ModuleID = 'arm64_vecCmpBr.c'
22 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
3 target triple = "arm64-apple-ios3.0.0"
43
54
65 define i32 @anyZero64(<4 x i16> %a) #0 {
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -o - %s| FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <16 x i8> @foov16i8(<8 x i16> %a0, <8 x i16> %b0) nounwind readnone ssp {
33 ; CHECK-LABEL: foov16i8:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 ;CHECK: @func30
33 ;CHECK: movi.4h v1, #1
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
33 ; CHECK-LABEL: v_orrimm:
None ; RUN: llc -march=arm64 -mcpu=generic -aarch64-neon-syntax=apple < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=generic -aarch64-neon-syntax=apple | FileCheck %s
11
22 define void @test0f(float* nocapture %x, float %a) #0 {
33 entry:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
11
22 ; rdar://9428579
33
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define void @test_vext_s8() nounwind ssp {
33 ; CHECK-LABEL: test_vext_s8:
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 ;;; Float vectors
33
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @shadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: shadd8b:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: shsub8b:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @smax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: smax_8b:
243243 declare <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
244244 declare <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
245245
246 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
246 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
247247
248248 define <8 x i8> @smaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
249249 ;CHECK-LABEL: smaxp_8b:
367367 declare <2 x i32> @llvm.aarch64.neon.umaxp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
368368 declare <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
369369
370 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
370 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
371371
372372 define <8 x i8> @sminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
373373 ;CHECK-LABEL: sminp_8b:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <2 x float> @f1(<2 x float> %a, <2 x float> %b) nounwind readnone ssp {
33 ; CHECK: fmaxnm.2s v0, v0, v1
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @xtn8b(<8 x i16> %A) nounwind {
33 ;CHECK-LABEL: xtn8b:
None ; RUN: llc -asm-verbose=false < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -asm-verbose=false -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22
33 define <8 x i16> @smull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11 define i64 @normal_load(i64* nocapture %bar) nounwind readonly {
22 ; CHECK: normal_load
33 ; CHECK: ldp
None ; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
1 target triple = "arm64-apple-ios"
0 ; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s
21
32 ; The non-byte ones used to fail with "Cannot select"
43
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @sqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: sqadd8b:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: sqsub8b:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 ;CHECK: @func63
33 ;CHECK: cmeq.4h v0, v0, v1
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
11 define <2 x i32> @fcmp_one(<2 x float> %x, <2 x float> %y) nounwind optsize readnone {
22 ; CHECK-LABEL: fcmp_one:
33 ; CHECK-NEXT: fcmgt.2s [[REG:v[0-9]+]], v0, v1
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -enable-misched=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -enable-misched=false | FileCheck %s
11
22 define <8 x i8> @sqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: sqshl8b:
None ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
11
22 define <8 x i16> @testShiftRightArith_v8i16(<8 x i16> %a, <8 x i16> %b) #0 {
33 ; CHECK-LABEL: testShiftRightArith_v8i16:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <2 x float> @frecps_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
33 ;CHECK-LABEL: frecps_2s:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vsras8:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @subhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
33 ;CHECK-LABEL: subhn8b:
None ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -disable-post-ra -verify-machineinstrs < %s | FileCheck %s
1 ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -disable-post-ra -verify-machineinstrs < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-atomic-cfg-tidy=0 -disable-post-ra -verify-machineinstrs | FileCheck %s
1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -disable-post-ra -verify-machineinstrs | FileCheck %s
22
33 ;
44 ; Get the actual value of the overflow bit.
None ; RUN: llc < %s -march=arm64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 define i64 @foo(i32 %a, i32 %b) nounwind readnone ssp {
33 entry:
None ; RUN: llc -march=arm64 < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
11
22 @var32 = global i32 0
33
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vzipi8:
None ; RUN: llc -march=aarch64 -no-integrated-as < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-eabi -no-integrated-as | FileCheck %s
11
22 define void @test() {
33 entry:
None ; RUN: llc -march=aarch64 -mtriple=aarch64-none-linux-gnu -stop-after branch-folder -o - < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -stop-after branch-folder | FileCheck %s
11 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
22
33 ; Function Attrs: norecurse nounwind
None ; RUN: llc -O3 -march=aarch64 < %s | FileCheck %s
0 ; RUN: llc < %s -O3 -mtriple=aarch64-eabi | FileCheck %s
11
22 define i16 @test_1cmp_signed_1(i16* %ptr1) {
33 ; CHECK-LABLE: @test_1cmp_signed_1
None ; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
11
22 ; marked as external to prevent possible optimizations
33 @a = external global i32
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 define <2 x i64> @test_v2f32_to_signed_v2i64(<2 x float> %in) {
33 ; CHECK-LABEL: test_v2f32_to_signed_v2i64:
None ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
11
22 ; CHECK: autogen_SD19655
33 ; CHECK: scvtf
None ; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
11
22 define i32 @testsize1(i32 %x) minsize nounwind {
33 entry:
None ; RUN: llc -march=aarch64 -o - %s
1 target triple = "arm64-unknown-unknown"
0 ; RUN: llc -mtriple=arm64-unknown-unknown -o - %s
21
32 ; Make sure we don't run into an assert in the aarch64 code selection when
43 ; DAGCombining fails.
None ; RUN: llc < %s -march=aarch64 -aarch64-neon-syntax=apple -aarch64-stp-suppress=false -verify-machineinstrs -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple -aarch64-stp-suppress=false -verify-machineinstrs -asm-verbose=false | FileCheck %s
11
22 ; CHECK-LABEL: test_strd_sturd:
33 ; CHECK-NEXT: stp d0, d1, [x0, #-8]
None ; RUN: llc -march=aarch64 -mcpu=bogus -o - %s
0 ; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=bogus
11
22 ; Fix the bug in PR20557. Set mcpu to a bogus name, llc will crash in type
33 ; legalization.
11
22 if not 'AArch64' in config.root.targets:
33 config.unsupported = True
4
5 # For now we don't test arm64-win32.
6 if re.search(r'cygwin|mingw32|win32|windows-gnu|windows-msvc', config.target_triple):
7 config.unsupported = True
None ; RUN: llc -march=aarch64 -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
11
22 ; and can be eliminated
33 ; CHECK-LABEL: {{^}}test_call_known_max_range:
None ; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
11
22 %structA = type { i128 }
33 @stubA = internal unnamed_addr constant %structA zeroinitializer, align 8
None ; RUN: llc -mcpu cortex-a53 -march aarch64 %s -o - | FileCheck %s --check-prefix=A53
0 ; RUN: llc < %s -mcpu cortex-a53 -mtriple=aarch64-eabi | FileCheck %s --check-prefix=A53
11
22 ; PR26827 - Merge stores causes wrong dependency.
33 %struct1 = type { %struct1*, %struct1*, i32, i32, i16, i16, void (i32, i32, i8*)*, i8* }
None ; RUN: llc -mtriple=aarch64-unknown-unknown %s -mcpu=cyclone -o - | FileCheck %s --check-prefix=CYCLONE --check-prefix=CHECK
1 ; RUN: llc -march aarch64 %s -mattr=-slow-misaligned-128store -o - | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK
0 ; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone | FileCheck %s --check-prefix=CYCLONE --check-prefix=CHECK
1 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK
22
33 @g0 = external global <3 x float>, align 16
44 @g1 = external global <3 x float>, align 4
None ; RUN: llc < %s -march=aarch64 | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-eabi | FileCheck %s
11
22 ; Convert mul x, pow2 to shift.
33 ; Convert mul x, pow2 +/- 1 to shift + add/sub.
None ; RUN: llc < %s -march=aarch64 -mattr=+no-quad-ldst-pairs -verify-machineinstrs -asm-verbose=false | FileCheck %s
1 ; RUN: llc < %s -march=aarch64 -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+no-quad-ldst-pairs -verify-machineinstrs -asm-verbose=false | FileCheck %s
1 ; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
22
33 ; CHECK-LABEL: test_nopair_st
44 ; CHECK: str
None ; RUN: llc -verify-machineinstrs -march=aarch64 < %s | FileCheck %s
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-eabi | FileCheck %s
11
22 ; CHECK: mrs [[NZCV_SAVE:x[0-9]+]], NZCV
33 ; CHECK: msr NZCV, [[NZCV_SAVE]]
None ; RUN: llc < %s -O3 -march=aarch64 -mcpu=cortex-a53 | FileCheck %s
0 ; RUN: llc < %s -O3 -mtriple=aarch64-eabi -mcpu=cortex-a53 | FileCheck %s
11
22 ; With cortex-a53, each of fmul and fcvt have latency of 6 cycles. After the
33 ; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive. The top-down
None ; RUN: llc < %s -march=aarch64
0 ; RUN: llc < %s -mtriple=aarch64-eabi
11
22 define i8 @test_minsize_uu8(i8 %x) minsize optsize {
33 entry:
None ; RUN: llc <%s -march=aarch64 -verify-machine-dom-info | FileCheck %s
0 ; RUN: llc <%s -mtriple=aarch64-eabi -verify-machine-dom-info | FileCheck %s
11
22 ; CHECK-LABEL: test:
33 ; CHECK: LBB0_7:
None ; RUN: llc -O1 -march=aarch64 < %s | FileCheck %s
0 ; RUN: llc < %s -O1 -mtriple=aarch64-eabi | FileCheck %s
11
22 declare void @t()
33