llvm.org GIT mirror llvm / e8d62a3
[COFF, ARM64] Add CodeView register mapping CodeView has its own register map which is defined in cvconst.h. Missing this mapping before saving register to CodeView causes debugger to show incorrect value for all register based variables, like variables in register and local variables addressed by register (stack pointer + offset). This change added mapping between LLVM register and CodeView register so the correct register number will be stored to CodeView/PDB, it aso fixed the mapping from CodeView register number to register name based on current CPUType but print PDB to yaml still assumes X86 CPU and needs to be fixed. Differential Revision: https://reviews.llvm.org/D62608 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362280 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Tan 2 months ago
14 changed file(s) with 641 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
508508
509509 // Corresponds to CV_HREG_e enum.
510510 enum class RegisterId : uint16_t {
511 #define CV_REGISTERS_ALL
511512 #define CV_REGISTER(name, value) name = value,
512513 #include "CodeViewRegisters.def"
513514 #undef CV_REGISTER
515 #undef CV_REGISTERS_ALL
516 };
517
518 // Register Ids are shared between architectures in CodeView. CPUType is needed
519 // to map register Id to name.
520 struct CPURegister {
521 CPURegister() = delete;
522 CPURegister(CPUType Cpu, codeview::RegisterId Reg) {
523 this->Cpu = Cpu;
524 this->Reg = Reg;
525 }
526 CPUType Cpu;
527 RegisterId Reg;
514528 };
515529
516530 /// Two-bit value indicating which register is the designated frame pointer
1313 #define CV_REGISTER(name, value)
1414 #endif
1515
16 #if !defined(CV_REGISTERS_ALL) && !defined(CV_REGISTERS_X86) && \
17 !defined(CV_REGISTERS_ARM64)
18 #error Need include at least one register set.
19 #endif
20
1621 // This currently only contains the "register subset shared by all processor
17 // types" (ERR etc.) and the x86 registers.
22 // types" (ERR etc.) and the x86/arm64 registers.
23
24 #if defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_X86)
1825
1926 // Some system headers define macros that conflict with our enums. Every
2027 // compiler supported by LLVM has the push_macro and pop_macro pragmas, so use
355362 #pragma pop_macro("CR2")
356363 #pragma pop_macro("CR3")
357364 #pragma pop_macro("CR4")
365
366 #endif // defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_X86)
367
368 #if defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_ARM64)
369
370 // ARM64 registers
371
372 CV_REGISTER(ARM64_NOREG, 0)
373
374 // General purpose 32-bit integer registers
375
376 CV_REGISTER(ARM64_W0, 10)
377 CV_REGISTER(ARM64_W1, 11)
378 CV_REGISTER(ARM64_W2, 12)
379 CV_REGISTER(ARM64_W3, 13)
380 CV_REGISTER(ARM64_W4, 14)
381 CV_REGISTER(ARM64_W5, 15)
382 CV_REGISTER(ARM64_W6, 16)
383 CV_REGISTER(ARM64_W7, 17)
384 CV_REGISTER(ARM64_W8, 18)
385 CV_REGISTER(ARM64_W9, 19)
386 CV_REGISTER(ARM64_W10, 20)
387 CV_REGISTER(ARM64_W11, 21)
388 CV_REGISTER(ARM64_W12, 22)
389 CV_REGISTER(ARM64_W13, 23)
390 CV_REGISTER(ARM64_W14, 24)
391 CV_REGISTER(ARM64_W15, 25)
392 CV_REGISTER(ARM64_W16, 26)
393 CV_REGISTER(ARM64_W17, 27)
394 CV_REGISTER(ARM64_W18, 28)
395 CV_REGISTER(ARM64_W19, 29)
396 CV_REGISTER(ARM64_W20, 30)
397 CV_REGISTER(ARM64_W21, 31)
398 CV_REGISTER(ARM64_W22, 32)
399 CV_REGISTER(ARM64_W23, 33)
400 CV_REGISTER(ARM64_W24, 34)
401 CV_REGISTER(ARM64_W25, 35)
402 CV_REGISTER(ARM64_W26, 36)
403 CV_REGISTER(ARM64_W27, 37)
404 CV_REGISTER(ARM64_W28, 38)
405 CV_REGISTER(ARM64_W29, 39)
406 CV_REGISTER(ARM64_W30, 40)
407 CV_REGISTER(ARM64_WZR, 41)
408
409 // General purpose 64-bit integer registers
410
411 CV_REGISTER(ARM64_X0, 50)
412 CV_REGISTER(ARM64_X1, 51)
413 CV_REGISTER(ARM64_X2, 52)
414 CV_REGISTER(ARM64_X3, 53)
415 CV_REGISTER(ARM64_X4, 54)
416 CV_REGISTER(ARM64_X5, 55)
417 CV_REGISTER(ARM64_X6, 56)
418 CV_REGISTER(ARM64_X7, 57)
419 CV_REGISTER(ARM64_X8, 58)
420 CV_REGISTER(ARM64_X9, 59)
421 CV_REGISTER(ARM64_X10, 60)
422 CV_REGISTER(ARM64_X11, 61)
423 CV_REGISTER(ARM64_X12, 62)
424 CV_REGISTER(ARM64_X13, 63)
425 CV_REGISTER(ARM64_X14, 64)
426 CV_REGISTER(ARM64_X15, 65)
427 CV_REGISTER(ARM64_X16, 66)
428 CV_REGISTER(ARM64_X17, 67)
429 CV_REGISTER(ARM64_X18, 68)
430 CV_REGISTER(ARM64_X19, 69)
431 CV_REGISTER(ARM64_X20, 70)
432 CV_REGISTER(ARM64_X21, 71)
433 CV_REGISTER(ARM64_X22, 72)
434 CV_REGISTER(ARM64_X23, 73)
435 CV_REGISTER(ARM64_X24, 74)
436 CV_REGISTER(ARM64_X25, 75)
437 CV_REGISTER(ARM64_X26, 76)
438 CV_REGISTER(ARM64_X27, 77)
439 CV_REGISTER(ARM64_X28, 78)
440 CV_REGISTER(ARM64_FP, 79)
441 CV_REGISTER(ARM64_LR, 80)
442 CV_REGISTER(ARM64_SP, 81)
443 CV_REGISTER(ARM64_ZR, 82)
444
445 // status register
446
447 CV_REGISTER(ARM64_NZCV, 90)
448
449 // 32-bit floating point registers
450
451 CV_REGISTER(ARM64_S0, 100)
452 CV_REGISTER(ARM64_S1, 101)
453 CV_REGISTER(ARM64_S2, 102)
454 CV_REGISTER(ARM64_S3, 103)
455 CV_REGISTER(ARM64_S4, 104)
456 CV_REGISTER(ARM64_S5, 105)
457 CV_REGISTER(ARM64_S6, 106)
458 CV_REGISTER(ARM64_S7, 107)
459 CV_REGISTER(ARM64_S8, 108)
460 CV_REGISTER(ARM64_S9, 109)
461 CV_REGISTER(ARM64_S10, 110)
462 CV_REGISTER(ARM64_S11, 111)
463 CV_REGISTER(ARM64_S12, 112)
464 CV_REGISTER(ARM64_S13, 113)
465 CV_REGISTER(ARM64_S14, 114)
466 CV_REGISTER(ARM64_S15, 115)
467 CV_REGISTER(ARM64_S16, 116)
468 CV_REGISTER(ARM64_S17, 117)
469 CV_REGISTER(ARM64_S18, 118)
470 CV_REGISTER(ARM64_S19, 119)
471 CV_REGISTER(ARM64_S20, 120)
472 CV_REGISTER(ARM64_S21, 121)
473 CV_REGISTER(ARM64_S22, 122)
474 CV_REGISTER(ARM64_S23, 123)
475 CV_REGISTER(ARM64_S24, 124)
476 CV_REGISTER(ARM64_S25, 125)
477 CV_REGISTER(ARM64_S26, 126)
478 CV_REGISTER(ARM64_S27, 127)
479 CV_REGISTER(ARM64_S28, 128)
480 CV_REGISTER(ARM64_S29, 129)
481 CV_REGISTER(ARM64_S30, 130)
482 CV_REGISTER(ARM64_S31, 131)
483
484 // 64-bit floating point registers
485
486 CV_REGISTER(ARM64_D0, 140)
487 CV_REGISTER(ARM64_D1, 141)
488 CV_REGISTER(ARM64_D2, 142)
489 CV_REGISTER(ARM64_D3, 143)
490 CV_REGISTER(ARM64_D4, 144)
491 CV_REGISTER(ARM64_D5, 145)
492 CV_REGISTER(ARM64_D6, 146)
493 CV_REGISTER(ARM64_D7, 147)
494 CV_REGISTER(ARM64_D8, 148)
495 CV_REGISTER(ARM64_D9, 149)
496 CV_REGISTER(ARM64_D10, 150)
497 CV_REGISTER(ARM64_D11, 151)
498 CV_REGISTER(ARM64_D12, 152)
499 CV_REGISTER(ARM64_D13, 153)
500 CV_REGISTER(ARM64_D14, 154)
501 CV_REGISTER(ARM64_D15, 155)
502 CV_REGISTER(ARM64_D16, 156)
503 CV_REGISTER(ARM64_D17, 157)
504 CV_REGISTER(ARM64_D18, 158)
505 CV_REGISTER(ARM64_D19, 159)
506 CV_REGISTER(ARM64_D20, 160)
507 CV_REGISTER(ARM64_D21, 161)
508 CV_REGISTER(ARM64_D22, 162)
509 CV_REGISTER(ARM64_D23, 163)
510 CV_REGISTER(ARM64_D24, 164)
511 CV_REGISTER(ARM64_D25, 165)
512 CV_REGISTER(ARM64_D26, 166)
513 CV_REGISTER(ARM64_D27, 167)
514 CV_REGISTER(ARM64_D28, 168)
515 CV_REGISTER(ARM64_D29, 169)
516 CV_REGISTER(ARM64_D30, 170)
517 CV_REGISTER(ARM64_D31, 171)
518
519 // 128-bit SIMD registers
520
521 CV_REGISTER(ARM64_Q0, 180)
522 CV_REGISTER(ARM64_Q1, 181)
523 CV_REGISTER(ARM64_Q2, 182)
524 CV_REGISTER(ARM64_Q3, 183)
525 CV_REGISTER(ARM64_Q4, 184)
526 CV_REGISTER(ARM64_Q5, 185)
527 CV_REGISTER(ARM64_Q6, 186)
528 CV_REGISTER(ARM64_Q7, 187)
529 CV_REGISTER(ARM64_Q8, 188)
530 CV_REGISTER(ARM64_Q9, 189)
531 CV_REGISTER(ARM64_Q10, 190)
532 CV_REGISTER(ARM64_Q11, 191)
533 CV_REGISTER(ARM64_Q12, 192)
534 CV_REGISTER(ARM64_Q13, 193)
535 CV_REGISTER(ARM64_Q14, 194)
536 CV_REGISTER(ARM64_Q15, 195)
537 CV_REGISTER(ARM64_Q16, 196)
538 CV_REGISTER(ARM64_Q17, 197)
539 CV_REGISTER(ARM64_Q18, 198)
540 CV_REGISTER(ARM64_Q19, 199)
541 CV_REGISTER(ARM64_Q20, 200)
542 CV_REGISTER(ARM64_Q21, 201)
543 CV_REGISTER(ARM64_Q22, 202)
544 CV_REGISTER(ARM64_Q23, 203)
545 CV_REGISTER(ARM64_Q24, 204)
546 CV_REGISTER(ARM64_Q25, 205)
547 CV_REGISTER(ARM64_Q26, 206)
548 CV_REGISTER(ARM64_Q27, 207)
549 CV_REGISTER(ARM64_Q28, 208)
550 CV_REGISTER(ARM64_Q29, 209)
551 CV_REGISTER(ARM64_Q30, 210)
552 CV_REGISTER(ARM64_Q31, 211)
553
554 // Floating point status register
555
556 CV_REGISTER(ARM64_FPSR, 220)
557
558 #endif // defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_ARM64)
1919
2020 ArrayRef> getSymbolTypeNames();
2121 ArrayRef> getTypeLeafNames();
22 ArrayRef> getRegisterNames();
22 ArrayRef> getRegisterNames(CPUType Cpu);
2323 ArrayRef> getPublicSymFlagNames();
2424 ArrayRef> getProcSymFlagNames();
2525 ArrayRef> getLocalFlagNames();
2626 raw_ostream &operator<<(raw_ostream &OS, const PDB_CallingConv &Conv);
2727 raw_ostream &operator<<(raw_ostream &OS, const PDB_BuiltinType &Type);
2828 raw_ostream &operator<<(raw_ostream &OS, const PDB_DataKind &Data);
29 raw_ostream &operator<<(raw_ostream &OS, const codeview::RegisterId &Reg);
29 raw_ostream &operator<<(raw_ostream &OS,
30 const llvm::codeview::CPURegister &CpuReg);
3031 raw_ostream &operator<<(raw_ostream &OS, const PDB_LocType &Loc);
3132 raw_ostream &operator<<(raw_ostream &OS, const codeview::ThunkOrdinal &Thunk);
3233 raw_ostream &operator<<(raw_ostream &OS, const PDB_Checksum &Checksum);
125125 Am33 = 0x13,
126126 Amd64 = 0x8664,
127127 Arm = 0x1C0,
128 Arm64 = 0xaa64,
128129 ArmNT = 0x1C4,
129130 Ebc = 0xEBC,
130131 x86 = 0x14C,
3030 #undef CV_TYPE
3131 };
3232
33 static const EnumEntry RegisterNames[] = {
33 static const EnumEntry RegisterNames_X86[] = {
34 #define CV_REGISTERS_X86
3435 #define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name),
3536 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
3637 #undef CV_REGISTER
38 #undef CV_REGISTERS_X86
39 };
40
41 static const EnumEntry RegisterNames_ARM64[] = {
42 #define CV_REGISTERS_ARM64
43 #define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name),
44 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
45 #undef CV_REGISTER
46 #undef CV_REGISTERS_ARM64
3747 };
3848
3949 static const EnumEntry PublicSymFlagNames[] = {
170180 CV_ENUM_CLASS_ENT(CPUType, ARM_XMAC),
171181 CV_ENUM_CLASS_ENT(CPUType, ARM_WMMX),
172182 CV_ENUM_CLASS_ENT(CPUType, ARM7),
183 CV_ENUM_CLASS_ENT(CPUType, ARM64),
173184 CV_ENUM_CLASS_ENT(CPUType, Omni),
174185 CV_ENUM_CLASS_ENT(CPUType, Ia64),
175186 CV_ENUM_CLASS_ENT(CPUType, Ia64_2),
299310 return makeArrayRef(TypeLeafNames);
300311 }
301312
302 ArrayRef> getRegisterNames() {
303 return makeArrayRef(RegisterNames);
313 ArrayRef> getRegisterNames(CPUType Cpu) {
314 if (Cpu == CPUType::ARM64) {
315 return makeArrayRef(RegisterNames_ARM64);
316 }
317 return makeArrayRef(RegisterNames_X86);
304318 }
305319
306320 ArrayRef> getPublicSymFlagNames() {
324324 Error CVSymbolDumperImpl::visitKnownRecord(
325325 CVSymbol &CVR, DefRangeRegisterRelSym &DefRangeRegisterRel) {
326326 W.printEnum("BaseRegister", uint16_t(DefRangeRegisterRel.Hdr.Register),
327 getRegisterNames());
327 getRegisterNames(CompilationCPUType));
328328 W.printBoolean("HasSpilledUDTMember",
329329 DefRangeRegisterRel.hasSpilledUDTMember());
330330 W.printNumber("OffsetInParent", DefRangeRegisterRel.offsetInParent());
338338 Error CVSymbolDumperImpl::visitKnownRecord(
339339 CVSymbol &CVR, DefRangeRegisterSym &DefRangeRegister) {
340340 W.printEnum("Register", uint16_t(DefRangeRegister.Hdr.Register),
341 getRegisterNames());
341 getRegisterNames(CompilationCPUType));
342342 W.printNumber("MayHaveNoName", DefRangeRegister.Hdr.MayHaveNoName);
343343 printLocalVariableAddrRange(DefRangeRegister.Range,
344344 DefRangeRegister.getRelocationOffset());
349349 Error CVSymbolDumperImpl::visitKnownRecord(
350350 CVSymbol &CVR, DefRangeSubfieldRegisterSym &DefRangeSubfieldRegister) {
351351 W.printEnum("Register", uint16_t(DefRangeSubfieldRegister.Hdr.Register),
352 getRegisterNames());
352 getRegisterNames(CompilationCPUType));
353353 W.printNumber("MayHaveNoName", DefRangeSubfieldRegister.Hdr.MayHaveNoName);
354354 W.printNumber("OffsetInParent", DefRangeSubfieldRegister.Hdr.OffsetInParent);
355355 printLocalVariableAddrRange(DefRangeSubfieldRegister.Range,
402402 FrameCookie.getRelocationOffset(),
403403 FrameCookie.CodeOffset, &LinkageName);
404404 }
405 W.printEnum("Register", uint16_t(FrameCookie.Register), getRegisterNames());
405 W.printEnum("Register", uint16_t(FrameCookie.Register),
406 getRegisterNames(CompilationCPUType));
406407 W.printEnum("CookieKind", uint16_t(FrameCookie.CookieKind),
407408 getFrameCookieKindNames());
408409 W.printHex("Flags", FrameCookie.Flags);
423424 getFrameProcSymFlagNames());
424425 W.printEnum("LocalFramePtrReg",
425426 uint16_t(FrameProc.getLocalFramePtrReg(CompilationCPUType)),
426 getRegisterNames());
427 getRegisterNames(CompilationCPUType));
427428 W.printEnum("ParamFramePtrReg",
428429 uint16_t(FrameProc.getParamFramePtrReg(CompilationCPUType)),
429 getRegisterNames());
430 getRegisterNames(CompilationCPUType));
430431 return Error::success();
431432 }
432433
504505 Error CVSymbolDumperImpl::visitKnownRecord(CVSymbol &CVR,
505506 RegisterSym &Register) {
506507 printTypeIndex("Type", Register.Index);
507 W.printEnum("Seg", uint16_t(Register.Register), getRegisterNames());
508 W.printEnum("Seg", uint16_t(Register.Register),
509 getRegisterNames(CompilationCPUType));
508510 W.printString("Name", Register.Name);
509511 return Error::success();
510512 }
598600 RegRelativeSym &RegRel) {
599601 W.printHex("Offset", RegRel.Offset);
600602 printTypeIndex("Type", RegRel.Type);
601 W.printEnum("Register", uint16_t(RegRel.Register), getRegisterNames());
603 W.printEnum("Register", uint16_t(RegRel.Register),
604 getRegisterNames(CompilationCPUType));
602605 W.printString("VarName", RegRel.Name);
603606 return Error::success();
604607 }
116116 }
117117
118118 raw_ostream &llvm::pdb::operator<<(raw_ostream &OS,
119 const codeview::RegisterId &Reg) {
120 switch (Reg) {
121 #define CV_REGISTER(name, val) case codeview::RegisterId::name: OS << #name; return OS;
119 const llvm::codeview::CPURegister &CpuReg) {
120 if (CpuReg.Cpu == llvm::codeview::CPUType::ARM64) {
121 switch (CpuReg.Reg) {
122 #define CV_REGISTERS_ARM64
123 #define CV_REGISTER(name, val) \
124 case codeview::RegisterId::name: \
125 OS << #name; \
126 return OS;
122127 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
123128 #undef CV_REGISTER
124 }
125 OS << static_cast(Reg);
129 #undef CV_REGISTERS_ARM64
130
131 default:
132 break;
133 }
134 } else {
135 switch (CpuReg.Reg) {
136 #define CV_REGISTERS_X86
137 #define CV_REGISTER(name, val) \
138 case codeview::RegisterId::name: \
139 OS << #name; \
140 return OS;
141 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
142 #undef CV_REGISTER
143 #undef CV_REGISTERS_X86
144
145 default:
146 break;
147 }
148 }
149 OS << static_cast(CpuReg.Reg);
126150 return OS;
127151 }
128152
146146 }
147147
148148 void ScalarEnumerationTraits::enumeration(IO &io, RegisterId &Reg) {
149 auto RegNames = getRegisterNames();
149 auto RegNames = getRegisterNames(CPUType::X64);
150150 for (const auto &E : RegNames) {
151151 io.enumCase(Reg, E.Name.str().c_str(), static_cast(E.Value));
152152 }
1616 #include "MCTargetDesc/AArch64AddressingModes.h"
1717 #include "MCTargetDesc/AArch64InstPrinter.h"
1818 #include "TargetInfo/AArch64TargetInfo.h"
19 #include "llvm/DebugInfo/CodeView/CodeView.h"
1920 #include "llvm/MC/MCAsmBackend.h"
2021 #include "llvm/MC/MCCodeEmitter.h"
2122 #include "llvm/MC/MCInstrAnalysis.h"
5556 }
5657
5758 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
58 for (unsigned Reg = AArch64::NoRegister + 1;
59 Reg < AArch64::NUM_TARGET_REGS; ++Reg) {
60 unsigned CV = MRI->getEncodingValue(Reg);
61 MRI->mapLLVMRegToCVReg(Reg, CV);
62 }
59 // Mapping from CodeView to MC register id.
60 static const struct {
61 codeview::RegisterId CVReg;
62 MCPhysReg Reg;
63 } RegMap[] = {
64 {codeview::RegisterId::ARM64_W0, AArch64::W0},
65 {codeview::RegisterId::ARM64_W1, AArch64::W1},
66 {codeview::RegisterId::ARM64_W2, AArch64::W2},
67 {codeview::RegisterId::ARM64_W3, AArch64::W3},
68 {codeview::RegisterId::ARM64_W4, AArch64::W4},
69 {codeview::RegisterId::ARM64_W5, AArch64::W5},
70 {codeview::RegisterId::ARM64_W6, AArch64::W6},
71 {codeview::RegisterId::ARM64_W7, AArch64::W7},
72 {codeview::RegisterId::ARM64_W8, AArch64::W8},
73 {codeview::RegisterId::ARM64_W9, AArch64::W9},
74 {codeview::RegisterId::ARM64_W10, AArch64::W10},
75 {codeview::RegisterId::ARM64_W11, AArch64::W11},
76 {codeview::RegisterId::ARM64_W12, AArch64::W12},
77 {codeview::RegisterId::ARM64_W13, AArch64::W13},
78 {codeview::RegisterId::ARM64_W14, AArch64::W14},
79 {codeview::RegisterId::ARM64_W15, AArch64::W15},
80 {codeview::RegisterId::ARM64_W16, AArch64::W16},
81 {codeview::RegisterId::ARM64_W17, AArch64::W17},
82 {codeview::RegisterId::ARM64_W18, AArch64::W18},
83 {codeview::RegisterId::ARM64_W19, AArch64::W19},
84 {codeview::RegisterId::ARM64_W20, AArch64::W20},
85 {codeview::RegisterId::ARM64_W21, AArch64::W21},
86 {codeview::RegisterId::ARM64_W22, AArch64::W22},
87 {codeview::RegisterId::ARM64_W23, AArch64::W23},
88 {codeview::RegisterId::ARM64_W24, AArch64::W24},
89 {codeview::RegisterId::ARM64_W25, AArch64::W25},
90 {codeview::RegisterId::ARM64_W26, AArch64::W26},
91 {codeview::RegisterId::ARM64_W27, AArch64::W27},
92 {codeview::RegisterId::ARM64_W28, AArch64::W28},
93 {codeview::RegisterId::ARM64_W29, AArch64::W29},
94 {codeview::RegisterId::ARM64_W30, AArch64::W30},
95 {codeview::RegisterId::ARM64_WZR, AArch64::WZR},
96 {codeview::RegisterId::ARM64_X0, AArch64::X0},
97 {codeview::RegisterId::ARM64_X1, AArch64::X1},
98 {codeview::RegisterId::ARM64_X2, AArch64::X2},
99 {codeview::RegisterId::ARM64_X3, AArch64::X3},
100 {codeview::RegisterId::ARM64_X4, AArch64::X4},
101 {codeview::RegisterId::ARM64_X5, AArch64::X5},
102 {codeview::RegisterId::ARM64_X6, AArch64::X6},
103 {codeview::RegisterId::ARM64_X7, AArch64::X7},
104 {codeview::RegisterId::ARM64_X8, AArch64::X8},
105 {codeview::RegisterId::ARM64_X9, AArch64::X9},
106 {codeview::RegisterId::ARM64_X10, AArch64::X10},
107 {codeview::RegisterId::ARM64_X11, AArch64::X11},
108 {codeview::RegisterId::ARM64_X12, AArch64::X12},
109 {codeview::RegisterId::ARM64_X13, AArch64::X13},
110 {codeview::RegisterId::ARM64_X14, AArch64::X14},
111 {codeview::RegisterId::ARM64_X15, AArch64::X15},
112 {codeview::RegisterId::ARM64_X16, AArch64::X16},
113 {codeview::RegisterId::ARM64_X17, AArch64::X17},
114 {codeview::RegisterId::ARM64_X18, AArch64::X18},
115 {codeview::RegisterId::ARM64_X19, AArch64::X19},
116 {codeview::RegisterId::ARM64_X20, AArch64::X20},
117 {codeview::RegisterId::ARM64_X21, AArch64::X21},
118 {codeview::RegisterId::ARM64_X22, AArch64::X22},
119 {codeview::RegisterId::ARM64_X23, AArch64::X23},
120 {codeview::RegisterId::ARM64_X24, AArch64::X24},
121 {codeview::RegisterId::ARM64_X25, AArch64::X25},
122 {codeview::RegisterId::ARM64_X26, AArch64::X26},
123 {codeview::RegisterId::ARM64_X27, AArch64::X27},
124 {codeview::RegisterId::ARM64_X28, AArch64::X28},
125 {codeview::RegisterId::ARM64_FP, AArch64::FP},
126 {codeview::RegisterId::ARM64_LR, AArch64::LR},
127 {codeview::RegisterId::ARM64_SP, AArch64::SP},
128 {codeview::RegisterId::ARM64_ZR, AArch64::XZR},
129 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},
130 {codeview::RegisterId::ARM64_S0, AArch64::S0},
131 {codeview::RegisterId::ARM64_S1, AArch64::S1},
132 {codeview::RegisterId::ARM64_S2, AArch64::S2},
133 {codeview::RegisterId::ARM64_S3, AArch64::S3},
134 {codeview::RegisterId::ARM64_S4, AArch64::S4},
135 {codeview::RegisterId::ARM64_S5, AArch64::S5},
136 {codeview::RegisterId::ARM64_S6, AArch64::S6},
137 {codeview::RegisterId::ARM64_S7, AArch64::S7},
138 {codeview::RegisterId::ARM64_S8, AArch64::S8},
139 {codeview::RegisterId::ARM64_S9, AArch64::S9},
140 {codeview::RegisterId::ARM64_S10, AArch64::S10},
141 {codeview::RegisterId::ARM64_S11, AArch64::S11},
142 {codeview::RegisterId::ARM64_S12, AArch64::S12},
143 {codeview::RegisterId::ARM64_S13, AArch64::S13},
144 {codeview::RegisterId::ARM64_S14, AArch64::S14},
145 {codeview::RegisterId::ARM64_S15, AArch64::S15},
146 {codeview::RegisterId::ARM64_S16, AArch64::S16},
147 {codeview::RegisterId::ARM64_S17, AArch64::S17},
148 {codeview::RegisterId::ARM64_S18, AArch64::S18},
149 {codeview::RegisterId::ARM64_S19, AArch64::S19},
150 {codeview::RegisterId::ARM64_S20, AArch64::S20},
151 {codeview::RegisterId::ARM64_S21, AArch64::S21},
152 {codeview::RegisterId::ARM64_S22, AArch64::S22},
153 {codeview::RegisterId::ARM64_S23, AArch64::S23},
154 {codeview::RegisterId::ARM64_S24, AArch64::S24},
155 {codeview::RegisterId::ARM64_S25, AArch64::S25},
156 {codeview::RegisterId::ARM64_S26, AArch64::S26},
157 {codeview::RegisterId::ARM64_S27, AArch64::S27},
158 {codeview::RegisterId::ARM64_S28, AArch64::S28},
159 {codeview::RegisterId::ARM64_S29, AArch64::S29},
160 {codeview::RegisterId::ARM64_S30, AArch64::S30},
161 {codeview::RegisterId::ARM64_S31, AArch64::S31},
162 {codeview::RegisterId::ARM64_D0, AArch64::D0},
163 {codeview::RegisterId::ARM64_D1, AArch64::D1},
164 {codeview::RegisterId::ARM64_D2, AArch64::D2},
165 {codeview::RegisterId::ARM64_D3, AArch64::D3},
166 {codeview::RegisterId::ARM64_D4, AArch64::D4},
167 {codeview::RegisterId::ARM64_D5, AArch64::D5},
168 {codeview::RegisterId::ARM64_D6, AArch64::D6},
169 {codeview::RegisterId::ARM64_D7, AArch64::D7},
170 {codeview::RegisterId::ARM64_D8, AArch64::D8},
171 {codeview::RegisterId::ARM64_D9, AArch64::D9},
172 {codeview::RegisterId::ARM64_D10, AArch64::D10},
173 {codeview::RegisterId::ARM64_D11, AArch64::D11},
174 {codeview::RegisterId::ARM64_D12, AArch64::D12},
175 {codeview::RegisterId::ARM64_D13, AArch64::D13},
176 {codeview::RegisterId::ARM64_D14, AArch64::D14},
177 {codeview::RegisterId::ARM64_D15, AArch64::D15},
178 {codeview::RegisterId::ARM64_D16, AArch64::D16},
179 {codeview::RegisterId::ARM64_D17, AArch64::D17},
180 {codeview::RegisterId::ARM64_D18, AArch64::D18},
181 {codeview::RegisterId::ARM64_D19, AArch64::D19},
182 {codeview::RegisterId::ARM64_D20, AArch64::D20},
183 {codeview::RegisterId::ARM64_D21, AArch64::D21},
184 {codeview::RegisterId::ARM64_D22, AArch64::D22},
185 {codeview::RegisterId::ARM64_D23, AArch64::D23},
186 {codeview::RegisterId::ARM64_D24, AArch64::D24},
187 {codeview::RegisterId::ARM64_D25, AArch64::D25},
188 {codeview::RegisterId::ARM64_D26, AArch64::D26},
189 {codeview::RegisterId::ARM64_D27, AArch64::D27},
190 {codeview::RegisterId::ARM64_D28, AArch64::D28},
191 {codeview::RegisterId::ARM64_D29, AArch64::D29},
192 {codeview::RegisterId::ARM64_D30, AArch64::D30},
193 {codeview::RegisterId::ARM64_D31, AArch64::D31},
194 {codeview::RegisterId::ARM64_Q0, AArch64::Q0},
195 {codeview::RegisterId::ARM64_Q1, AArch64::Q1},
196 {codeview::RegisterId::ARM64_Q2, AArch64::Q2},
197 {codeview::RegisterId::ARM64_Q3, AArch64::Q3},
198 {codeview::RegisterId::ARM64_Q4, AArch64::Q4},
199 {codeview::RegisterId::ARM64_Q5, AArch64::Q5},
200 {codeview::RegisterId::ARM64_Q6, AArch64::Q6},
201 {codeview::RegisterId::ARM64_Q7, AArch64::Q7},
202 {codeview::RegisterId::ARM64_Q8, AArch64::Q8},
203 {codeview::RegisterId::ARM64_Q9, AArch64::Q9},
204 {codeview::RegisterId::ARM64_Q10, AArch64::Q10},
205 {codeview::RegisterId::ARM64_Q11, AArch64::Q11},
206 {codeview::RegisterId::ARM64_Q12, AArch64::Q12},
207 {codeview::RegisterId::ARM64_Q13, AArch64::Q13},
208 {codeview::RegisterId::ARM64_Q14, AArch64::Q14},
209 {codeview::RegisterId::ARM64_Q15, AArch64::Q15},
210 {codeview::RegisterId::ARM64_Q16, AArch64::Q16},
211 {codeview::RegisterId::ARM64_Q17, AArch64::Q17},
212 {codeview::RegisterId::ARM64_Q18, AArch64::Q18},
213 {codeview::RegisterId::ARM64_Q19, AArch64::Q19},
214 {codeview::RegisterId::ARM64_Q20, AArch64::Q20},
215 {codeview::RegisterId::ARM64_Q21, AArch64::Q21},
216 {codeview::RegisterId::ARM64_Q22, AArch64::Q22},
217 {codeview::RegisterId::ARM64_Q23, AArch64::Q23},
218 {codeview::RegisterId::ARM64_Q24, AArch64::Q24},
219 {codeview::RegisterId::ARM64_Q25, AArch64::Q25},
220 {codeview::RegisterId::ARM64_Q26, AArch64::Q26},
221 {codeview::RegisterId::ARM64_Q27, AArch64::Q27},
222 {codeview::RegisterId::ARM64_Q28, AArch64::Q28},
223 {codeview::RegisterId::ARM64_Q29, AArch64::Q29},
224 {codeview::RegisterId::ARM64_Q30, AArch64::Q30},
225 {codeview::RegisterId::ARM64_Q31, AArch64::Q31},
226
227 };
228 for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
229 MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast(RegMap[I].CVReg));
63230 }
64231
65232 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
0 ; RUN: llc < %s -filetype=obj | llvm-readobj --codeview - | FileCheck %s --check-prefix=OBJ
1
2 ; Generated from:
3 ; volatile int x;
4 ; int getint(void);
5 ; void putint(int);
6 ; static inline int inlineinc(int a) {
7 ; int b = a + 1;
8 ; ++x;
9 ; return b;
10 ; }
11 ; void f(int p) {
12 ; if (p) {
13 ; int a = getint();
14 ; int b = inlineinc(a);
15 ; putint(b);
16 ; } else {
17 ; int c = getint();
18 ; putint(c);
19 ; }
20 ; }
21
22
23 ; OBJ: DefRangeRegisterRelSym {
24 ; OBJ: Kind: S_DEFRANGE_REGISTER_REL (0x1145)
25 ; OBJ: BaseRegister: ARM64_SP (0x51)
26 ; OBJ: HasSpilledUDTMember: No
27 ; OBJ: OffsetInParent: 0
28 ; OBJ: BasePointerOffset: 12
29 ; OBJ: LocalVariableAddrRange {
30 ; OBJ: OffsetStart: .text+0x10
31 ; OBJ: ISectStart: 0x0
32 ; OBJ: Range: 0x2C
33 ; OBJ: }
34 ; OBJ: }
35
36 ; ModuleID = 't.cpp'
37 source_filename = "test/DebugInfo/COFF/register-variables-arm64.ll"
38 target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
39 target triple = "arm64-unknown-windows-msvc19.16.27023"
40
41 @x = common dso_local global i32 0, align 4, !dbg !0
42
43 ; Function Attrs: noinline nounwind optnone uwtable
44 define dso_local void @f(i32 %p) #0 !dbg !12 {
45 entry:
46 %p.addr = alloca i32, align 4
47 %a = alloca i32, align 4
48 %b = alloca i32, align 4
49 %c = alloca i32, align 4
50 store i32 %p, i32* %p.addr, align 4
51 call void @llvm.dbg.declare(metadata i32* %p.addr, metadata !15, metadata !DIExpression()), !dbg !16
52 %0 = load i32, i32* %p.addr, align 4, !dbg !17
53 %tobool = icmp ne i32 %0, 0, !dbg !17
54 br i1 %tobool, label %if.then, label %if.else, !dbg !17
55
56 if.then: ; preds = %entry
57 call void @llvm.dbg.declare(metadata i32* %a, metadata !18, metadata !DIExpression()), !dbg !21
58 %call = call i32 @getint(), !dbg !21
59 store i32 %call, i32* %a, align 4, !dbg !21
60 call void @llvm.dbg.declare(metadata i32* %b, metadata !22, metadata !DIExpression()), !dbg !23
61 %1 = load i32, i32* %a, align 4, !dbg !23
62 %call1 = call i32 @inlineinc(i32 %1), !dbg !23
63 store i32 %call1, i32* %b, align 4, !dbg !23
64 %2 = load i32, i32* %b, align 4, !dbg !24
65 call void @putint(i32 %2), !dbg !24
66 br label %if.end, !dbg !25
67
68 if.else: ; preds = %entry
69 call void @llvm.dbg.declare(metadata i32* %c, metadata !26, metadata !DIExpression()), !dbg !28
70 %call2 = call i32 @getint(), !dbg !28
71 store i32 %call2, i32* %c, align 4, !dbg !28
72 %3 = load i32, i32* %c, align 4, !dbg !29
73 call void @putint(i32 %3), !dbg !29
74 br label %if.end, !dbg !30
75
76 if.end: ; preds = %if.else, %if.then
77 ret void, !dbg !31
78 }
79
80 ; Function Attrs: nounwind readnone speculatable
81 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
82
83 declare dso_local i32 @getint() #2
84
85 ; Function Attrs: noinline nounwind optnone uwtable
86 define internal i32 @inlineinc(i32 %a) #0 !dbg !32 {
87 entry:
88 %a.addr = alloca i32, align 4
89 %b = alloca i32, align 4
90 store i32 %a, i32* %a.addr, align 4
91 call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !35, metadata !DIExpression()), !dbg !36
92 call void @llvm.dbg.declare(metadata i32* %b, metadata !37, metadata !DIExpression()), !dbg !38
93 %0 = load i32, i32* %a.addr, align 4, !dbg !38
94 %add = add nsw i32 %0, 1, !dbg !38
95 store i32 %add, i32* %b, align 4, !dbg !38
96 %1 = load volatile i32, i32* @x, align 4, !dbg !39
97 %inc = add nsw i32 %1, 1, !dbg !39
98 store volatile i32 %inc, i32* @x, align 4, !dbg !39
99 %2 = load i32, i32* %b, align 4, !dbg !40
100 ret i32 %2, !dbg !40
101 }
102
103 declare dso_local void @putint(i32) #2
104
105 !llvm.dbg.cu = !{!2}
106 !llvm.module.flags = !{!8, !9, !10}
107
108 !0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
109 !1 = distinct !DIGlobalVariable(name: "x", scope: !2, file: !3, line: 1, type: !6, isLocal: false, isDefinition: true)
110 !2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 9.0.0 (trunk 361867) (llvm/trunk 361866)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, nameTableKind: None)
111 !3 = !DIFile(filename: "t.c", directory: "S:\5CLLVM\5Csvn\5Csbr\5Cbin", checksumkind: CSK_MD5, checksum: "734c448e95a6204a439a847ed063e5ce")
112 !4 = !{}
113 !5 = !{!0}
114 !6 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !7)
115 !7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
116 !8 = !{i32 2, !"CodeView", i32 1}
117 !9 = !{i32 2, !"Debug Info Version", i32 3}
118 !10 = !{i32 1, !"wchar_size", i32 2}
119 !11 = !{!"clang version 9.0.0 (trunk 361867) (llvm/trunk 361866)"}
120 !12 = distinct !DISubprogram(name: "f", scope: !3, file: !3, line: 9, type: !13, scopeLine: 9, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !2, retainedNodes: !4)
121 !13 = !DISubroutineType(types: !14)
122 !14 = !{null, !7}
123 !15 = !DILocalVariable(name: "p", arg: 1, scope: !12, file: !3, line: 9, type: !7)
124 !16 = !DILocation(line: 9, scope: !12)
125 !17 = !DILocation(line: 10, scope: !12)
126 !18 = !DILocalVariable(name: "a", scope: !19, file: !3, line: 11, type: !7)
127 !19 = distinct !DILexicalBlock(scope: !20, file: !3, line: 10)
128 !20 = distinct !DILexicalBlock(scope: !12, file: !3, line: 10)
129 !21 = !DILocation(line: 11, scope: !19)
130 !22 = !DILocalVariable(name: "b", scope: !19, file: !3, line: 12, type: !7)
131 !23 = !DILocation(line: 12, scope: !19)
132 !24 = !DILocation(line: 13, scope: !19)
133 !25 = !DILocation(line: 14, scope: !19)
134 !26 = !DILocalVariable(name: "c", scope: !27, file: !3, line: 15, type: !7)
135 !27 = distinct !DILexicalBlock(scope: !20, file: !3, line: 14)
136 !28 = !DILocation(line: 15, scope: !27)
137 !29 = !DILocation(line: 16, scope: !27)
138 !30 = !DILocation(line: 17, scope: !27)
139 !31 = !DILocation(line: 18, scope: !12)
140 !32 = distinct !DISubprogram(name: "inlineinc", scope: !3, file: !3, line: 4, type: !33, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !2, retainedNodes: !4)
141 !33 = !DISubroutineType(types: !34)
142 !34 = !{!7, !7}
143 !35 = !DILocalVariable(name: "a", arg: 1, scope: !32, file: !3, line: 4, type: !7)
144 !36 = !DILocation(line: 4, scope: !32)
145 !37 = !DILocalVariable(name: "b", scope: !32, file: !3, line: 5, type: !7)
146 !38 = !DILocation(line: 5, scope: !32)
147 !39 = !DILocation(line: 6, scope: !32)
148 !40 = !DILocation(line: 7, scope: !32)
286286 return formatUnknownEnum(Kind);
287287 }
288288
289 static std::string formatRegisterId(RegisterId Id) {
290 switch (Id) {
289 static std::string formatRegisterId(RegisterId Id, CPUType Cpu) {
290 if (Cpu == CPUType::ARM64) {
291 switch (Id) {
292 #define CV_REGISTERS_ARM64
291293 #define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name)
292294 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
293295 #undef CV_REGISTER
296 #undef CV_REGISTERS_ARM64
297
298 default:
299 break;
300 }
301 } else {
302 switch (Id) {
303 #define CV_REGISTERS_X86
304 #define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name)
305 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
306 #undef CV_REGISTER
307 #undef CV_REGISTERS_X86
308
309 default:
310 break;
311 }
294312 }
295313 return formatUnknownEnum(Id);
296314 }
297315
298 static std::string formatRegisterId(uint16_t Reg16) {
299 return formatRegisterId(RegisterId(Reg16));
300 }
301
302 static std::string formatRegisterId(ulittle16_t &Reg16) {
303 return formatRegisterId(uint16_t(Reg16));
316 static std::string formatRegisterId(uint16_t Reg16, CPUType Cpu) {
317 return formatRegisterId(RegisterId(Reg16), Cpu);
318 }
319
320 static std::string formatRegisterId(ulittle16_t &Reg16, CPUType Cpu) {
321 return formatRegisterId(uint16_t(Reg16), Cpu);
304322 }
305323
306324 static std::string formatRange(LocalVariableAddrRange Range) {
561579 AutoIndent Indent(P, 7);
562580 P.formatLine("register = {0}, offset = {1}, offset in parent = {2}, has "
563581 "spilled udt = {3}",
564 formatRegisterId(Def.Hdr.Register),
582 formatRegisterId(Def.Hdr.Register, CompilationCPU),
565583 int32_t(Def.Hdr.BasePointerOffset), Def.offsetInParent(),
566584 Def.hasSpilledUDTMember());
567585 P.formatLine("range = {0}, gaps = {1}", formatRange(Def.Range),
574592 AutoIndent Indent(P, 7);
575593 P.formatLine("register = {0}, may have no name = {1}, range start = "
576594 "{2}, length = {3}",
577 formatRegisterId(DefRangeRegister.Hdr.Register),
595 formatRegisterId(DefRangeRegister.Hdr.Register, CompilationCPU),
578596 bool(DefRangeRegister.Hdr.MayHaveNoName),
579597 formatSegmentOffset(DefRangeRegister.Range.ISectStart,
580598 DefRangeRegister.Range.OffsetStart),
589607 AutoIndent Indent(P, 7);
590608 bool NoName = !!(Def.Hdr.MayHaveNoName == 0);
591609 P.formatLine("register = {0}, may have no name = {1}, offset in parent = {2}",
592 formatRegisterId(Def.Hdr.Register), NoName,
610 formatRegisterId(Def.Hdr.Register, CompilationCPU), NoName,
593611 uint32_t(Def.Hdr.OffsetInParent));
594612 P.formatLine("range = {0}, gaps = {1}", formatRange(Def.Range),
595613 formatGaps(P.getIndentLevel() + 9, Def.Gaps));
616634 Error MinimalSymbolDumper::visitKnownRecord(CVSymbol &CVR, FrameCookieSym &FC) {
617635 AutoIndent Indent(P, 7);
618636 P.formatLine("code offset = {0}, Register = {1}, kind = {2}, flags = {3}",
619 FC.CodeOffset, formatRegisterId(FC.Register),
637 FC.CodeOffset, formatRegisterId(FC.Register, CompilationCPU),
620638 formatCookieKind(FC.CookieKind), FC.Flags);
621639 return Error::success();
622640 }
630648 FP.BytesOfCalleeSavedRegisters,
631649 formatSegmentOffset(FP.SectionIdOfExceptionHandler,
632650 FP.OffsetOfExceptionHandler));
633 P.formatLine("local fp reg = {0}, param fp reg = {1}",
634 formatRegisterId(FP.getLocalFramePtrReg(CompilationCPU)),
635 formatRegisterId(FP.getParamFramePtrReg(CompilationCPU)));
651 P.formatLine(
652 "local fp reg = {0}, param fp reg = {1}",
653 formatRegisterId(FP.getLocalFramePtrReg(CompilationCPU), CompilationCPU),
654 formatRegisterId(FP.getParamFramePtrReg(CompilationCPU), CompilationCPU));
636655 P.formatLine("flags = {0}",
637656 formatFrameProcedureOptions(P.getIndentLevel() + 9, FP.Flags));
638657 return Error::success();
740759 P.format(" `{0}`", Register.Name);
741760 AutoIndent Indent(P, 7);
742761 P.formatLine("register = {0}, type = {1}",
743 formatRegisterId(Register.Register), typeIndex(Register.Index));
762 formatRegisterId(Register.Register, CompilationCPU),
763 typeIndex(Register.Index));
744764 return Error::success();
745765 }
746766
828848 RegRelativeSym &RegRel) {
829849 P.format(" `{0}`", RegRel.Name);
830850 AutoIndent Indent(P, 7);
831 P.formatLine("type = {0}, register = {1}, offset = {2}",
832 typeIndex(RegRel.Type), formatRegisterId(RegRel.Register),
833 RegRel.Offset);
851 P.formatLine(
852 "type = {0}, register = {1}, offset = {2}", typeIndex(RegRel.Type),
853 formatRegisterId(RegRel.Register, CompilationCPU), RegRel.Offset);
834854 return Error::success();
835855 }
836856
4949 io.enumCase(Value, "SH3DSP", PDB_Machine::SH3DSP);
5050 io.enumCase(Value, "Thumb", PDB_Machine::Thumb);
5151 io.enumCase(Value, "WceMipsV2", PDB_Machine::WceMipsV2);
52 io.enumCase(Value, "Arm64", PDB_Machine::Arm64);
5253 }
5354 };
5455
137137
138138 if (Symbol.hasFramePointer()) {
139139 WithColor(Printer, PDB_ColorItem::Register).get()
140 << Symbol.getLocalBasePointerRegisterId();
140 << CPURegister{Symbol.getRawSymbol().getPlatform(),
141 Symbol.getLocalBasePointerRegisterId()};
141142 } else {
142143 WithColor(Printer, PDB_ColorItem::Register).get() << "FPO";
143144 }