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[ARM] First MVE instructions: scalar shifts. This introduces a new decoding table for MVE instructions, and starts by adding the family of scalar shift instructions that are part of the MVE architecture extension: saturating shifts within a single GPR, and long shifts across a pair of GPRs (both saturating and normal). Some of these shift instructions have only 3-bit register fields in the encoding, with the low bit fixed. So they can only address an odd or even numbered GPR (depending on the operand), and therefore I add two new register classes, GPREven and GPROdd. Differential Revision: https://reviews.llvm.org/D62668 Change-Id: Iad95d5f83d26aef70c674027a184a6b1e0098d33 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363051 91177308-0d34-0410-b5e6-96231b3b80d8 Mikhail Maltsev 1 year, 1 month ago
9 changed file(s) with 533 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
57585758 include "ARMInstrNEON.td"
57595759
57605760 //===----------------------------------------------------------------------===//
5761 // MVE Support
5762 //
5763
5764 include "ARMInstrMVE.td"
5765
5766 //===----------------------------------------------------------------------===//
57615767 // Assembler aliases
57625768 //
57635769
0 //===-- ARMInstrMVE.td - MVE support for ARM ---------------*- tablegen -*-===//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This file describes the ARM MVE instruction set.
9 //
10 //===----------------------------------------------------------------------===//
11
12 class MVE_MI_with_pred
13 string ops, string cstr, list pattern>
14 : Thumb2I
15 pattern>,
16 Requires<[HasV8_1MMainline, HasMVEInt]> {
17 let D = MVEDomain;
18 let DecoderNamespace = "MVE";
19 }
20
21 class t2MVEShift
22 list pattern=[]>
23 : MVE_MI_with_pred {
24 let Inst{31-20} = 0b111010100101;
25 let Inst{8} = 0b1;
26
27 }
28
29 class t2MVEShiftSingleReg
30 list pattern=[]>
31 : t2MVEShift {
32 bits<4> RdaDest;
33
34 let Inst{19-16} = RdaDest{3-0};
35 }
36
37 class t2MVEShiftSRegImm op5_4, list pattern=[]>
38 : t2MVEShiftSingleReg
39 "$RdaSrc, $imm", "$RdaDest = $RdaSrc", pattern> {
40 bits<5> imm;
41
42 let Inst{15} = 0b0;
43 let Inst{14-12} = imm{4-2};
44 let Inst{11-8} = 0b1111;
45 let Inst{7-6} = imm{1-0};
46 let Inst{5-4} = op5_4{1-0};
47 let Inst{3-0} = 0b1111;
48 }
49
50 def t2SQSHL : t2MVEShiftSRegImm<"sqshl", 0b11>;
51 def t2SRSHR : t2MVEShiftSRegImm<"srshr", 0b10>;
52 def t2UQSHL : t2MVEShiftSRegImm<"uqshl", 0b00>;
53 def t2URSHR : t2MVEShiftSRegImm<"urshr", 0b01>;
54
55 class t2MVEShiftSRegReg op5_4, list pattern=[]>
56 : t2MVEShiftSingleReg
57 "$RdaSrc, $Rm", "$RdaDest = $RdaSrc", pattern> {
58 bits<4> Rm;
59
60 let Inst{15-12} = Rm{3-0};
61 let Inst{11-8} = 0b1111;
62 let Inst{7-6} = 0b00;
63 let Inst{5-4} = op5_4{1-0};
64 let Inst{3-0} = 0b1101;
65 }
66
67 def t2SQRSHR : t2MVEShiftSRegReg<"sqrshr", 0b10>;
68 def t2UQRSHL : t2MVEShiftSRegReg<"uqrshl", 0b00>;
69
70 class t2MVEShiftDoubleReg
71 list pattern=[]>
72 : t2MVEShift
73 pattern> {
74 bits<4> RdaLo;
75 bits<4> RdaHi;
76
77 let Inst{19-17} = RdaLo{3-1};
78 let Inst{11-9} = RdaHi{3-1};
79 }
80
81 class t2MVEShiftDRegImm op5_4, bit op16, list pattern=[]>
82 : t2MVEShiftDoubleReg
83 long_shift:$imm), "$RdaLo, $RdaHi, $imm",
84 "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src", pattern> {
85 bits<5> imm;
86
87 let Inst{16} = op16;
88 let Inst{15} = 0b0;
89 let Inst{14-12} = imm{4-2};
90 let Inst{7-6} = imm{1-0};
91 let Inst{5-4} = op5_4{1-0};
92 let Inst{3-0} = 0b1111;
93 }
94
95 class t2MVEShiftDRegReg pattern=[]>
96 : t2MVEShiftDoubleReg
97 "$RdaLo, $RdaHi, $Rm",
98 "@earlyclobber $RdaHi,@earlyclobber $RdaLo,$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
99 pattern> {
100 bits<4> Rm;
101
102 let Inst{16} = op16;
103 let Inst{15-12} = Rm{3-0};
104 let Inst{7-6} = 0b00;
105 let Inst{5} = op5;
106 let Inst{4} = 0b0;
107 let Inst{3-0} = 0b1101;
108
109 // Custom decoder method because of the following overlapping encodings:
110 // ASRL and SQRSHR
111 // LSLL and UQRSHL
112 // SQRSHRL and SQRSHR
113 // UQRSHLL and UQRSHL
114 let DecoderMethod = "DecodeMVEOverlappingLongShift";
115 }
116
117 def t2ASRLr : t2MVEShiftDRegReg<"asrl", 0b1, 0b0>;
118 def t2ASRLi : t2MVEShiftDRegImm<"asrl", 0b10, ?>;
119 def t2LSLLr : t2MVEShiftDRegReg<"lsll", 0b0, 0b0>;
120 def t2LSLLi : t2MVEShiftDRegImm<"lsll", 0b00, ?>;
121 def t2LSRL : t2MVEShiftDRegImm<"lsrl", 0b01, ?>;
122
123 def t2SQRSHRL : t2MVEShiftDRegReg<"sqrshrl", 0b1, 0b1>;
124 def t2SQSHLL : t2MVEShiftDRegImm<"sqshll", 0b11, 0b1>;
125 def t2SRSHRL : t2MVEShiftDRegImm<"srshrl", 0b10, 0b1>;
126
127 def t2UQRSHLL : t2MVEShiftDRegReg<"uqrshll", 0b0, 0b1>;
128 def t2UQSHLL : t2MVEShiftDRegImm<"uqshll", 0b00, 0b1>;
129 def t2URSHRL : t2MVEShiftDRegImm<"urshrl", 0b01, 0b1>;
3636 let PrintMethod = "printShiftImmOperand";
3737 let ParserMatchClass = ShifterImmAsmOperand;
3838 let DecoderMethod = "DecodeT2ShifterImmOperand";
39 }
40
41 def mve_shift_imm : AsmOperandClass {
42 let Name = "MVELongShift";
43 let RenderMethod = "addImmOperands";
44 let DiagnosticString = "operand must be an immediate in the range [1,32]";
45 }
46 def long_shift : Operand {
47 let ParserMatchClass = mve_shift_imm;
48 let DecoderMethod = "DecodeLongShiftOperand";
3949 }
4050
4151 // Shifted operands. No register controlled shifts for Thumb2.
180180 case tGPR_and_tcGPRRegClassID:
181181 case tcGPRRegClassID:
182182 case tGPRRegClassID:
183 case tGPREvenRegClassID:
184 case tGPROddRegClassID:
185 case tGPR_and_tGPREvenRegClassID:
186 case tGPR_and_tGPROddRegClassID:
187 case tGPREven_and_tcGPRRegClassID:
188 case tGPREven_and_tGPR_and_tcGPRRegClassID:
189 case tGPROdd_and_tcGPRRegClassID:
183190 return getRegBank(ARM::GPRRegBankID);
184191 case HPRRegClassID:
185192 case SPR_8RegClassID:
330330 }];
331331 }
332332
333 def tGPROdd : RegisterClass<"ARM", [i32], 32, (add R1, R3, R5, R7, R9, R11)> {
334 let AltOrders = [(and tGPROdd, tGPR)];
335 let AltOrderSelect = [{
336 return MF.getSubtarget().isThumb1Only();
337 }];
338 }
339
340 def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> {
341 let AltOrders = [(and tGPREven, tGPR)];
342 let AltOrderSelect = [{
343 return MF.getSubtarget().isThumb1Only();
344 }];
345 }
346
333347 // Condition code registers.
334348 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
335349 let CopyCost = -1; // Don't allow copying of status registers.
20452045 uint64_t Value = CE->getValue();
20462046
20472047 return (Value % Angle == Remainder && Value <= 270);
2048 }
2049
2050 bool isMVELongShift() const {
2051 if (!isImm()) return false;
2052 const MCConstantExpr *CE = dyn_cast(getImm());
2053 // Must be a constant.
2054 if (!CE) return false;
2055 uint64_t Value = CE->getValue();
2056 return Value >= 1 && Value <= 32;
20482057 }
20492058
20502059 bool isITCondCodeNoAL() const {
144144 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
145145 uint64_t Address, const void *Decoder);
146146 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
147 uint64_t Address, const void *Decoder);
148 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
149 uint64_t Address, const void *Decoder);
150 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
147151 uint64_t Address, const void *Decoder);
148152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
149153 unsigned RegNo, uint64_t Address,
431435 const void *Decoder);
432436 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
433437 const void *Decoder);
438 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
439 uint64_t Address,
440 const void *Decoder);
434441 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
435442 const void *Decoder);
436443 template
437444 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
438445 uint64_t Address,
439446 const void *Decoder);
447 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
448 uint64_t Address,
449 const void *Decoder);
440450 #include "ARMGenDisassemblerTables.inc"
441451
442452 static MCDisassembler *createARMDisassembler(const Target &T,
800810
801811 uint32_t Insn32 =
802812 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
813
814 Result =
815 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
816 if (Result != MCDisassembler::Fail) {
817 Size = 4;
818 Check(Result, AddThumbPredicate(MI));
819 return Result;
820 }
821
803822 Result =
804823 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
805824 if (Result != MCDisassembler::Fail) {
56425661 return S;
56435662 }
56445663
5664 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
5665 uint64_t Address,
5666 const void *Decoder) {
5667 DecodeStatus S = MCDisassembler::Success;
5668
5669 if (Val == 0)
5670 Val = 32;
5671
5672 Inst.addOperand(MCOperand::createImm(Val));
5673
5674 return S;
5675 }
5676
5677 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
5678 uint64_t Address, const void *Decoder) {
5679 if ((RegNo) + 1 > 11)
5680 return MCDisassembler::Fail;
5681
5682 unsigned Register = GPRDecoderTable[(RegNo) + 1];
5683 Inst.addOperand(MCOperand::createReg(Register));
5684 return MCDisassembler::Success;
5685 }
5686
5687 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
5688 uint64_t Address, const void *Decoder) {
5689 if ((RegNo) > 14)
5690 return MCDisassembler::Fail;
5691
5692 unsigned Register = GPRDecoderTable[(RegNo)];
5693 Inst.addOperand(MCOperand::createReg(Register));
5694 return MCDisassembler::Success;
5695 }
5696
56455697 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
56465698 const void *Decoder) {
56475699 DecodeStatus S = MCDisassembler::Success;
57255777
57265778 return S;
57275779 }
5780
5781 static DecodeStatus DecodeMVEOverlappingLongShift(
5782 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {
5783 DecodeStatus S = MCDisassembler::Success;
5784
5785 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
5786 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
5787 unsigned Rm = fieldFromInstruction(Insn, 12, 4);
5788
5789 if (RdaHi == 14) {
5790 // This value of RdaHi (really indicating pc, because RdaHi has to
5791 // be an odd-numbered register, so the low bit will be set by the
5792 // decode function below) indicates that we must decode as SQRSHR
5793 // or UQRSHL, which both have a single Rda register field with all
5794 // four bits.
5795 unsigned Rda = fieldFromInstruction(Insn, 16, 4);
5796
5797 switch (Inst.getOpcode()) {
5798 case ARM::t2ASRLr:
5799 case ARM::t2SQRSHRL:
5800 Inst.setOpcode(ARM::t2SQRSHR);
5801 break;
5802 case ARM::t2LSLLr:
5803 case ARM::t2UQRSHLL:
5804 Inst.setOpcode(ARM::t2UQRSHL);
5805 break;
5806 default:
5807 llvm_unreachable("Unexpected starting opcode!");
5808 }
5809
5810 // Rda as output parameter
5811 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
5812 return MCDisassembler::Fail;
5813
5814 // Rda again as input parameter
5815 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
5816 return MCDisassembler::Fail;
5817
5818 // Rm, the amount to shift by
5819 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
5820 return MCDisassembler::Fail;
5821
5822 return S;
5823 }
5824
5825 // Otherwise, we decode as whichever opcode our caller has already
5826 // put into Inst. Those all look the same:
5827
5828 // RdaLo,RdaHi as output parameters
5829 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
5830 return MCDisassembler::Fail;
5831 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
5832 return MCDisassembler::Fail;
5833
5834 // RdaLo,RdaHi again as input parameters
5835 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
5836 return MCDisassembler::Fail;
5837 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
5838 return MCDisassembler::Fail;
5839
5840 // Rm, the amount to shift by
5841 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
5842 return MCDisassembler::Fail;
5843
5844 return S;
5845 }
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \
1 # RUN: | FileCheck --check-prefix=CHECK %s
2 # RUN: FileCheck --check-prefix=ERROR < %t %s
3 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
4 # RUN: | FileCheck --check-prefix=CHECK %s
5 # RUN: FileCheck --check-prefix=ERROR < %t %s
6 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t \
7 # RUN: | FileCheck --check-prefix=CHECK-NOMVE %s
8 # RUN: FileCheck --check-prefix=ERROR-NOMVE < %t %s
9
10 # CHECK: asrl r0, r1, #23 @ encoding: [0x50,0xea,0xef,0x51]
11 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
12 asrl r0, r1, #23
13
14 # CHECK: asrl lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
15 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
16 asrl lr, r1, #27
17
18 # CHECK: it eq @ encoding: [0x08,0xbf]
19 # CHECK-NEXT: asrleq lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
20 it eq
21 asrleq lr, r1, #27
22
23 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid instruction
24 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
25 asrl r3, r2, #33
26
27 # ERROR: [[@LINE+3]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
28 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
29 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
30 asrl r0, r1, #33
31
32 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
33 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
34 asrl r0, r0, #32
35
36 # CHECK: asrl r0, r1, r4 @ encoding: [0x50,0xea,0x2d,0x41]
37 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
38 asrl r0, r1, r4
39
40 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
41 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
42 asrl r0, r0, r4
43
44 # The assembler will reject the above shifts when MVE is not supported,
45 # so the previous valid instruction will be IT EQ, so we need to add
46 # a NOPEQ:
47 nopeq
48
49 # CHECK: cinc lr, r2, lo @ encoding: [0x52,0xea,0x22,0x9e]
50 # CHECK-NOMVE: cinc lr, r2, lo @ encoding: [0x52,0xea,0x22,0x9e]
51 csinc lr, r2, r2, hs
52
53 # CHECK: cinc lr, r7, pl @ encoding: [0x57,0xea,0x47,0x9e]
54 # CHECK-NOMVE: cinc lr, r7, pl @ encoding: [0x57,0xea,0x47,0x9e]
55 cinc lr, r7, pl
56
57 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
58 # CHECK-NOMVE: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
59 cinv lr, r12, hs
60
61 # CHECK: cneg lr, r10, hs @ encoding: [0x5a,0xea,0x3a,0xbe]
62 # CHECK-NOMVE: cneg lr, r10, hs @ encoding: [0x5a,0xea,0x3a,0xbe]
63 csneg lr, r10, r10, lo
64
65 # CHECK: csel r9, r9, r11, vc @ encoding: [0x59,0xea,0x7b,0x89]
66 # CHECK-NOMVE: csel r9, r9, r11, vc @ encoding: [0x59,0xea,0x7b,0x89]
67 csel r9, r9, r11, vc
68
69 # CHECK: cset lr, eq @ encoding: [0x5f,0xea,0x1f,0x9e]
70 # CHECK-NOMVE: cset lr, eq @ encoding: [0x5f,0xea,0x1f,0x9e]
71 cset lr, eq
72
73 # CHECK: csetm lr, hs @ encoding: [0x5f,0xea,0x3f,0xae]
74 # CHECK-NOMVE: csetm lr, hs @ encoding: [0x5f,0xea,0x3f,0xae]
75 csetm lr, hs
76
77 # CHECK: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]
78 # CHECK-NOMVE: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]
79 csinc lr, r10, r7, le
80
81 # CHECK: csinv lr, r5, zr, hs @ encoding: [0x55,0xea,0x2f,0xae]
82 # CHECK-NOMVE: csinv lr, r5, zr, hs @ encoding: [0x55,0xea,0x2f,0xae]
83 csinv lr, r5, zr, hs
84
85 # CHECK: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
86 # CHECK-NOMVE: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
87 csinv lr, r2, r2, mi
88
89 # CHECK: csneg lr, r1, r11, vc @ encoding: [0x51,0xea,0x7b,0xbe]
90 # CHECK-NOMVE: csneg lr, r1, r11, vc @ encoding: [0x51,0xea,0x7b,0xbe]
91 csneg lr, r1, r11, vc
92
93 # CHECK: lsll lr, r1, #11 @ encoding: [0x5e,0xea,0xcf,0x21]
94 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
95 lsll lr, r1, #11
96
97 # CHECK: lsll lr, r1, r4 @ encoding: [0x5e,0xea,0x0d,0x41]
98 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
99 lsll lr, r1, r4
100
101 # CHECK: lsrl lr, r1, #12 @ encoding: [0x5e,0xea,0x1f,0x31]
102 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
103 lsrl lr, r1, #12
104
105 # CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf]
106 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
107 sqrshr lr, r12
108
109 # CHECK: sqrshr r11, r12 @ encoding: [0x5b,0xea,0x2d,0xcf]
110 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
111 sqrshr r11, r12
112
113 # CHECK: sqrshrl lr, r3, r8 @ encoding: [0x5f,0xea,0x2d,0x83]
114 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
115 sqrshrl lr, r3, r8
116
117 # CHECK: sqshl lr, #17 @ encoding: [0x5e,0xea,0x7f,0x4f]
118 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
119 sqshl lr, #17
120
121 # CHECK: sqshll lr, r11, #28 @ encoding: [0x5f,0xea,0x3f,0x7b]
122 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
123 sqshll lr, r11, #28
124
125 # CHECK: srshr lr, #11 @ encoding: [0x5e,0xea,0xef,0x2f]
126 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
127 srshr lr, #11
128
129 # CHECK: srshrl lr, r11, #23 @ encoding: [0x5f,0xea,0xef,0x5b]
130 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
131 srshrl lr, r11, #23
132
133 # CHECK: uqrshl lr, r1 @ encoding: [0x5e,0xea,0x0d,0x1f]
134 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
135 uqrshl lr, r1
136
137 # CHECK: uqrshll lr, r1, r4 @ encoding: [0x5f,0xea,0x0d,0x41]
138 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
139 uqrshll lr, r1, r4
140
141 # CHECK: uqshl r0, #1 @ encoding: [0x50,0xea,0x4f,0x0f]
142 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
143 uqshl r0, #1
144
145 # CHECK: uqshll lr, r7, #7 @ encoding: [0x5f,0xea,0xcf,0x17]
146 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
147 uqshll lr, r7, #7
148
149 # CHECK: urshr r0, #10 @ encoding: [0x50,0xea,0x9f,0x2f]
150 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
151 urshr r0, #10
152
153 # CHECK: urshrl r0, r9, #29 @ encoding: [0x51,0xea,0x5f,0x79]
154 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
155 urshrl r0, r9, #29
0 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
1 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
2 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
3
4 [0x50 0xea 0xef 0x51]
5 # CHECK: asrl r0, r1, #23 @ encoding: [0x50,0xea,0xef,0x51]
6 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction
7
8 [0x5e 0xea 0xef 0x61]
9 # CHECK: asrl lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
10 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
11
12 [0x50 0xea 0x2d 0x41]
13 # CHECK: asrl r0, r1, r4 @ encoding: [0x50,0xea,0x2d,0x41]
14 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
15
16 [0x5e 0xea 0xcf 0x21]
17 # CHECK: lsll lr, r1, #11 @ encoding: [0x5e,0xea,0xcf,0x21]
18 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
19
20 [0x5e 0xea 0x0d 0x41]
21 # CHECK: lsll lr, r1, r4 @ encoding: [0x5e,0xea,0x0d,0x41]
22 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
23
24 [0x5e 0xea 0x1f 0x31]
25 # CHECK: lsrl lr, r1, #12 @ encoding: [0x5e,0xea,0x1f,0x31]
26 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
27
28 [0x5f 0xea 0x2d 0x83]
29 # CHECK: sqrshrl lr, r3, r8 @ encoding: [0x5f,0xea,0x2d,0x83]
30 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
31
32 [0x5e 0xea 0x7f 0x4f]
33 # CHECK: sqshl lr, #17 @ encoding: [0x5e,0xea,0x7f,0x4f]
34 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
35
36 [0x5f 0xea 0x3f 0x7b]
37 # CHECK: sqshll lr, r11, #28 @ encoding: [0x5f,0xea,0x3f,0x7b]
38 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
39
40 [0x5e 0xea 0xef 0x2f]
41 # CHECK: srshr lr, #11 @ encoding: [0x5e,0xea,0xef,0x2f]
42 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
43
44 [0x5f 0xea 0xef 0x5b]
45 # CHECK: srshrl lr, r11, #23 @ encoding: [0x5f,0xea,0xef,0x5b]
46 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
47
48 [0x5e 0xea 0x2d 0xcf]
49 # CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf]
50 # CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
51
52 [0x5b 0xea 0x2d 0xcf]
53 # CHECK: sqrshr r11, r12 @ encoding: [0x5b,0xea,0x2d,0xcf]
54 # CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
55
56 [0x5e 0xea 0x0d 0xcf]
57 # CHECK: uqrshl lr, r12 @ encoding: [0x5e,0xea,0x0d,0xcf]
58 # CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
59
60 [0x5b 0xea 0x0d 0xcf]
61 # CHECK: uqrshl r11, r12 @ encoding: [0x5b,0xea,0x0d,0xcf]
62 # CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
63
64 [0x5f 0xea 0x0d 0x41]
65 # CHECK: uqrshll lr, r1, r4 @ encoding: [0x5f,0xea,0x0d,0x41]
66 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
67
68 [0x50 0xea 0x4f 0x0f]
69 # CHECK: uqshl r0, #1 @ encoding: [0x50,0xea,0x4f,0x0f]
70 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
71
72 [0x5f 0xea 0xcf 0x17]
73 # CHECK: uqshll lr, r7, #7 @ encoding: [0x5f,0xea,0xcf,0x17]
74 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
75
76 [0x50 0xea 0x9f 0x2f]
77 # CHECK: urshr r0, #10 @ encoding: [0x50,0xea,0x9f,0x2f]
78 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
79
80 [0x51 0xea 0x5f 0x79]
81 # CHECK: urshrl r0, r9, #29 @ encoding: [0x51,0xea,0x5f,0x79]
82 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding