llvm.org GIT mirror llvm / e8a6608
[X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize There are some cases where the mul sequence is smaller, but for the most part, using a div is preferable. This does not apply to vectors, since x86 doesn't have vector idiv, and a vector mul/shifts sequence ought to be smaller than a scalarized division. Differential Revision: http://reviews.llvm.org/D12082 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245431 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Kuperstein 4 years ago
4 changed file(s) with 58 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
2642626426 bool X86TargetLowering::isTargetFTOL() const {
2642726427 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
2642826428 }
26429
26430 bool X86TargetLowering::isIntDivCheap(EVT VT, bool OptSize) const {
26431 // Integer division on x86 is expensive. However, when aggressively optimizing
26432 // for code size, we prefer to use a div instruction, as it is usually smaller
26433 // than the alternative sequence.
26434 // The exception to this is vector division. Since x86 doesn't have vector
26435 // integer division, leaving the division as-is is a loss even in terms of
26436 // size, because it will have to be scalarized, while the alternative code
26437 // sequence can be performed in vector form.
26438 return OptSize && !VT.isVector();
26439 }
901901 /// \brief Customize the preferred legalization strategy for certain types.
902902 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
903903
904 bool isIntDivCheap(EVT VT, bool OptSize) const override;
905
904906 protected:
905907 std::pair
906908 findRepresentativeClass(const TargetRegisterInfo *TRI,
9393 ; CHECK: shrl $11
9494 ; CHECK: ret
9595 }
96
97 define i32 @testsize1(i32 %x) minsize nounwind {
98 entry:
99 %div = sdiv i32 %x, 32
100 ret i32 %div
101 ; CHECK-LABEL: testsize1:
102 ; CHECK: divl
103 }
104
105 define i32 @testsize2(i32 %x) minsize nounwind {
106 entry:
107 %div = sdiv i32 %x, 33
108 ret i32 %div
109 ; CHECK-LABEL: testsize2:
110 ; CHECK: divl
111 }
112
113 define i32 @testsize3(i32 %x) minsize nounwind {
114 entry:
115 %div = udiv i32 %x, 32
116 ret i32 %div
117 ; CHECK-LABEL: testsize3:
118 ; CHECK: shrl
119 }
120
121 define i32 @testsize4(i32 %x) minsize nounwind {
122 entry:
123 %div = udiv i32 %x, 33
124 ret i32 %div
125 ; CHECK-LABEL: testsize4:
126 ; CHECK: divl
127 }
1111 %0 = sdiv <8 x i16> %var,
1212 ret <8 x i16> %0
1313 }
14
15 define <8 x i16> @sdiv_vec8x16_minsize(<8 x i16> %var) minsize {
16 entry:
17 ; CHECK: sdiv_vec8x16_minsize
18 ; CHECK: psraw $15
19 ; CHECK: vpsrlw $11
20 ; CHECK: vpaddw
21 ; CHECK: vpsraw $5
22 ; CHECK: ret
23 %0 = sdiv <8 x i16> %var,
24 ret <8 x i16> %0
25 }
26
1427
1528 define <4 x i32> @sdiv_zero(<4 x i32> %var) {
1629 entry: