llvm.org GIT mirror llvm / e8838d5
Improve sub-register def handling in ProcessImplicitDefs. This boils down to using MachineOperand::readsReg() more. This fixes PR11829 where a use ended up after the first def when lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148996 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
2 changed file(s) with 34 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
4949 SmallSet &ImpDefRegs) {
5050 switch(OpIdx) {
5151 case 1:
52 return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 ||
52 return MI->isCopy() && (!MI->getOperand(0).readsReg() ||
5353 ImpDefRegs.count(MI->getOperand(0).getReg()));
5454 case 2:
55 return MI->isSubregToReg() && (MI->getOperand(0).getSubReg() == 0 ||
55 return MI->isSubregToReg() && (!MI->getOperand(0).readsReg() ||
5656 ImpDefRegs.count(MI->getOperand(0).getReg()));
5757 default: return false;
5858 }
6565 MachineOperand &MO1 = MI->getOperand(1);
6666 if (MO1.getReg() != Reg)
6767 return false;
68 if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg()))
68 if (!MO0.readsReg() || ImpDefRegs.count(MO0.getReg()))
6969 return true;
7070 return false;
7171 }
104104 MachineInstr *MI = &*I;
105105 ++I;
106106 if (MI->isImplicitDef()) {
107 if (MI->getOperand(0).getSubReg())
107 ImpDefMIs.push_back(MI);
108 // Is this a sub-register read-modify-write?
109 if (MI->getOperand(0).readsReg())
108110 continue;
109111 unsigned Reg = MI->getOperand(0).getReg();
110112 ImpDefRegs.insert(Reg);
112114 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
113115 ImpDefRegs.insert(*SS);
114116 }
115 ImpDefMIs.push_back(MI);
116117 continue;
117118 }
118119
119120 // Eliminate %reg1032:sub = COPY undef.
120 if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
121 if (MI->isCopy() && MI->getOperand(0).readsReg()) {
121122 MachineOperand &MO = MI->getOperand(1);
122123 if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) {
123124 if (MO.isKill()) {
139140 bool ChangedToImpDef = false;
140141 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
141142 MachineOperand& MO = MI->getOperand(i);
142 if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef())
143 if (!MO.isReg() || !MO.readsReg())
143144 continue;
144145 unsigned Reg = MO.getReg();
145146 if (!Reg)
171172 continue;
172173 }
173174 if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
174 // Make sure other uses of
175 // Make sure other reads of Reg are also marked .
175176 for (unsigned j = i+1; j != e; ++j) {
176177 MachineOperand &MOJ = MI->getOperand(j);
177 if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg)
178 if (MOJ.isReg() && MOJ.getReg() == Reg && MOJ.readsReg())
178179 MOJ.setIsUndef();
179180 }
180181 ImpDefRegs.erase(Reg);
0 ; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs -verify-coalescing
11 ; PR11841
2 ; PR11829
23 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
34 target triple = "armv7-none-linux-eabi"
45
3637 ret void
3738 }
3839
40 define arm_aapcs_vfpcc void @foo2() nounwind uwtable {
41 entry:
42 br i1 undef, label %for.end, label %cond.end295
43
44 cond.end295: ; preds = %entry
45 %shuffle.i39.i.i1035 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
46 %shuffle.i38.i.i1036 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> zeroinitializer
47 %shuffle.i37.i.i1037 = shufflevector <1 x i64> %shuffle.i39.i.i1035, <1 x i64> %shuffle.i38.i.i1036, <2 x i32>
48 %0 = bitcast <2 x i64> %shuffle.i37.i.i1037 to <4 x float>
49 %1 = bitcast <4 x float> undef to <2 x i64>
50 %shuffle.i36.i.i = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer
51 %shuffle.i35.i.i = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
52 %shuffle.i34.i.i = shufflevector <1 x i64> %shuffle.i36.i.i, <1 x i64> %shuffle.i35.i.i, <2 x i32>
53 %2 = bitcast <2 x i64> %shuffle.i34.i.i to <4 x float>
54 tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind
55 tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind
56 unreachable
57
58 for.end: ; preds = %entry
59 ret void
60 }
61
3962 declare arm_aapcs_vfpcc void @bar(i8*, float, float, float)
63 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
4064
4165 !0 = metadata !{metadata !"omnipotent char", metadata !1}
4266 !1 = metadata !{metadata !"Simple C/C++ TBAA", null}