llvm.org GIT mirror llvm / e8548c2
[X86] Move InstPrinter files to MCTargetDesc. NFC For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360484 91177308-0d34-0410-b5e6-96231b3b80d8 Richard Trieu 1 year, 4 months ago
30 changed file(s) with 2930 addition(s) and 2955 deletion(s). Raw diff Collapse all Expand all
1717 type = Library
1818 name = X86AsmParser
1919 parent = X86
20 required_libraries = MC MCParser Support X86Desc X86Info X86AsmPrinter
20 required_libraries = MC MCParser Support X86Desc X86Info
2121 add_to_library_groups = X86
55 //
66 //===----------------------------------------------------------------------===//
77
8 #include "InstPrinter/X86IntelInstPrinter.h"
98 #include "MCTargetDesc/X86BaseInfo.h"
9 #include "MCTargetDesc/X86IntelInstPrinter.h"
1010 #include "MCTargetDesc/X86MCExpr.h"
1111 #include "MCTargetDesc/X86TargetStreamer.h"
1212 #include "X86AsmParserCommon.h"
88 #ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
99 #define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
1010
11 #include "InstPrinter/X86IntelInstPrinter.h"
11 #include "MCTargetDesc/X86IntelInstPrinter.h"
1212 #include "MCTargetDesc/X86MCTargetDesc.h"
1313 #include "X86AsmParserCommon.h"
1414 #include "llvm/ADT/STLExtras.h"
7373
7474 add_subdirectory(AsmParser)
7575 add_subdirectory(Disassembler)
76 add_subdirectory(InstPrinter)
7776 add_subdirectory(MCTargetDesc)
7877 add_subdirectory(TargetInfo)
7978 add_subdirectory(Utils)
+0
-6
lib/Target/X86/InstPrinter/CMakeLists.txt less more
None add_llvm_library(LLVMX86AsmPrinter
1 X86ATTInstPrinter.cpp
2 X86IntelInstPrinter.cpp
3 X86InstComments.cpp
4 X86InstPrinterCommon.cpp
5 )
+0
-22
lib/Target/X86/InstPrinter/LLVMBuild.txt less more
None ;===- ./lib/Target/X86/InstPrinter/LLVMBuild.txt ---------------*- Conf -*--===;
1 ;
2 ; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 ; See https://llvm.org/LICENSE.txt for license information.
4 ; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 ;
6 ;===------------------------------------------------------------------------===;
7 ;
8 ; This is an LLVMBuild description file for the components in this subdirectory.
9 ;
10 ; For more information on the LLVMBuild system, please see:
11 ;
12 ; http://llvm.org/docs/LLVMBuild.html
13 ;
14 ;===------------------------------------------------------------------------===;
15
16 [component_0]
17 type = Library
18 name = X86AsmPrinter
19 parent = X86
20 required_libraries = MC Support X86Utils
21 add_to_library_groups = X86
+0
-487
lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp less more
None //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This file includes code for rendering MCInst instances as AT&T-style
9 // assembly.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86ATTInstPrinter.h"
14 #include "MCTargetDesc/X86BaseInfo.h"
15 #include "X86InstComments.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Casting.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/Format.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include
25 #include
26 #include
27
28 using namespace llvm;
29
30 #define DEBUG_TYPE "asm-printer"
31
32 // Include the auto-generated portion of the assembly writer.
33 #define PRINT_ALIAS_INSTR
34 #include "X86GenAsmWriter.inc"
35
36 void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
37 OS << markup("");
38 }
39
40 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
41 StringRef Annot, const MCSubtargetInfo &STI) {
42 // If verbose assembly is enabled, we can print some informative comments.
43 if (CommentStream)
44 HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII);
45
46 printInstFlags(MI, OS);
47
48 // Output CALLpcrel32 as "callq" in 64-bit mode.
49 // In Intel annotation it's always emitted as "call".
50 //
51 // TODO: Probably this hack should be redesigned via InstAlias in
52 // InstrInfo.td as soon as Requires clause is supported properly
53 // for InstAlias.
54 if (MI->getOpcode() == X86::CALLpcrel32 &&
55 (STI.getFeatureBits()[X86::Mode64Bit])) {
56 OS << "\tcallq\t";
57 printPCRelImm(MI, 0, OS);
58 }
59 // data16 and data32 both have the same encoding of 0x66. While data32 is
60 // valid only in 16 bit systems, data16 is valid in the rest.
61 // There seems to be some lack of support of the Requires clause that causes
62 // 0x66 to be interpreted as "data16" by the asm printer.
63 // Thus we add an adjustment here in order to print the "right" instruction.
64 else if (MI->getOpcode() == X86::DATA16_PREFIX &&
65 STI.getFeatureBits()[X86::Mode16Bit]) {
66 OS << "\tdata32";
67 }
68 // Try to print any aliases first.
69 else if (!printAliasInstr(MI, OS) &&
70 !printVecCompareInstr(MI, OS))
71 printInstruction(MI, OS);
72
73 // Next always print the annotation.
74 printAnnotation(OS, Annot);
75 }
76
77 bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
78 raw_ostream &OS) {
79 if (MI->getNumOperands() == 0 ||
80 !MI->getOperand(MI->getNumOperands() - 1).isImm())
81 return false;
82
83 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
84
85 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
86
87 // Custom print the vector compare instructions to get the immediate
88 // translated into the mnemonic.
89 switch (MI->getOpcode()) {
90 case X86::CMPPDrmi: case X86::CMPPDrri:
91 case X86::CMPPSrmi: case X86::CMPPSrri:
92 case X86::CMPSDrm: case X86::CMPSDrr:
93 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int:
94 case X86::CMPSSrm: case X86::CMPSSrr:
95 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int:
96 if (Imm >= 0 && Imm <= 7) {
97 OS << '\t';
98 printCMPMnemonic(MI, /*IsVCMP*/false, OS);
99
100 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
101 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
102 printdwordmem(MI, 2, OS);
103 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
104 printqwordmem(MI, 2, OS);
105 else
106 printxmmwordmem(MI, 2, OS);
107 } else
108 printOperand(MI, 2, OS);
109
110 // Skip operand 1 as its tied to the dest.
111
112 OS << ", ";
113 printOperand(MI, 0, OS);
114 return true;
115 }
116 break;
117
118 case X86::VCMPPDrmi: case X86::VCMPPDrri:
119 case X86::VCMPPDYrmi: case X86::VCMPPDYrri:
120 case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri:
121 case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri:
122 case X86::VCMPPDZrmi: case X86::VCMPPDZrri:
123 case X86::VCMPPSrmi: case X86::VCMPPSrri:
124 case X86::VCMPPSYrmi: case X86::VCMPPSYrri:
125 case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri:
126 case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri:
127 case X86::VCMPPSZrmi: case X86::VCMPPSZrri:
128 case X86::VCMPSDrm: case X86::VCMPSDrr:
129 case X86::VCMPSDZrm: case X86::VCMPSDZrr:
130 case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int:
131 case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int:
132 case X86::VCMPSSrm: case X86::VCMPSSrr:
133 case X86::VCMPSSZrm: case X86::VCMPSSZrr:
134 case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int:
135 case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int:
136 case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
137 case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
138 case X86::VCMPPDZrmik: case X86::VCMPPDZrrik:
139 case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
140 case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
141 case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
142 case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk:
143 case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk:
144 case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
145 case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
146 case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
147 case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
148 case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
149 case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
150 case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
151 case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
152 case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk:
153 case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk:
154 if (Imm >= 0 && Imm <= 31) {
155 OS << '\t';
156 printCMPMnemonic(MI, /*IsVCMP*/true, OS);
157
158 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2;
159
160 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
161 if (Desc.TSFlags & X86II::EVEX_B) {
162 // Broadcast form.
163 // Load size is based on W-bit.
164 if (Desc.TSFlags & X86II::VEX_W)
165 printqwordmem(MI, CurOp--, OS);
166 else
167 printdwordmem(MI, CurOp--, OS);
168
169 // Print the number of elements broadcasted.
170 unsigned NumElts;
171 if (Desc.TSFlags & X86II::EVEX_L2)
172 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
173 else if (Desc.TSFlags & X86II::VEX_L)
174 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
175 else
176 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
177 OS << "{1to" << NumElts << "}";
178 } else {
179 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
180 printdwordmem(MI, CurOp--, OS);
181 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
182 printqwordmem(MI, CurOp--, OS);
183 else if (Desc.TSFlags & X86II::EVEX_L2)
184 printzmmwordmem(MI, CurOp--, OS);
185 else if (Desc.TSFlags & X86II::VEX_L)
186 printymmwordmem(MI, CurOp--, OS);
187 else
188 printxmmwordmem(MI, CurOp--, OS);
189 }
190 } else {
191 if (Desc.TSFlags & X86II::EVEX_B)
192 OS << "{sae}, ";
193 printOperand(MI, CurOp--, OS);
194 }
195
196 OS << ", ";
197 printOperand(MI, CurOp--, OS);
198 OS << ", ";
199 printOperand(MI, 0, OS);
200 if (CurOp > 0) {
201 // Print mask operand.
202 OS << " {";
203 printOperand(MI, CurOp--, OS);
204 OS << "}";
205 }
206
207 return true;
208 }
209 break;
210
211 case X86::VPCOMBmi: case X86::VPCOMBri:
212 case X86::VPCOMDmi: case X86::VPCOMDri:
213 case X86::VPCOMQmi: case X86::VPCOMQri:
214 case X86::VPCOMUBmi: case X86::VPCOMUBri:
215 case X86::VPCOMUDmi: case X86::VPCOMUDri:
216 case X86::VPCOMUQmi: case X86::VPCOMUQri:
217 case X86::VPCOMUWmi: case X86::VPCOMUWri:
218 case X86::VPCOMWmi: case X86::VPCOMWri:
219 if (Imm >= 0 && Imm <= 7) {
220 OS << '\t';
221 printVPCOMMnemonic(MI, OS);
222
223 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem)
224 printxmmwordmem(MI, 2, OS);
225 else
226 printOperand(MI, 2, OS);
227
228 OS << ", ";
229 printOperand(MI, 1, OS);
230 OS << ", ";
231 printOperand(MI, 0, OS);
232 return true;
233 }
234 break;
235
236 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri:
237 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri:
238 case X86::VPCMPBZrmi: case X86::VPCMPBZrri:
239 case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri:
240 case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri:
241 case X86::VPCMPDZrmi: case X86::VPCMPDZrri:
242 case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri:
243 case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri:
244 case X86::VPCMPQZrmi: case X86::VPCMPQZrri:
245 case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri:
246 case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri:
247 case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri:
248 case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri:
249 case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri:
250 case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri:
251 case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri:
252 case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri:
253 case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri:
254 case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri:
255 case X86::VPCMPUWZ256rmi: case X86::VPCMPUWZ256rri:
256 case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri:
257 case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri:
258 case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri:
259 case X86::VPCMPWZrmi: case X86::VPCMPWZrri:
260 case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik:
261 case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik:
262 case X86::VPCMPBZrmik: case X86::VPCMPBZrrik:
263 case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik:
264 case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik:
265 case X86::VPCMPDZrmik: case X86::VPCMPDZrrik:
266 case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik:
267 case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik:
268 case X86::VPCMPQZrmik: case X86::VPCMPQZrrik:
269 case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
270 case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
271 case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik:
272 case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
273 case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
274 case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik:
275 case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
276 case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
277 case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik:
278 case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
279 case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik:
280 case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik:
281 case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik:
282 case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik:
283 case X86::VPCMPWZrmik: case X86::VPCMPWZrrik:
284 case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk:
285 case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk:
286 case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk:
287 case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk:
288 case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk:
289 case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk:
290 case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk:
291 case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk:
292 case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk:
293 case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk:
294 case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk:
295 case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk:
296 if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) {
297 OS << '\t';
298 printVPCMPMnemonic(MI, OS);
299
300 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2;
301
302 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
303 if (Desc.TSFlags & X86II::EVEX_B) {
304 // Broadcast form.
305 // Load size is based on W-bit as only D and Q are supported.
306 if (Desc.TSFlags & X86II::VEX_W)
307 printqwordmem(MI, CurOp--, OS);
308 else
309 printdwordmem(MI, CurOp--, OS);
310
311 // Print the number of elements broadcasted.
312 unsigned NumElts;
313 if (Desc.TSFlags & X86II::EVEX_L2)
314 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
315 else if (Desc.TSFlags & X86II::VEX_L)
316 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
317 else
318 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
319 OS << "{1to" << NumElts << "}";
320 } else {
321 if (Desc.TSFlags & X86II::EVEX_L2)
322 printzmmwordmem(MI, CurOp--, OS);
323 else if (Desc.TSFlags & X86II::VEX_L)
324 printymmwordmem(MI, CurOp--, OS);
325 else
326 printxmmwordmem(MI, CurOp--, OS);
327 }
328 } else {
329 printOperand(MI, CurOp--, OS);
330 }
331
332 OS << ", ";
333 printOperand(MI, CurOp--, OS);
334 OS << ", ";
335 printOperand(MI, 0, OS);
336 if (CurOp > 0) {
337 // Print mask operand.
338 OS << " {";
339 printOperand(MI, CurOp--, OS);
340 OS << "}";
341 }
342
343 return true;
344 }
345 break;
346 }
347
348 return false;
349 }
350
351 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
352 raw_ostream &O) {
353 const MCOperand &Op = MI->getOperand(OpNo);
354 if (Op.isReg()) {
355 printRegName(O, Op.getReg());
356 } else if (Op.isImm()) {
357 // Print immediates as signed values.
358 int64_t Imm = Op.getImm();
359 O << markup("");
360
361 // TODO: This should be in a helper function in the base class, so it can
362 // be used by other printers.
363
364 // If there are no instruction-specific comments, add a comment clarifying
365 // the hex value of the immediate operand when it isn't in the range
366 // [-256,255].
367 if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) {
368 // Don't print unnecessary hex sign bits.
369 if (Imm == (int16_t)(Imm))
370 *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm);
371 else if (Imm == (int32_t)(Imm))
372 *CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm);
373 else
374 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm);
375 }
376 } else {
377 assert(Op.isExpr() && "unknown operand kind in printOperand");
378 O << markup("
379 Op.getExpr()->print(O, &MAI);
380 O << markup(">");
381 }
382 }
383
384 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
385 raw_ostream &O) {
386 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
387 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
388 const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
389
390 O << markup("
391
392 // If this has a segment register, print it.
393 printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
394
395 if (DispSpec.isImm()) {
396 int64_t DispVal = DispSpec.getImm();
397 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
398 O << formatImm(DispVal);
399 } else {
400 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
401 DispSpec.getExpr()->print(O, &MAI);
402 }
403
404 if (IndexReg.getReg() || BaseReg.getReg()) {
405 O << '(';
406 if (BaseReg.getReg())
407 printOperand(MI, Op + X86::AddrBaseReg, O);
408
409 if (IndexReg.getReg()) {
410 O << ',';
411 printOperand(MI, Op + X86::AddrIndexReg, O);
412 unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
413 if (ScaleVal != 1) {
414 O << ',' << markup("
415 << markup(">");
416 }
417 }
418 O << ')';
419 }
420
421 O << markup(">");
422 }
423
424 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
425 raw_ostream &O) {
426 O << markup("
427
428 // If this has a segment register, print it.
429 printOptionalSegReg(MI, Op + 1, O);
430
431 O << "(";
432 printOperand(MI, Op, O);
433 O << ")";
434
435 O << markup(">");
436 }
437
438 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
439 raw_ostream &O) {
440 O << markup("
441
442 O << "%es:(";
443 printOperand(MI, Op, O);
444 O << ")";
445
446 O << markup(">");
447 }
448
449 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
450 raw_ostream &O) {
451 const MCOperand &DispSpec = MI->getOperand(Op);
452
453 O << markup("
454
455 // If this has a segment register, print it.
456 printOptionalSegReg(MI, Op + 1, O);
457
458 if (DispSpec.isImm()) {
459 O << formatImm(DispSpec.getImm());
460 } else {
461 assert(DispSpec.isExpr() && "non-immediate displacement?");
462 DispSpec.getExpr()->print(O, &MAI);
463 }
464
465 O << markup(">");
466 }
467
468 void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
469 raw_ostream &O) {
470 if (MI->getOperand(Op).isExpr())
471 return printOperand(MI, Op, O);
472
473 O << markup("getOperand(Op).getImm() & 0xff)
474 << markup(">");
475 }
476
477 void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
478 raw_ostream &OS) {
479 const MCOperand &Op = MI->getOperand(OpNo);
480 unsigned Reg = Op.getReg();
481 // Override the default printing to print st(0) instead st.
482 if (Reg == X86::ST0)
483 OS << markup("");
484 else
485 printRegName(OS, Reg);
486 }
+0
-124
lib/Target/X86/InstPrinter/X86ATTInstPrinter.h less more
None //=- X86ATTInstPrinter.h - Convert X86 MCInst to assembly syntax --*- C++ -*-=//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This class prints an X86 MCInst to AT&T style .s file syntax.
9 //
10 //===----------------------------------------------------------------------===//
11
12 #ifndef LLVM_LIB_TARGET_X86_INSTPRINTER_X86ATTINSTPRINTER_H
13 #define LLVM_LIB_TARGET_X86_INSTPRINTER_X86ATTINSTPRINTER_H
14
15 #include "X86InstPrinterCommon.h"
16
17 namespace llvm {
18
19 class X86ATTInstPrinter final : public X86InstPrinterCommon {
20 public:
21 X86ATTInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
22 const MCRegisterInfo &MRI)
23 : X86InstPrinterCommon(MAI, MII, MRI), HasCustomInstComment(false) {}
24
25 void printRegName(raw_ostream &OS, unsigned RegNo) const override;
26 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
27 const MCSubtargetInfo &STI) override;
28 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
29
30 // Autogenerated by tblgen, returns true if we successfully printed an
31 // alias.
32 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
33 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
34 unsigned PrintMethodIdx, raw_ostream &O);
35
36 // Autogenerated by tblgen.
37 void printInstruction(const MCInst *MI, raw_ostream &OS);
38 static const char *getRegisterName(unsigned RegNo);
39
40 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
41 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
42 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
43 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
44 void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
45 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS);
46 void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
47
48 void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
49 printMemReference(MI, OpNo, O);
50 }
51 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
52 printMemReference(MI, OpNo, O);
53 }
54
55 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
56 printMemReference(MI, OpNo, O);
57 }
58 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
59 printMemReference(MI, OpNo, O);
60 }
61 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
62 printMemReference(MI, OpNo, O);
63 }
64 void printqwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
65 printMemReference(MI, OpNo, O);
66 }
67 void printxmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
68 printMemReference(MI, OpNo, O);
69 }
70 void printymmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
71 printMemReference(MI, OpNo, O);
72 }
73 void printzmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
74 printMemReference(MI, OpNo, O);
75 }
76 void printtbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
77 printMemReference(MI, OpNo, O);
78 }
79
80 void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
81 printSrcIdx(MI, OpNo, O);
82 }
83 void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
84 printSrcIdx(MI, OpNo, O);
85 }
86 void printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
87 printSrcIdx(MI, OpNo, O);
88 }
89 void printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
90 printSrcIdx(MI, OpNo, O);
91 }
92 void printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
93 printDstIdx(MI, OpNo, O);
94 }
95 void printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
96 printDstIdx(MI, OpNo, O);
97 }
98 void printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
99 printDstIdx(MI, OpNo, O);
100 }
101 void printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
102 printDstIdx(MI, OpNo, O);
103 }
104 void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
105 printMemOffset(MI, OpNo, O);
106 }
107 void printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
108 printMemOffset(MI, OpNo, O);
109 }
110 void printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
111 printMemOffset(MI, OpNo, O);
112 }
113 void printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
114 printMemOffset(MI, OpNo, O);
115 }
116
117 private:
118 bool HasCustomInstComment;
119 };
120
121 } // end namespace llvm
122
123 #endif // LLVM_LIB_TARGET_X86_INSTPRINTER_X86ATTINSTPRINTER_H
+0
-1310
lib/Target/X86/InstPrinter/X86InstComments.cpp less more
None //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This defines functionality used to emit comments about X86 instructions to
9 // an output stream for -fverbose-asm.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86InstComments.h"
14 #include "X86ATTInstPrinter.h"
15 #include "MCTargetDesc/X86BaseInfo.h"
16 #include "MCTargetDesc/X86MCTargetDesc.h"
17 #include "Utils/X86ShuffleDecode.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/Support/raw_ostream.h"
21
22 using namespace llvm;
23
24 #define CASE_SSE_INS_COMMON(Inst, src) \
25 case X86::Inst##src:
26
27 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
28 case X86::V##Inst##Suffix##src:
29
30 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
31 case X86::V##Inst##Suffix##src##k:
32
33 #define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \
34 case X86::V##Inst##Suffix##src##kz:
35
36 #define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
37 CASE_AVX_INS_COMMON(Inst, Suffix, src) \
38 CASE_MASK_INS_COMMON(Inst, Suffix, src) \
39 CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
40
41 #define CASE_MOVDUP(Inst, src) \
42 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
43 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
44 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
45 CASE_AVX_INS_COMMON(Inst, , r##src) \
46 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
47 CASE_SSE_INS_COMMON(Inst, r##src)
48
49 #define CASE_MASK_MOVDUP(Inst, src) \
50 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
51 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
52 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
53
54 #define CASE_MASKZ_MOVDUP(Inst, src) \
55 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
56 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
57 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
58
59 #define CASE_PMOVZX(Inst, src) \
60 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
61 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
62 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
63 CASE_AVX_INS_COMMON(Inst, , r##src) \
64 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
65 CASE_SSE_INS_COMMON(Inst, r##src)
66
67 #define CASE_MASK_PMOVZX(Inst, src) \
68 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
69 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
70 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
71
72 #define CASE_MASKZ_PMOVZX(Inst, src) \
73 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
74 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
75 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
76
77 #define CASE_UNPCK(Inst, src) \
78 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
79 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
80 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
81 CASE_AVX_INS_COMMON(Inst, , r##src) \
82 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
83 CASE_SSE_INS_COMMON(Inst, r##src)
84
85 #define CASE_MASK_UNPCK(Inst, src) \
86 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
87 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
88 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
89
90 #define CASE_MASKZ_UNPCK(Inst, src) \
91 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
92 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
93 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
94
95 #define CASE_SHUF(Inst, suf) \
96 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
97 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
98 CASE_AVX512_INS_COMMON(Inst, Z128, suf) \
99 CASE_AVX_INS_COMMON(Inst, , suf) \
100 CASE_AVX_INS_COMMON(Inst, Y, suf) \
101 CASE_SSE_INS_COMMON(Inst, suf)
102
103 #define CASE_MASK_SHUF(Inst, src) \
104 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
105 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
106 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
107
108 #define CASE_MASKZ_SHUF(Inst, src) \
109 CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \
110 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \
111 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
112
113 #define CASE_VPERMILPI(Inst, src) \
114 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
115 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
116 CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \
117 CASE_AVX_INS_COMMON(Inst, , src##i) \
118 CASE_AVX_INS_COMMON(Inst, Y, src##i)
119
120 #define CASE_MASK_VPERMILPI(Inst, src) \
121 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
122 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
123 CASE_MASK_INS_COMMON(Inst, Z128, src##i)
124
125 #define CASE_MASKZ_VPERMILPI(Inst, src) \
126 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
127 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \
128 CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
129
130 #define CASE_VPERM(Inst, src) \
131 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
132 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
133 CASE_AVX_INS_COMMON(Inst, Y, src##i)
134
135 #define CASE_MASK_VPERM(Inst, src) \
136 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
137 CASE_MASK_INS_COMMON(Inst, Z256, src##i)
138
139 #define CASE_MASKZ_VPERM(Inst, src) \
140 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
141 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
142
143 #define CASE_VSHUF(Inst, src) \
144 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
145 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
146 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
147 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
148
149 #define CASE_MASK_VSHUF(Inst, src) \
150 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
151 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
152 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
153 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
154
155 #define CASE_MASKZ_VSHUF(Inst, src) \
156 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
157 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
158 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
159 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
160
161 #define CASE_AVX512_FMA(Inst, suf) \
162 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
163 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
164 CASE_AVX512_INS_COMMON(Inst, Z128, suf)
165
166 #define CASE_FMA(Inst, suf) \
167 CASE_AVX512_FMA(Inst, suf) \
168 CASE_AVX_INS_COMMON(Inst, , suf) \
169 CASE_AVX_INS_COMMON(Inst, Y, suf)
170
171 #define CASE_FMA_PACKED_REG(Inst) \
172 CASE_FMA(Inst##PD, r) \
173 CASE_FMA(Inst##PS, r)
174
175 #define CASE_FMA_PACKED_MEM(Inst) \
176 CASE_FMA(Inst##PD, m) \
177 CASE_FMA(Inst##PS, m) \
178 CASE_AVX512_FMA(Inst##PD, mb) \
179 CASE_AVX512_FMA(Inst##PS, mb)
180
181 #define CASE_FMA_SCALAR_REG(Inst) \
182 CASE_AVX_INS_COMMON(Inst##SD, , r) \
183 CASE_AVX_INS_COMMON(Inst##SS, , r) \
184 CASE_AVX_INS_COMMON(Inst##SD, , r_Int) \
185 CASE_AVX_INS_COMMON(Inst##SS, , r_Int) \
186 CASE_AVX_INS_COMMON(Inst##SD, Z, r) \
187 CASE_AVX_INS_COMMON(Inst##SS, Z, r) \
188 CASE_AVX512_INS_COMMON(Inst##SD, Z, r_Int) \
189 CASE_AVX512_INS_COMMON(Inst##SS, Z, r_Int)
190
191 #define CASE_FMA_SCALAR_MEM(Inst) \
192 CASE_AVX_INS_COMMON(Inst##SD, , m) \
193 CASE_AVX_INS_COMMON(Inst##SS, , m) \
194 CASE_AVX_INS_COMMON(Inst##SD, , m_Int) \
195 CASE_AVX_INS_COMMON(Inst##SS, , m_Int) \
196 CASE_AVX_INS_COMMON(Inst##SD, Z, m) \
197 CASE_AVX_INS_COMMON(Inst##SS, Z, m) \
198 CASE_AVX512_INS_COMMON(Inst##SD, Z, m_Int) \
199 CASE_AVX512_INS_COMMON(Inst##SS, Z, m_Int)
200
201 static unsigned getVectorRegSize(unsigned RegNo) {
202 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
203 return 512;
204 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
205 return 256;
206 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
207 return 128;
208 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
209 return 64;
210
211 llvm_unreachable("Unknown vector reg!");
212 }
213
214 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize,
215 unsigned OperandIndex) {
216 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
217 return getVectorRegSize(OpReg) / ScalarSize;
218 }
219
220 static const char *getRegName(unsigned Reg) {
221 return X86ATTInstPrinter::getRegisterName(Reg);
222 }
223
224 /// Wraps the destination register name with AVX512 mask/maskz filtering.
225 static void printMasking(raw_ostream &OS, const MCInst *MI,
226 const MCInstrInfo &MCII) {
227 const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
228 uint64_t TSFlags = Desc.TSFlags;
229
230 if (!(TSFlags & X86II::EVEX_K))
231 return;
232
233 bool MaskWithZero = (TSFlags & X86II::EVEX_Z);
234 unsigned MaskOp = Desc.getNumDefs();
235
236 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1)
237 ++MaskOp;
238
239 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg());
240
241 // MASK: zmmX {%kY}
242 OS << " {%" << MaskRegName << "}";
243
244 // MASKZ: zmmX {%kY} {z}
245 if (MaskWithZero)
246 OS << " {z}";
247 }
248
249 static bool printFMA3Comments(const MCInst *MI, raw_ostream &OS) {
250 const char *Mul1Name = nullptr, *Mul2Name = nullptr, *AccName = nullptr;
251 unsigned NumOperands = MI->getNumOperands();
252 bool RegForm = false;
253 bool Negate = false;
254 StringRef AccStr = "+";
255
256 // The operands for FMA instructions without rounding fall into two forms.
257 // dest, src1, src2, src3
258 // dest, src1, mask, src2, src3
259 // Where src3 is either a register or 5 memory address operands. So to find
260 // dest and src1 we can index from the front. To find src2 and src3 we can
261 // index from the end by taking into account memory vs register form when
262 // finding src2.
263
264 switch (MI->getOpcode()) {
265 default:
266 return false;
267 CASE_FMA_PACKED_REG(FMADD132)
268 CASE_FMA_SCALAR_REG(FMADD132)
269 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
270 RegForm = true;
271 LLVM_FALLTHROUGH;
272 CASE_FMA_PACKED_MEM(FMADD132)
273 CASE_FMA_SCALAR_MEM(FMADD132)
274 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
275 Mul1Name = getRegName(MI->getOperand(1).getReg());
276 break;
277
278 CASE_FMA_PACKED_REG(FMADD213)
279 CASE_FMA_SCALAR_REG(FMADD213)
280 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
281 RegForm = true;
282 LLVM_FALLTHROUGH;
283 CASE_FMA_PACKED_MEM(FMADD213)
284 CASE_FMA_SCALAR_MEM(FMADD213)
285 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
286 Mul2Name = getRegName(MI->getOperand(1).getReg());
287 break;
288
289 CASE_FMA_PACKED_REG(FMADD231)
290 CASE_FMA_SCALAR_REG(FMADD231)
291 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
292 RegForm = true;
293 LLVM_FALLTHROUGH;
294 CASE_FMA_PACKED_MEM(FMADD231)
295 CASE_FMA_SCALAR_MEM(FMADD231)
296 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
297 AccName = getRegName(MI->getOperand(1).getReg());
298 break;
299
300 CASE_FMA_PACKED_REG(FMSUB132)
301 CASE_FMA_SCALAR_REG(FMSUB132)
302 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
303 RegForm = true;
304 LLVM_FALLTHROUGH;
305 CASE_FMA_PACKED_MEM(FMSUB132)
306 CASE_FMA_SCALAR_MEM(FMSUB132)
307 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
308 Mul1Name = getRegName(MI->getOperand(1).getReg());
309 AccStr = "-";
310 break;
311
312 CASE_FMA_PACKED_REG(FMSUB213)
313 CASE_FMA_SCALAR_REG(FMSUB213)
314 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
315 RegForm = true;
316 LLVM_FALLTHROUGH;
317 CASE_FMA_PACKED_MEM(FMSUB213)
318 CASE_FMA_SCALAR_MEM(FMSUB213)
319 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
320 Mul2Name = getRegName(MI->getOperand(1).getReg());
321 AccStr = "-";
322 break;
323
324 CASE_FMA_PACKED_REG(FMSUB231)
325 CASE_FMA_SCALAR_REG(FMSUB231)
326 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
327 RegForm = true;
328 LLVM_FALLTHROUGH;
329 CASE_FMA_PACKED_MEM(FMSUB231)
330 CASE_FMA_SCALAR_MEM(FMSUB231)
331 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
332 AccName = getRegName(MI->getOperand(1).getReg());
333 AccStr = "-";
334 break;
335
336 CASE_FMA_PACKED_REG(FNMADD132)
337 CASE_FMA_SCALAR_REG(FNMADD132)
338 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
339 RegForm = true;
340 LLVM_FALLTHROUGH;
341 CASE_FMA_PACKED_MEM(FNMADD132)
342 CASE_FMA_SCALAR_MEM(FNMADD132)
343 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
344 Mul1Name = getRegName(MI->getOperand(1).getReg());
345 Negate = true;
346 break;
347
348 CASE_FMA_PACKED_REG(FNMADD213)
349 CASE_FMA_SCALAR_REG(FNMADD213)
350 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
351 RegForm = true;
352 LLVM_FALLTHROUGH;
353 CASE_FMA_PACKED_MEM(FNMADD213)
354 CASE_FMA_SCALAR_MEM(FNMADD213)
355 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
356 Mul2Name = getRegName(MI->getOperand(1).getReg());
357 Negate = true;
358 break;
359
360 CASE_FMA_PACKED_REG(FNMADD231)
361 CASE_FMA_SCALAR_REG(FNMADD231)
362 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
363 RegForm = true;
364 LLVM_FALLTHROUGH;
365 CASE_FMA_PACKED_MEM(FNMADD231)
366 CASE_FMA_SCALAR_MEM(FNMADD231)
367 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
368 AccName = getRegName(MI->getOperand(1).getReg());
369 Negate = true;
370 break;
371
372 CASE_FMA_PACKED_REG(FNMSUB132)
373 CASE_FMA_SCALAR_REG(FNMSUB132)
374 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
375 RegForm = true;
376 LLVM_FALLTHROUGH;
377 CASE_FMA_PACKED_MEM(FNMSUB132)
378 CASE_FMA_SCALAR_MEM(FNMSUB132)
379 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
380 Mul1Name = getRegName(MI->getOperand(1).getReg());
381 AccStr = "-";
382 Negate = true;
383 break;
384
385 CASE_FMA_PACKED_REG(FNMSUB213)
386 CASE_FMA_SCALAR_REG(FNMSUB213)
387 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
388 RegForm = true;
389 LLVM_FALLTHROUGH;
390 CASE_FMA_PACKED_MEM(FNMSUB213)
391 CASE_FMA_SCALAR_MEM(FNMSUB213)
392 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
393 Mul2Name = getRegName(MI->getOperand(1).getReg());
394 AccStr = "-";
395 Negate = true;
396 break;
397
398 CASE_FMA_PACKED_REG(FNMSUB231)
399 CASE_FMA_SCALAR_REG(FNMSUB231)
400 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
401 RegForm = true;
402 LLVM_FALLTHROUGH;
403 CASE_FMA_PACKED_MEM(FNMSUB231)
404 CASE_FMA_SCALAR_MEM(FNMSUB231)
405 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
406 AccName = getRegName(MI->getOperand(1).getReg());
407 AccStr = "-";
408 Negate = true;
409 break;
410
411 CASE_FMA_PACKED_REG(FMADDSUB132)
412 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
413 RegForm = true;
414 LLVM_FALLTHROUGH;
415 CASE_FMA_PACKED_MEM(FMADDSUB132)
416 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
417 Mul1Name = getRegName(MI->getOperand(1).getReg());
418 AccStr = "+/-";
419 break;
420
421 CASE_FMA_PACKED_REG(FMADDSUB213)
422 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
423 RegForm = true;
424 LLVM_FALLTHROUGH;
425 CASE_FMA_PACKED_MEM(FMADDSUB213)
426 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
427 Mul2Name = getRegName(MI->getOperand(1).getReg());
428 AccStr = "+/-";
429 break;
430
431 CASE_FMA_PACKED_REG(FMADDSUB231)
432 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
433 RegForm = true;
434 LLVM_FALLTHROUGH;
435 CASE_FMA_PACKED_MEM(FMADDSUB231)
436 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
437 AccName = getRegName(MI->getOperand(1).getReg());
438 AccStr = "+/-";
439 break;
440
441 CASE_FMA_PACKED_REG(FMSUBADD132)
442 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
443 RegForm = true;
444 LLVM_FALLTHROUGH;
445 CASE_FMA_PACKED_MEM(FMSUBADD132)
446 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
447 Mul1Name = getRegName(MI->getOperand(1).getReg());
448 AccStr = "-/+";
449 break;
450
451 CASE_FMA_PACKED_REG(FMSUBADD213)
452 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
453 RegForm = true;
454 LLVM_FALLTHROUGH;
455 CASE_FMA_PACKED_MEM(FMSUBADD213)
456 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
457 Mul2Name = getRegName(MI->getOperand(1).getReg());
458 AccStr = "-/+";
459 break;
460
461 CASE_FMA_PACKED_REG(FMSUBADD231)
462 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
463 RegForm = true;
464 LLVM_FALLTHROUGH;
465 CASE_FMA_PACKED_MEM(FMSUBADD231)
466 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
467 AccName = getRegName(MI->getOperand(1).getReg());
468 AccStr = "-/+";
469 break;
470 }
471
472 const char *DestName = getRegName(MI->getOperand(0).getReg());
473
474 if (!Mul1Name) Mul1Name = "mem";
475 if (!Mul2Name) Mul2Name = "mem";
476 if (!AccName) AccName = "mem";
477
478 OS << DestName << " = ";
479 // TODO: Print masking information?
480
481 if (Negate)
482 OS << '-';
483
484 OS << '(' << Mul1Name << " * " << Mul2Name << ") " << AccStr << ' '
485 << AccName;
486
487 return true;
488 }
489
490
491 //===----------------------------------------------------------------------===//
492 // Top Level Entrypoint
493 //===----------------------------------------------------------------------===//
494
495 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
496 /// newline terminated strings to the specified string if desired. This
497 /// information is shown in disassembly dumps when verbose assembly is enabled.
498 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
499 const MCInstrInfo &MCII) {
500 // If this is a shuffle operation, the switch should fill in this state.
501 SmallVector ShuffleMask;
502 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
503 unsigned NumOperands = MI->getNumOperands();
504 bool RegForm = false;
505
506 if (printFMA3Comments(MI, OS))
507 return true;
508
509 switch (MI->getOpcode()) {
510 default:
511 // Not an instruction for which we can decode comments.
512 return false;
513
514 case X86::BLENDPDrri:
515 case X86::VBLENDPDrri:
516 case X86::VBLENDPDYrri:
517 Src2Name = getRegName(MI->getOperand(2).getReg());
518 LLVM_FALLTHROUGH;
519 case X86::BLENDPDrmi:
520 case X86::VBLENDPDrmi:
521 case X86::VBLENDPDYrmi:
522 if (MI->getOperand(NumOperands - 1).isImm())
523 DecodeBLENDMask(getRegOperandNumElts(MI, 64, 0),
524 MI->getOperand(NumOperands - 1).getImm(),
525 ShuffleMask);
526 Src1Name = getRegName(MI->getOperand(1).getReg());
527 DestName = getRegName(MI->getOperand(0).getReg());
528 break;
529
530 case X86::BLENDPSrri:
531 case X86::VBLENDPSrri:
532 case X86::VBLENDPSYrri:
533 Src2Name = getRegName(MI->getOperand(2).getReg());
534 LLVM_FALLTHROUGH;
535 case X86::BLENDPSrmi:
536 case X86::VBLENDPSrmi:
537 case X86::VBLENDPSYrmi:
538 if (MI->getOperand(NumOperands - 1).isImm())
539 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
540 MI->getOperand(NumOperands - 1).getImm(),
541 ShuffleMask);
542 Src1Name = getRegName(MI->getOperand(1).getReg());
543 DestName = getRegName(MI->getOperand(0).getReg());
544 break;
545
546 case X86::PBLENDWrri:
547 case X86::VPBLENDWrri:
548 case X86::VPBLENDWYrri:
549 Src2Name = getRegName(MI->getOperand(2).getReg());
550 LLVM_FALLTHROUGH;
551 case X86::PBLENDWrmi:
552 case X86::VPBLENDWrmi:
553 case X86::VPBLENDWYrmi:
554 if (MI->getOperand(NumOperands - 1).isImm())
555 DecodeBLENDMask(getRegOperandNumElts(MI, 16, 0),
556 MI->getOperand(NumOperands - 1).getImm(),
557 ShuffleMask);
558 Src1Name = getRegName(MI->getOperand(1).getReg());
559 DestName = getRegName(MI->getOperand(0).getReg());
560 break;
561
562 case X86::VPBLENDDrri:
563 case X86::VPBLENDDYrri:
564 Src2Name = getRegName(MI->getOperand(2).getReg());
565 LLVM_FALLTHROUGH;
566 case X86::VPBLENDDrmi:
567 case X86::VPBLENDDYrmi:
568 if (MI->getOperand(NumOperands - 1).isImm())
569 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
570 MI->getOperand(NumOperands - 1).getImm(),
571 ShuffleMask);
572 Src1Name = getRegName(MI->getOperand(1).getReg());
573 DestName = getRegName(MI->getOperand(0).getReg());
574 break;
575
576 case X86::INSERTPSrr:
577 case X86::VINSERTPSrr:
578 case X86::VINSERTPSZrr:
579 Src2Name = getRegName(MI->getOperand(2).getReg());
580 LLVM_FALLTHROUGH;
581 case X86::INSERTPSrm:
582 case X86::VINSERTPSrm:
583 case X86::VINSERTPSZrm:
584 DestName = getRegName(MI->getOperand(0).getReg());
585 Src1Name = getRegName(MI->getOperand(1).getReg());
586 if (MI->getOperand(NumOperands - 1).isImm())
587 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(),
588 ShuffleMask);
589 break;
590
591 case X86::MOVLHPSrr:
592 case X86::VMOVLHPSrr:
593 case X86::VMOVLHPSZrr:
594 Src2Name = getRegName(MI->getOperand(2).getReg());
595 Src1Name = getRegName(MI->getOperand(1).getReg());
596 DestName = getRegName(MI->getOperand(0).getReg());
597 DecodeMOVLHPSMask(2, ShuffleMask);
598 break;
599
600 case X86::MOVHLPSrr:
601 case X86::VMOVHLPSrr:
602 case X86::VMOVHLPSZrr:
603 Src2Name = getRegName(MI->getOperand(2).getReg());
604 Src1Name = getRegName(MI->getOperand(1).getReg());
605 DestName = getRegName(MI->getOperand(0).getReg());
606 DecodeMOVHLPSMask(2, ShuffleMask);
607 break;
608
609 case X86::MOVHPDrm:
610 case X86::VMOVHPDrm:
611 case X86::VMOVHPDZ128rm:
612 Src1Name = getRegName(MI->getOperand(1).getReg());
613 DestName = getRegName(MI->getOperand(0).getReg());
614 DecodeInsertElementMask(2, 1, 1, ShuffleMask);
615 break;
616
617 case X86::MOVHPSrm:
618 case X86::VMOVHPSrm:
619 case X86::VMOVHPSZ128rm:
620 Src1Name = getRegName(MI->getOperand(1).getReg());
621 DestName = getRegName(MI->getOperand(0).getReg());
622 DecodeInsertElementMask(4, 2, 2, ShuffleMask);
623 break;
624
625 case X86::MOVLPDrm:
626 case X86::VMOVLPDrm:
627 case X86::VMOVLPDZ128rm:
628 Src1Name = getRegName(MI->getOperand(1).getReg());
629 DestName = getRegName(MI->getOperand(0).getReg());
630 DecodeInsertElementMask(2, 0, 1, ShuffleMask);
631 break;
632
633 case X86::MOVLPSrm:
634 case X86::VMOVLPSrm:
635 case X86::VMOVLPSZ128rm:
636 Src1Name = getRegName(MI->getOperand(1).getReg());
637 DestName = getRegName(MI->getOperand(0).getReg());
638 DecodeInsertElementMask(4, 0, 2, ShuffleMask);
639 break;
640
641 CASE_MOVDUP(MOVSLDUP, r)
642 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
643 LLVM_FALLTHROUGH;
644
645 CASE_MOVDUP(MOVSLDUP, m)
646 DestName = getRegName(MI->getOperand(0).getReg());
647 DecodeMOVSLDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
648 break;
649
650 CASE_MOVDUP(MOVSHDUP, r)
651 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
652 LLVM_FALLTHROUGH;
653
654 CASE_MOVDUP(MOVSHDUP, m)
655 DestName = getRegName(MI->getOperand(0).getReg());
656 DecodeMOVSHDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
657 break;
658
659 CASE_MOVDUP(MOVDDUP, r)
660 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
661 LLVM_FALLTHROUGH;
662
663 CASE_MOVDUP(MOVDDUP, m)
664 DestName = getRegName(MI->getOperand(0).getReg());
665 DecodeMOVDDUPMask(getRegOperandNumElts(MI, 64, 0), ShuffleMask);
666 break;
667
668 case X86::PSLLDQri:
669 case X86::VPSLLDQri:
670 case X86::VPSLLDQYri:
671 case X86::VPSLLDQZ128rr:
672 case X86::VPSLLDQZ256rr:
673 case X86::VPSLLDQZrr:
674 Src1Name = getRegName(MI->getOperand(1).getReg());
675 LLVM_FALLTHROUGH;
676 case X86::VPSLLDQZ128rm:
677 case X86::VPSLLDQZ256rm:
678 case X86::VPSLLDQZrm:
679 DestName = getRegName(MI->getOperand(0).getReg());
680 if (MI->getOperand(NumOperands - 1).isImm())
681 DecodePSLLDQMask(getRegOperandNumElts(MI, 8, 0),
682 MI->getOperand(NumOperands - 1).getImm(),
683 ShuffleMask);
684 break;
685
686 case X86::PSRLDQri:
687 case X86::VPSRLDQri:
688 case X86::VPSRLDQYri:
689 case X86::VPSRLDQZ128rr:
690 case X86::VPSRLDQZ256rr:
691 case X86::VPSRLDQZrr:
692 Src1Name = getRegName(MI->getOperand(1).getReg());
693 LLVM_FALLTHROUGH;
694 case X86::VPSRLDQZ128rm:
695 case X86::VPSRLDQZ256rm:
696 case X86::VPSRLDQZrm:
697 DestName = getRegName(MI->getOperand(0).getReg());
698 if (MI->getOperand(NumOperands - 1).isImm())
699 DecodePSRLDQMask(getRegOperandNumElts(MI, 8, 0),
700 MI->getOperand(NumOperands - 1).getImm(),
701 ShuffleMask);
702 break;
703
704 CASE_SHUF(PALIGNR, rri)
705 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
706 RegForm = true;
707 LLVM_FALLTHROUGH;
708
709 CASE_SHUF(PALIGNR, rmi)
710 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
711 DestName = getRegName(MI->getOperand(0).getReg());
712 if (MI->getOperand(NumOperands - 1).isImm())
713 DecodePALIGNRMask(getRegOperandNumElts(MI, 8, 0),
714 MI->getOperand(NumOperands - 1).getImm(),
715 ShuffleMask);
716 break;
717
718 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri)
719 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri)
720 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri)
721 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
722 RegForm = true;
723 LLVM_FALLTHROUGH;
724
725 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi)
726 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi)
727 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi)
728 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
729 DestName = getRegName(MI->getOperand(0).getReg());
730 if (MI->getOperand(NumOperands - 1).isImm())
731 DecodeVALIGNMask(getRegOperandNumElts(MI, 64, 0),
732 MI->getOperand(NumOperands - 1).getImm(),
733 ShuffleMask);
734 break;
735
736 CASE_AVX512_INS_COMMON(ALIGND, Z, rri)
737 CASE_AVX512_INS_COMMON(ALIGND, Z256, rri)
738 CASE_AVX512_INS_COMMON(ALIGND, Z128, rri)
739 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
740 RegForm = true;
741 LLVM_FALLTHROUGH;
742
743 CASE_AVX512_INS_COMMON(ALIGND, Z, rmi)
744 CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi)
745 CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi)
746 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
747 DestName = getRegName(MI->getOperand(0).getReg());
748 if (MI->getOperand(NumOperands - 1).isImm())
749 DecodeVALIGNMask(getRegOperandNumElts(MI, 32, 0),
750 MI->getOperand(NumOperands - 1).getImm(),
751 ShuffleMask);
752 break;
753
754 CASE_SHUF(PSHUFD, ri)
755 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
756 LLVM_FALLTHROUGH;
757
758 CASE_SHUF(PSHUFD, mi)
759 DestName = getRegName(MI->getOperand(0).getReg());
760 if (MI->getOperand(NumOperands - 1).isImm())
761 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
762 MI->getOperand(NumOperands - 1).getImm(),
763 ShuffleMask);
764 break;
765
766 CASE_SHUF(PSHUFHW, ri)
767 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
768 LLVM_FALLTHROUGH;
769
770 CASE_SHUF(PSHUFHW, mi)
771 DestName = getRegName(MI->getOperand(0).getReg());
772 if (MI->getOperand(NumOperands - 1).isImm())
773 DecodePSHUFHWMask(getRegOperandNumElts(MI, 16, 0),
774 MI->getOperand(NumOperands - 1).getImm(),
775 ShuffleMask);
776 break;
777
778 CASE_SHUF(PSHUFLW, ri)
779 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
780 LLVM_FALLTHROUGH;
781
782 CASE_SHUF(PSHUFLW, mi)
783 DestName = getRegName(MI->getOperand(0).getReg());
784 if (MI->getOperand(NumOperands - 1).isImm())
785 DecodePSHUFLWMask(getRegOperandNumElts(MI, 16, 0),
786 MI->getOperand(NumOperands - 1).getImm(),
787 ShuffleMask);
788 break;
789
790 case X86::MMX_PSHUFWri:
791 Src1Name = getRegName(MI->getOperand(1).getReg());
792 LLVM_FALLTHROUGH;
793
794 case X86::MMX_PSHUFWmi:
795 DestName = getRegName(MI->getOperand(0).getReg());
796 if (MI->getOperand(NumOperands - 1).isImm())
797 DecodePSHUFMask(4, 16, MI->getOperand(NumOperands - 1).getImm(),
798 ShuffleMask);
799 break;
800
801 case X86::PSWAPDrr:
802 Src1Name = getRegName(MI->getOperand(1).getReg());
803 LLVM_FALLTHROUGH;
804
805 case X86::PSWAPDrm:
806 DestName = getRegName(MI->getOperand(0).getReg());
807 DecodePSWAPMask(2, ShuffleMask);
808 break;
809
810 CASE_UNPCK(PUNPCKHBW, r)
811 case X86::MMX_PUNPCKHBWirr:
812 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
813 RegForm = true;
814 LLVM_FALLTHROUGH;
815
816 CASE_UNPCK(PUNPCKHBW, m)
817 case X86::MMX_PUNPCKHBWirm:
818 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
819 DestName = getRegName(MI->getOperand(0).getReg());
820 DecodeUNPCKHMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
821 break;
822
823 CASE_UNPCK(PUNPCKHWD, r)
824 case X86::MMX_PUNPCKHWDirr:
825 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
826 RegForm = true;
827 LLVM_FALLTHROUGH;
828
829 CASE_UNPCK(PUNPCKHWD, m)
830 case X86::MMX_PUNPCKHWDirm:
831 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
832 DestName = getRegName(MI->getOperand(0).getReg());
833 DecodeUNPCKHMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
834 break;
835
836 CASE_UNPCK(PUNPCKHDQ, r)
837 case X86::MMX_PUNPCKHDQirr:
838 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
839 RegForm = true;
840 LLVM_FALLTHROUGH;
841
842 CASE_UNPCK(PUNPCKHDQ, m)
843 case X86::MMX_PUNPCKHDQirm:
844 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
845 DestName = getRegName(MI->getOperand(0).getReg());
846 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
847 break;
848
849 CASE_UNPCK(PUNPCKHQDQ, r)
850 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
851 RegForm = true;
852 LLVM_FALLTHROUGH;
853
854 CASE_UNPCK(PUNPCKHQDQ, m)
855 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
856 DestName = getRegName(MI->getOperand(0).getReg());
857 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
858 break;
859
860 CASE_UNPCK(PUNPCKLBW, r)
861 case X86::MMX_PUNPCKLBWirr:
862 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
863 RegForm = true;
864 LLVM_FALLTHROUGH;
865
866 CASE_UNPCK(PUNPCKLBW, m)
867 case X86::MMX_PUNPCKLBWirm:
868 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
869 DestName = getRegName(MI->getOperand(0).getReg());
870 DecodeUNPCKLMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
871 break;
872
873 CASE_UNPCK(PUNPCKLWD, r)
874 case X86::MMX_PUNPCKLWDirr:
875 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
876 RegForm = true;
877 LLVM_FALLTHROUGH;
878
879 CASE_UNPCK(PUNPCKLWD, m)
880 case X86::MMX_PUNPCKLWDirm:
881 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
882 DestName = getRegName(MI->getOperand(0).getReg());
883 DecodeUNPCKLMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
884 break;
885
886 CASE_UNPCK(PUNPCKLDQ, r)
887 case X86::MMX_PUNPCKLDQirr:
888 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
889 RegForm = true;
890 LLVM_FALLTHROUGH;
891
892 CASE_UNPCK(PUNPCKLDQ, m)
893 case X86::MMX_PUNPCKLDQirm:
894 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
895 DestName = getRegName(MI->getOperand(0).getReg());
896 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
897 break;
898
899 CASE_UNPCK(PUNPCKLQDQ, r)
900 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
901 RegForm = true;
902 LLVM_FALLTHROUGH;
903
904 CASE_UNPCK(PUNPCKLQDQ, m)
905 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
906 DestName = getRegName(MI->getOperand(0).getReg());
907 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
908 break;
909
910 CASE_SHUF(SHUFPD, rri)
911 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
912 RegForm = true;
913 LLVM_FALLTHROUGH;
914
915 CASE_SHUF(SHUFPD, rmi)
916 if (MI->getOperand(NumOperands - 1).isImm())
917 DecodeSHUFPMask(getRegOperandNumElts(MI, 64, 0), 64,
918 MI->getOperand(NumOperands - 1).getImm(), ShuffleMask);
919 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
920 DestName = getRegName(MI->getOperand(0).getReg());
921 break;
922
923 CASE_SHUF(SHUFPS, rri)
924 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
925 RegForm = true;
926 LLVM_FALLTHROUGH;
927
928 CASE_SHUF(SHUFPS, rmi)
929 if (MI->getOperand(NumOperands - 1).isImm())
930 DecodeSHUFPMask(getRegOperandNumElts(MI, 32, 0), 32,
931 MI->getOperand(NumOperands - 1).getImm(),
932 ShuffleMask);
933 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
934 DestName = getRegName(MI->getOperand(0).getReg());
935 break;
936
937 CASE_VSHUF(64X2, r)
938 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
939 RegForm = true;
940 LLVM_FALLTHROUGH;
941
942 CASE_VSHUF(64X2, m)
943 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 64, 0), 64,
944 MI->getOperand(NumOperands - 1).getImm(),
945 ShuffleMask);
946 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
947 DestName = getRegName(MI->getOperand(0).getReg());
948 break;
949
950 CASE_VSHUF(32X4, r)
951 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
952 RegForm = true;
953 LLVM_FALLTHROUGH;
954
955 CASE_VSHUF(32X4, m)
956 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 32, 0), 32,
957 MI->getOperand(NumOperands - 1).getImm(),
958 ShuffleMask);
959 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
960 DestName = getRegName(MI->getOperand(0).getReg());
961 break;
962
963 CASE_UNPCK(UNPCKLPD, r)
964 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
965 RegForm = true;
966 LLVM_FALLTHROUGH;
967
968 CASE_UNPCK(UNPCKLPD, m)
969 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
970 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
971 DestName = getRegName(MI->getOperand(0).getReg());
972 break;
973
974 CASE_UNPCK(UNPCKLPS, r)
975 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
976 RegForm = true;
977 LLVM_FALLTHROUGH;
978
979 CASE_UNPCK(UNPCKLPS, m)
980 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
981 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
982 DestName = getRegName(MI->getOperand(0).getReg());
983 break;
984
985 CASE_UNPCK(UNPCKHPD, r)
986 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
987 RegForm = true;
988 LLVM_FALLTHROUGH;
989
990 CASE_UNPCK(UNPCKHPD, m)
991 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
992 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
993 DestName = getRegName(MI->getOperand(0).getReg());
994 break;
995
996 CASE_UNPCK(UNPCKHPS, r)
997 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
998 RegForm = true;
999 LLVM_FALLTHROUGH;
1000
1001 CASE_UNPCK(UNPCKHPS, m)
1002 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1003 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1004 DestName = getRegName(MI->getOperand(0).getReg());
1005 break;
1006
1007 CASE_VPERMILPI(PERMILPS, r)
1008 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1009 LLVM_FALLTHROUGH;
1010
1011 CASE_VPERMILPI(PERMILPS, m)
1012 if (MI->getOperand(NumOperands - 1).isImm())
1013 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
1014 MI->getOperand(NumOperands - 1).getImm(),
1015 ShuffleMask);
1016 DestName = getRegName(MI->getOperand(0).getReg());
1017 break;
1018
1019 CASE_VPERMILPI(PERMILPD, r)
1020 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1021 LLVM_FALLTHROUGH;
1022
1023 CASE_VPERMILPI(PERMILPD, m)
1024 if (MI->getOperand(NumOperands - 1).isImm())
1025 DecodePSHUFMask(getRegOperandNumElts(MI, 64, 0), 64,
1026 MI->getOperand(NumOperands - 1).getImm(),
1027 ShuffleMask);
1028 DestName = getRegName(MI->getOperand(0).getReg());
1029 break;
1030
1031 case X86::VPERM2F128rr:
1032 case X86::VPERM2I128rr:
1033 Src2Name = getRegName(MI->getOperand(2).getReg());
1034 LLVM_FALLTHROUGH;
1035
1036 case X86::VPERM2F128rm:
1037 case X86::VPERM2I128rm:
1038 // For instruction comments purpose, assume the 256-bit vector is v4i64.
1039 if (MI->getOperand(NumOperands - 1).isImm())
1040 DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(),
1041 ShuffleMask);
1042 Src1Name = getRegName(MI->getOperand(1).getReg());
1043 DestName = getRegName(MI->getOperand(0).getReg());
1044 break;
1045
1046 CASE_VPERM(PERMPD, r)
1047 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1048 LLVM_FALLTHROUGH;
1049
1050 CASE_VPERM(PERMPD, m)
1051 if (MI->getOperand(NumOperands - 1).isImm())
1052 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1053 MI->getOperand(NumOperands - 1).getImm(),
1054 ShuffleMask);
1055 DestName = getRegName(MI->getOperand(0).getReg());
1056 break;
1057
1058 CASE_VPERM(PERMQ, r)
1059 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1060 LLVM_FALLTHROUGH;
1061
1062 CASE_VPERM(PERMQ, m)
1063 if (MI->getOperand(NumOperands - 1).isImm())
1064 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1065 MI->getOperand(NumOperands - 1).getImm(),
1066 ShuffleMask);
1067 DestName = getRegName(MI->getOperand(0).getReg());
1068 break;
1069
1070 case X86::MOVSDrr:
1071 case X86::VMOVSDrr:
1072 case X86::VMOVSDZrr:
1073 Src2Name = getRegName(MI->getOperand(2).getReg());
1074 Src1Name = getRegName(MI->getOperand(1).getReg());
1075 LLVM_FALLTHROUGH;
1076
1077 case X86::MOVSDrm:
1078 case X86::VMOVSDrm:
1079 case X86::VMOVSDZrm:
1080 DecodeScalarMoveMask(2, nullptr == Src2Name, ShuffleMask);
1081 DestName = getRegName(MI->getOperand(0).getReg());
1082 break;
1083
1084 case X86::MOVSSrr:
1085 case X86::VMOVSSrr:
1086 case X86::VMOVSSZrr:
1087 Src2Name = getRegName(MI->getOperand(2).getReg());
1088 Src1Name = getRegName(MI->getOperand(1).getReg());
1089 LLVM_FALLTHROUGH;
1090
1091 case X86::MOVSSrm:
1092 case X86::VMOVSSrm:
1093 case X86::VMOVSSZrm:
1094 DecodeScalarMoveMask(4, nullptr == Src2Name, ShuffleMask);
1095 DestName = getRegName(MI->getOperand(0).getReg());
1096 break;
1097
1098 case X86::MOVPQI2QIrr:
1099 case X86::MOVZPQILo2PQIrr:
1100 case X86::VMOVPQI2QIrr:
1101 case X86::VMOVPQI2QIZrr:
1102 case X86::VMOVZPQILo2PQIrr:
1103 case X86::VMOVZPQILo2PQIZrr:
1104 Src1Name = getRegName(MI->getOperand(1).getReg());
1105 LLVM_FALLTHROUGH;
1106
1107 case X86::MOVQI2PQIrm:
1108 case X86::VMOVQI2PQIrm:
1109 case X86::VMOVQI2PQIZrm:
1110 DecodeZeroMoveLowMask(2, ShuffleMask);
1111 DestName = getRegName(MI->getOperand(0).getReg());
1112 break;
1113
1114 case X86::MOVDI2PDIrm:
1115 case X86::VMOVDI2PDIrm:
1116 case X86::VMOVDI2PDIZrm:
1117 DecodeZeroMoveLowMask(4, ShuffleMask);
1118 DestName = getRegName(MI->getOperand(0).getReg());
1119 break;
1120
1121 case X86::EXTRQI:
1122 if (MI->getOperand(2).isImm() &&
1123 MI->getOperand(3).isImm())
1124 DecodeEXTRQIMask(16, 8, MI->getOperand(2).getImm(),
1125 MI->getOperand(3).getImm(), ShuffleMask);
1126
1127 DestName = getRegName(MI->getOperand(0).getReg());
1128 Src1Name = getRegName(MI->getOperand(1).getReg());
1129 break;
1130
1131 case X86::INSERTQI:
1132 if (MI->getOperand(3).isImm() &&
1133 MI->getOperand(4).isImm())
1134 DecodeINSERTQIMask(16, 8, MI->getOperand(3).getImm(),
1135 MI->getOperand(4).getImm(), ShuffleMask);
1136
1137 DestName = getRegName(MI->getOperand(0).getReg());
1138 Src1Name = getRegName(MI->getOperand(1).getReg());
1139 Src2Name = getRegName(MI->getOperand(2).getReg());
1140 break;
1141
1142 case X86::VBROADCASTF128:
1143 case X86::VBROADCASTI128:
1144 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
1145 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
1146 DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1147 DestName = getRegName(MI->getOperand(0).getReg());
1148 break;
1149 CASE_AVX512_INS_COMMON(BROADCASTF64X2, , rm)
1150 CASE_AVX512_INS_COMMON(BROADCASTI64X2, , rm)
1151 DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1152 DestName = getRegName(MI->getOperand(0).getReg());
1153 break;
1154 CASE_AVX512_INS_COMMON(BROADCASTF64X4, , rm)
1155 CASE_AVX512_INS_COMMON(BROADCASTI64X4, , rm)
1156 DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1157 DestName = getRegName(MI->getOperand(0).getReg());
1158 break;
1159 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm)
1160 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm)
1161 DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1162 DestName = getRegName(MI->getOperand(0).getReg());
1163 break;
1164 CASE_AVX512_INS_COMMON(BROADCASTF32X4, , rm)
1165 CASE_AVX512_INS_COMMON(BROADCASTI32X4, , rm)
1166 DecodeSubVectorBroadcast(16, 4, ShuffleMask);
1167 DestName = getRegName(MI->getOperand(0).getReg());
1168 break;
1169 CASE_AVX512_INS_COMMON(BROADCASTF32X8, , rm)
1170 CASE_AVX512_INS_COMMON(BROADCASTI32X8, , rm)
1171 DecodeSubVectorBroadcast(16, 8, ShuffleMask);
1172 DestName = getRegName(MI->getOperand(0).getReg());
1173 break;
1174 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, r)
1175 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1176 LLVM_FALLTHROUGH;
1177 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, m)
1178 DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1179 DestName = getRegName(MI->getOperand(0).getReg());
1180 break;
1181 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, r)
1182 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, r)
1183 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1184 LLVM_FALLTHROUGH;
1185 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, m)
1186 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, m)
1187 DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1188 DestName = getRegName(MI->getOperand(0).getReg());
1189 break;
1190 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, r)
1191 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, r)
1192 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1193 LLVM_FALLTHROUGH;
1194 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, m)
1195 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, m)
1196 DecodeSubVectorBroadcast(16, 2, ShuffleMask);
1197 DestName = getRegName(MI->getOperand(0).getReg());
1198 break;
1199
1200 CASE_PMOVZX(PMOVZXBW, r)
1201 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1202 LLVM_FALLTHROUGH;
1203 CASE_PMOVZX(PMOVZXBW, m)
1204 DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), ShuffleMask);
1205 DestName = getRegName(MI->getOperand(0).getReg());
1206 break;
1207
1208 CASE_PMOVZX(PMOVZXBD, r)
1209 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1210 LLVM_FALLTHROUGH;
1211 CASE_PMOVZX(PMOVZXBD, m)
1212 DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), ShuffleMask);
1213 DestName = getRegName(MI->getOperand(0).getReg());
1214 break;
1215
1216 CASE_PMOVZX(PMOVZXBQ, r)
1217 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1218 LLVM_FALLTHROUGH;
1219 CASE_PMOVZX(PMOVZXBQ, m)
1220 DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);
1221 DestName = getRegName(MI->getOperand(0).getReg());
1222 break;
1223
1224 CASE_PMOVZX(PMOVZXWD, r)
1225 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1226 LLVM_FALLTHROUGH;
1227 CASE_PMOVZX(PMOVZXWD, m)
1228 DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), ShuffleMask);
1229 DestName = getRegName(MI->getOperand(0).getReg());
1230 break;
1231
1232 CASE_PMOVZX(PMOVZXWQ, r)
1233 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1234 LLVM_FALLTHROUGH;
1235 CASE_PMOVZX(PMOVZXWQ, m)
1236 DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);
1237 DestName = getRegName(MI->getOperand(0).getReg());
1238 break;
1239
1240 CASE_PMOVZX(PMOVZXDQ, r)
1241 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1242 LLVM_FALLTHROUGH;
1243 CASE_PMOVZX(PMOVZXDQ, m)
1244 DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);
1245 DestName = getRegName(MI->getOperand(0).getReg());
1246 break;
1247 }
1248
1249 // The only comments we decode are shuffles, so give up if we were unable to
1250 // decode a shuffle mask.
1251 if (ShuffleMask.empty())
1252 return false;
1253
1254 if (!DestName) DestName = Src1Name;
1255 if (DestName) {
1256 OS << DestName;
1257 printMasking(OS, MI, MCII);
1258 } else
1259 OS << "mem";
1260
1261 OS << " = ";
1262
1263 // If the two sources are the same, canonicalize the input elements to be
1264 // from the first src so that we get larger element spans.
1265 if (Src1Name == Src2Name) {
1266 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1267 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
1268 ShuffleMask[i] >= (int)e) // From second mask.
1269 ShuffleMask[i] -= e;
1270 }
1271 }
1272
1273 // The shuffle mask specifies which elements of the src1/src2 fill in the
1274 // destination, with a few sentinel values. Loop through and print them
1275 // out.
1276 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1277 if (i != 0)
1278 OS << ',';
1279 if (ShuffleMask[i] == SM_SentinelZero) {
1280 OS << "zero";
1281 continue;
1282 }
1283
1284 // Otherwise, it must come from src1 or src2. Print the span of elements
1285 // that comes from this src.
1286 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1287 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1288 OS << (SrcName ? SrcName : "mem") << '[';
1289 bool IsFirst = true;
1290 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1291 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1292 if (!IsFirst)
1293 OS << ',';
1294 else
1295 IsFirst = false;
1296 if (ShuffleMask[i] == SM_SentinelUndef)
1297 OS << "u";
1298 else
1299 OS << ShuffleMask[i] % ShuffleMask.size();
1300 ++i;
1301 }
1302 OS << ']';
1303 --i; // For loop increments element #.
1304 }
1305 OS << '\n';
1306
1307 // We successfully added a comment to this instruction.
1308 return true;
1309 }
+0
-26
lib/Target/X86/InstPrinter/X86InstComments.h less more
None //=- X86InstComments.h - Generate verbose-asm comments for instrs -*- C++ -*-=//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This defines functionality used to emit comments about X86 instructions to
9 // an output stream for -fverbose-asm.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_X86_INSTPRINTER_X86INSTCOMMENTS_H
14 #define LLVM_LIB_TARGET_X86_INSTPRINTER_X86INSTCOMMENTS_H
15
16 namespace llvm {
17
18 class MCInst;
19 class MCInstrInfo;
20 class raw_ostream;
21 bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
22 const MCInstrInfo &MCII);
23 }
24
25 #endif
+0
-337
lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp less more
None //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This file includes common code for rendering MCInst instances as Intel-style
9 // and Intel-style assembly.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86InstPrinterCommon.h"
14 #include "MCTargetDesc/X86BaseInfo.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/Support/raw_ostream.h"
20 #include "llvm/Support/Casting.h"
21 #include
22 #include
23
24 using namespace llvm;
25
26 void X86InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op,
27 raw_ostream &O) {
28 int64_t Imm = MI->getOperand(Op).getImm();
29 switch (Imm) {
30 default: llvm_unreachable("Invalid condcode argument!");
31 case 0: O << "o"; break;
32 case 1: O << "no"; break;
33 case 2: O << "b"; break;
34 case 3: O << "ae"; break;
35 case 4: O << "e"; break;
36 case 5: O << "ne"; break;
37 case 6: O << "be"; break;
38 case 7: O << "a"; break;
39 case 8: O << "s"; break;
40 case 9: O << "ns"; break;
41 case 0xa: O << "p"; break;
42 case 0xb: O << "np"; break;
43 case 0xc: O << "l"; break;
44 case 0xd: O << "ge"; break;
45 case 0xe: O << "le"; break;
46 case 0xf: O << "g"; break;
47 }
48 }
49
50 void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op,
51 raw_ostream &O) {
52 int64_t Imm = MI->getOperand(Op).getImm();
53 switch (Imm) {
54 default: llvm_unreachable("Invalid ssecc/avxcc argument!");
55 case 0: O << "eq"; break;
56 case 1: O << "lt"; break;
57 case 2: O << "le"; break;
58 case 3: O << "unord"; break;
59 case 4: O << "neq"; break;
60 case 5: O << "nlt"; break;
61 case 6: O << "nle"; break;
62 case 7: O << "ord"; break;
63 case 8: O << "eq_uq"; break;
64 case 9: O << "nge"; break;
65 case 0xa: O << "ngt"; break;
66 case 0xb: O << "false"; break;
67 case 0xc: O << "neq_oq"; break;
68 case 0xd: O << "ge"; break;
69 case 0xe: O << "gt"; break;
70 case 0xf: O << "true"; break;
71 case 0x10: O << "eq_os"; break;
72 case 0x11: O << "lt_oq"; break;
73 case 0x12: O << "le_oq"; break;
74 case 0x13: O << "unord_s"; break;
75 case 0x14: O << "neq_us"; break;
76 case 0x15: O << "nlt_uq"; break;
77 case 0x16: O << "nle_uq"; break;
78 case 0x17: O << "ord_s"; break;
79 case 0x18: O << "eq_us"; break;
80 case 0x19: O << "nge_uq"; break;
81 case 0x1a: O << "ngt_uq"; break;
82 case 0x1b: O << "false_os"; break;
83 case 0x1c: O << "neq_os"; break;
84 case 0x1d: O << "ge_oq"; break;
85 case 0x1e: O << "gt_oq"; break;
86 case 0x1f: O << "true_us"; break;
87 }
88 }
89
90 void X86InstPrinterCommon::printVPCOMMnemonic(const MCInst *MI,
91 raw_ostream &OS) {
92 OS << "vpcom";
93
94 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
95 switch (Imm) {
96 default: llvm_unreachable("Invalid vpcom argument!");
97 case 0: OS << "lt"; break;
98 case 1: OS << "le"; break;
99 case 2: OS << "gt"; break;
100 case 3: OS << "ge"; break;
101 case 4: OS << "eq"; break;
102 case 5: OS << "neq"; break;
103 case 6: OS << "false"; break;
104 case 7: OS << "true"; break;
105 }
106
107 switch (MI->getOpcode()) {
108 default: llvm_unreachable("Unexpected opcode!");
109 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break;
110 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break;
111 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break;
112 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break;
113 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break;
114 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break;
115 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break;
116 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break;
117 }
118 }
119
120 void X86InstPrinterCommon::printVPCMPMnemonic(const MCInst *MI,
121 raw_ostream &OS) {
122 OS << "vpcmp";
123
124 printSSEAVXCC(MI, MI->getNumOperands() - 1, OS);
125
126 switch (MI->getOpcode()) {
127 default: llvm_unreachable("Unexpected opcode!");
128 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri:
129 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri:
130 case X86::VPCMPBZrmi: case X86::VPCMPBZrri:
131 case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik:
132 case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik:
133 case X86::VPCMPBZrmik: case X86::VPCMPBZrrik:
134 OS << "b\t";
135 break;
136 case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri:
137 case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri:
138 case X86::VPCMPDZrmi: case X86::VPCMPDZrri:
139 case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik:
140 case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik:
141 case X86::VPCMPDZrmik: case X86::VPCMPDZrrik:
142 case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk:
143 case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk:
144 case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk:
145 OS << "d\t";
146 break;
147 case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri:
148 case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri:
149 case X86::VPCMPQZrmi: case X86::VPCMPQZrri:
150 case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik:
151 case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik:
152 case X86::VPCMPQZrmik: case X86::VPCMPQZrrik:
153 case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk:
154 case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk:
155 case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk:
156 OS << "q\t";
157 break;
158 case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri:
159 case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri:
160 case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri:
161 case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
162 case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
163 case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik:
164 OS << "ub\t";
165 break;
166 case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri:
167 case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri:
168 case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri:
169 case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
170 case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
171 case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik:
172 case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk:
173 case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk:
174 case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk:
175 OS << "ud\t";
176 break;
177 case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri:
178 case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri:
179 case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri:
180 case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
181 case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
182 case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik:
183 case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk:
184 case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk:
185 case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk:
186 OS << "uq\t";
187 break;
188 case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri:
189 case X86::VPCMPUWZ256rri: case X86::VPCMPUWZ256rmi:
190 case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri:
191 case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
192 case X86::VPCMPUWZ256rrik: case X86::VPCMPUWZ256rmik:
193 case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik:
194 OS << "uw\t";
195 break;
196 case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri:
197 case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri:
198 case X86::VPCMPWZrmi: case X86::VPCMPWZrri:
199 case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik:
200 case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik:
201 case X86::VPCMPWZrmik: case X86::VPCMPWZrrik:
202 OS << "w\t";
203 break;
204 }
205 }
206
207 void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp,
208 raw_ostream &OS) {
209 OS << (IsVCmp ? "vcmp" : "cmp");
210
211 printSSEAVXCC(MI, MI->getNumOperands() - 1, OS);
212
213 switch (MI->getOpcode()) {
214 default: llvm_unreachable("Unexpected opcode!");
215 case X86::CMPPDrmi: case X86::CMPPDrri:
216 case X86::VCMPPDrmi: case X86::VCMPPDrri:
217 case X86::VCMPPDYrmi: case X86::VCMPPDYrri:
218 case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri:
219 case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri:
220 case X86::VCMPPDZrmi: case X86::VCMPPDZrri:
221 case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
222 case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
223 case X86::VCMPPDZrmik: case X86::VCMPPDZrrik:
224 case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
225 case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
226 case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
227 case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
228 OS << "pd\t";
229 break;
230 case X86::CMPPSrmi: case X86::CMPPSrri:
231 case X86::VCMPPSrmi: case X86::VCMPPSrri:
232 case X86::VCMPPSYrmi: case X86::VCMPPSYrri:
233 case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri:
234 case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri:
235 case X86::VCMPPSZrmi: case X86::VCMPPSZrri:
236 case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
237 case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
238 case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
239 case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
240 case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
241 case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
242 case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
243 OS << "ps\t";
244 break;
245 case X86::CMPSDrm: case X86::CMPSDrr:
246 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int:
247 case X86::VCMPSDrm: case X86::VCMPSDrr:
248 case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int:
249 case X86::VCMPSDZrm: case X86::VCMPSDZrr:
250 case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int:
251 case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk:
252 case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk:
253 OS << "sd\t";
254 break;
255 case X86::CMPSSrm: case X86::CMPSSrr:
256 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int:
257 case X86::VCMPSSrm: case X86::VCMPSSrr:
258 case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int:
259 case X86::VCMPSSZrm: case X86::VCMPSSZrr:
260 case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int:
261 case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk:
262 case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk:
263 OS << "ss\t";
264 break;
265 }
266 }
267
268 void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op,
269 raw_ostream &O) {
270 int64_t Imm = MI->getOperand(Op).getImm();
271 switch (Imm) {
272 default:
273 llvm_unreachable("Invalid rounding control!");
274 case X86::TO_NEAREST_INT:
275 O << "{rn-sae}";
276 break;
277 case X86::TO_NEG_INF:
278 O << "{rd-sae}";
279 break;
280 case X86::TO_POS_INF:
281 O << "{ru-sae}";
282 break;
283 case X86::TO_ZERO:
284 O << "{rz-sae}";
285 break;
286 }
287 }
288
289 /// printPCRelImm - This is used to print an immediate value that ends up
290 /// being encoded as a pc-relative value (e.g. for jumps and calls). In
291 /// Intel-style these print slightly differently than normal immediates.
292 /// for example, a $ is not emitted.
293 void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, unsigned OpNo,
294 raw_ostream &O) {
295 const MCOperand &Op = MI->getOperand(OpNo);
296 if (Op.isImm())
297 O << formatImm(Op.getImm());
298 else {
299 assert(Op.isExpr() && "unknown pcrel immediate operand");
300 // If a symbolic branch target was added as a constant expression then print
301 // that address in hex.
302 const MCConstantExpr *BranchTarget = dyn_cast(Op.getExpr());
303 int64_t Address;
304 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
305 O << formatHex((uint64_t)Address);
306 } else {
307 // Otherwise, just print the expression.
308 Op.getExpr()->print(O, &MAI);
309 }
310 }
311 }
312
313 void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo,
314 raw_ostream &O) {
315 if (MI->getOperand(OpNo).getReg()) {
316 printOperand(MI, OpNo, O);
317 O << ':';
318 }
319 }
320
321 void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O) {
322 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
323 uint64_t TSFlags = Desc.TSFlags;
324 unsigned Flags = MI->getFlags();
325
326 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK))
327 O << "\tlock\t";
328
329 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK))
330 O << "\tnotrack\t";
331
332 if (Flags & X86::IP_HAS_REPEAT_NE)
333 O << "\trepne\t";
334 else if (Flags & X86::IP_HAS_REPEAT)
335 O << "\trep\t";
336 }
+0
-40
lib/Target/X86/InstPrinter/X86InstPrinterCommon.h less more
None //===-- X86InstPrinterCommon.cpp - X86 assembly instruction printing ------===//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This file includes code common for rendering MCInst instances as AT&T-style
9 // and Intel-style assembly.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_X86_INSTPRINTER_X86INSTPRINTERCOMMON_H
14 #define LLVM_LIB_TARGET_X86_INSTPRINTER_X86INSTPRINTERCOMMON_H
15
16 #include "llvm/MC/MCInstPrinter.h"
17
18 namespace llvm {
19
20 class X86InstPrinterCommon : public MCInstPrinter {
21 public:
22 using MCInstPrinter::MCInstPrinter;
23
24 virtual void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) = 0;
25 void printCondCode(const MCInst *MI, unsigned Op, raw_ostream &OS);
26 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
27 void printVPCOMMnemonic(const MCInst *MI, raw_ostream &OS);
28 void printVPCMPMnemonic(const MCInst *MI, raw_ostream &OS);
29 void printCMPMnemonic(const MCInst *MI, bool IsVCmp, raw_ostream &OS);
30 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &O);
31 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
32 protected:
33 void printInstFlags(const MCInst *MI, raw_ostream &O);
34 void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
35 };
36
37 } // end namespace llvm
38
39 #endif // LLVM_LIB_TARGET_X86_INSTPRINTER_X86ATTINSTPRINTER_H
+0
-445
lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp less more
None //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This file includes code for rendering MCInst instances as Intel-style
9 // assembly.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86IntelInstPrinter.h"
14 #include "MCTargetDesc/X86BaseInfo.h"
15 #include "X86InstComments.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/Casting.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include
24 #include
25
26 using namespace llvm;
27
28 #define DEBUG_TYPE "asm-printer"
29
30 // Include the auto-generated portion of the assembly writer.
31 #define PRINT_ALIAS_INSTR
32 #include "X86GenAsmWriter1.inc"
33
34 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
35 OS << getRegisterName(RegNo);
36 }
37
38 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
39 StringRef Annot,
40 const MCSubtargetInfo &STI) {
41 printInstFlags(MI, OS);
42
43 // In 16-bit mode, print data16 as data32.
44 if (MI->getOpcode() == X86::DATA16_PREFIX &&
45 STI.getFeatureBits()[X86::Mode16Bit]) {
46 OS << "\tdata32";
47 } else if (!printAliasInstr(MI, OS) &&
48 !printVecCompareInstr(MI, OS))
49 printInstruction(MI, OS);
50
51 // Next always print the annotation.
52 printAnnotation(OS, Annot);
53
54 // If verbose assembly is enabled, we can print some informative comments.
55 if (CommentStream)
56 EmitAnyX86InstComments(MI, *CommentStream, MII);
57 }
58
59 bool X86IntelInstPrinter::printVecCompareInstr(const MCInst *MI, raw_ostream &OS) {
60 if (MI->getNumOperands() == 0 ||
61 !MI->getOperand(MI->getNumOperands() - 1).isImm())
62 return false;
63
64 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
65
66 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
67
68 // Custom print the vector compare instructions to get the immediate
69 // translated into the mnemonic.
70 switch (MI->getOpcode()) {
71 case X86::CMPPDrmi: case X86::CMPPDrri:
72 case X86::CMPPSrmi: case X86::CMPPSrri:
73 case X86::CMPSDrm: case X86::CMPSDrr:
74 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int:
75 case X86::CMPSSrm: case X86::CMPSSrr:
76 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int:
77 if (Imm >= 0 && Imm <= 7) {
78 OS << '\t';
79 printCMPMnemonic(MI, /*IsVCMP*/false, OS);
80 printOperand(MI, 0, OS);
81 OS << ", ";
82 // Skip operand 1 as its tied to the dest.
83
84 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
85 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
86 printdwordmem(MI, 2, OS);
87 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
88 printqwordmem(MI, 2, OS);
89 else
90 printxmmwordmem(MI, 2, OS);
91 } else
92 printOperand(MI, 2, OS);
93
94 return true;
95 }
96 break;
97
98 case X86::VCMPPDrmi: case X86::VCMPPDrri:
99 case X86::VCMPPDYrmi: case X86::VCMPPDYrri:
100 case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri:
101 case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri:
102 case X86::VCMPPDZrmi: case X86::VCMPPDZrri:
103 case X86::VCMPPSrmi: case X86::VCMPPSrri:
104 case X86::VCMPPSYrmi: case X86::VCMPPSYrri:
105 case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri:
106 case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri:
107 case X86::VCMPPSZrmi: case X86::VCMPPSZrri:
108 case X86::VCMPSDrm: case X86::VCMPSDrr:
109 case X86::VCMPSDZrm: case X86::VCMPSDZrr:
110 case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int:
111 case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int:
112 case X86::VCMPSSrm: case X86::VCMPSSrr:
113 case X86::VCMPSSZrm: case X86::VCMPSSZrr:
114 case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int:
115 case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int:
116 case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
117 case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
118 case X86::VCMPPDZrmik: case X86::VCMPPDZrrik:
119 case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
120 case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
121 case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
122 case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk:
123 case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk:
124 case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
125 case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
126 case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
127 case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
128 case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
129 case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
130 case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
131 case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
132 case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk:
133 case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk:
134 if (Imm >= 0 && Imm <= 31) {
135 OS << '\t';
136 printCMPMnemonic(MI, /*IsVCMP*/true, OS);
137
138 unsigned CurOp = 0;
139 printOperand(MI, CurOp++, OS);
140
141 if (Desc.TSFlags & X86II::EVEX_K) {
142 // Print mask operand.
143 OS << " {";
144 printOperand(MI, CurOp++, OS);
145 OS << "}";
146 }
147 OS << ", ";
148 printOperand(MI, CurOp++, OS);
149 OS << ", ";
150
151 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
152 if (Desc.TSFlags & X86II::EVEX_B) {
153 // Broadcast form.
154 // Load size is based on W-bit.
155 if (Desc.TSFlags & X86II::VEX_W)
156 printqwordmem(MI, CurOp++, OS);
157 else
158 printdwordmem(MI, CurOp++, OS);
159
160 // Print the number of elements broadcasted.
161 unsigned NumElts;
162 if (Desc.TSFlags & X86II::EVEX_L2)
163 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
164 else if (Desc.TSFlags & X86II::VEX_L)
165 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
166 else
167 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
168 OS << "{1to" << NumElts << "}";
169 } else {
170 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
171 printdwordmem(MI, CurOp++, OS);
172 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
173 printqwordmem(MI, CurOp++, OS);
174 else if (Desc.TSFlags & X86II::EVEX_L2)
175 printzmmwordmem(MI, CurOp++, OS);
176 else if (Desc.TSFlags & X86II::VEX_L)
177 printymmwordmem(MI, CurOp++, OS);
178 else
179 printxmmwordmem(MI, CurOp++, OS);
180 }
181 } else {
182 printOperand(MI, CurOp++, OS);
183 if (Desc.TSFlags & X86II::EVEX_B)
184 OS << ", {sae}";
185 }
186
187 return true;
188 }
189 break;
190
191 case X86::VPCOMBmi: case X86::VPCOMBri:
192 case X86::VPCOMDmi: case X86::VPCOMDri:
193 case X86::VPCOMQmi: case X86::VPCOMQri:
194 case X86::VPCOMUBmi: case X86::VPCOMUBri:
195 case X86::VPCOMUDmi: case X86::VPCOMUDri:
196 case X86::VPCOMUQmi: case X86::VPCOMUQri:
197 case X86::VPCOMUWmi: case X86::VPCOMUWri:
198 case X86::VPCOMWmi: case X86::VPCOMWri:
199 if (Imm >= 0 && Imm <= 7) {
200 OS << '\t';
201 printVPCOMMnemonic(MI, OS);
202 printOperand(MI, 0, OS);
203 OS << ", ";
204 printOperand(MI, 1, OS);
205 OS << ", ";
206 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem)
207 printxmmwordmem(MI, 2, OS);
208 else
209 printOperand(MI, 2, OS);
210 return true;
211 }
212 break;
213
214 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri:
215 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri:
216 case X86::VPCMPBZrmi: case X86::VPCMPBZrri:
217 case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri:
218 case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri:
219 case X86::VPCMPDZrmi: case X86::VPCMPDZrri:
220 case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri:
221 case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri:
222 case X86::VPCMPQZrmi: case X86::VPCMPQZrri:
223 case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri:
224 case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri:
225 case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri:
226 case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri:
227 case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri:
228 case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri:
229 case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri:
230 case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri:
231 case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri:
232 case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri:
233 case X86::VPCMPUWZ256rmi: case X86::VPCMPUWZ256rri:
234 case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri:
235 case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri:
236 case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri:
237 case X86::VPCMPWZrmi: case X86::VPCMPWZrri:
238 case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik:
239 case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik:
240 case X86::VPCMPBZrmik: case X86::VPCMPBZrrik:
241 case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik:
242 case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik:
243 case X86::VPCMPDZrmik: case X86::VPCMPDZrrik:
244 case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik:
245 case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik:
246 case X86::VPCMPQZrmik: case X86::VPCMPQZrrik:
247 case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
248 case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
249 case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik:
250 case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
251 case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
252 case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik:
253 case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
254 case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
255 case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik:
256 case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
257 case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik:
258 case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik:
259 case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik:
260 case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik:
261 case X86::VPCMPWZrmik: case X86::VPCMPWZrrik:
262 case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk:
263 case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk:
264 case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk:
265 case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk:
266 case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk:
267 case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk:
268 case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk:
269 case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk:
270 case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk:
271 case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk:
272 case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk:
273 case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk:
274 if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) {
275 OS << '\t';
276 printVPCMPMnemonic(MI, OS);
277
278 unsigned CurOp = 0;
279 printOperand(MI, CurOp++, OS);
280
281 if (Desc.TSFlags & X86II::EVEX_K) {
282 // Print mask operand.
283 OS << " {";
284 printOperand(MI, CurOp++, OS);
285 OS << "}";
286 }
287 OS << ", ";
288 printOperand(MI, CurOp++, OS);
289 OS << ", ";
290
291 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
292 if (Desc.TSFlags & X86II::EVEX_B) {
293 // Broadcast form.
294 // Load size is based on W-bit as only D and Q are supported.
295 if (Desc.TSFlags & X86II::VEX_W)
296 printqwordmem(MI, CurOp++, OS);
297 else
298 printdwordmem(MI, CurOp++, OS);
299
300 // Print the number of elements broadcasted.
301 unsigned NumElts;
302 if (Desc.TSFlags & X86II::EVEX_L2)
303 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
304 else if (Desc.TSFlags & X86II::VEX_L)
305 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
306 else
307 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
308 OS << "{1to" << NumElts << "}";
309 } else {
310 if (Desc.TSFlags & X86II::EVEX_L2)
311 printzmmwordmem(MI, CurOp++, OS);
312 else if (Desc.TSFlags & X86II::VEX_L)
313 printymmwordmem(MI, CurOp++, OS);
314 else
315 printxmmwordmem(MI, CurOp++, OS);
316 }
317 } else {
318 printOperand(MI, CurOp++, OS);
319 }
320
321 return true;
322 }
323 break;
324 }
325
326 return false;
327 }
328
329 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
330 raw_ostream &O) {
331 const MCOperand &Op = MI->getOperand(OpNo);
332 if (Op.isReg()) {
333 printRegName(O, Op.getReg());
334 } else if (Op.isImm()) {
335 O << formatImm((int64_t)Op.getImm());
336 } else {
337 assert(Op.isExpr() && "unknown operand kind in printOperand");
338 O << "offset ";
339 Op.getExpr()->print(O, &MAI);
340 }
341 }
342
343 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
344 raw_ostream &O) {
345 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
346 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
347 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
348 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
349
350 // If this has a segment register, print it.
351 printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
352
353 O << '[';
354
355 bool NeedPlus = false;
356 if (BaseReg.getReg()) {
357 printOperand(MI, Op+X86::AddrBaseReg, O);
358 NeedPlus = true;
359 }
360
361 if (IndexReg.getReg()) {
362 if (NeedPlus) O << " + ";
363 if (ScaleVal != 1)
364 O << ScaleVal << '*';
365 printOperand(MI, Op+X86::AddrIndexReg, O);
366 NeedPlus = true;
367 }
368
369 if (!DispSpec.isImm()) {
370 if (NeedPlus) O << " + ";
371 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
372 DispSpec.getExpr()->print(O, &MAI);
373 } else {
374 int64_t DispVal = DispSpec.getImm();
375 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
376 if (NeedPlus) {
377 if (DispVal > 0)
378 O << " + ";
379 else {
380 O << " - ";
381 DispVal = -DispVal;
382 }
383 }
384 O << formatImm(DispVal);
385 }
386 }
387
388 O << ']';
389 }
390
391 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
392 raw_ostream &O) {
393 // If this has a segment register, print it.
394 printOptionalSegReg(MI, Op + 1, O);
395 O << '[';
396 printOperand(MI, Op, O);
397 O << ']';
398 }
399
400 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
401 raw_ostream &O) {
402 // DI accesses are always ES-based.
403 O << "es:[";
404 printOperand(MI, Op, O);
405 O << ']';
406 }
407
408 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
409 raw_ostream &O) {
410 const MCOperand &DispSpec = MI->getOperand(Op);
411
412 // If this has a segment register, print it.
413 printOptionalSegReg(MI, Op + 1, O);
414
415 O << '[';
416
417 if (DispSpec.isImm()) {
418 O << formatImm(DispSpec.getImm());
419 } else {
420 assert(DispSpec.isExpr() && "non-immediate displacement?");
421 DispSpec.getExpr()->print(O, &MAI);
422 }
423
424 O << ']';
425 }
426
427 void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
428 raw_ostream &O) {
429 if (MI->getOperand(Op).isExpr())
430 return MI->getOperand(Op).getExpr()->print(O, &MAI);
431
432 O << formatImm(MI->getOperand(Op).getImm() & 0xff);
433 }
434
435 void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
436 raw_ostream &OS) {
437 const MCOperand &Op = MI->getOperand(OpNo);
438 unsigned Reg = Op.getReg();
439 // Override the default printing to print st(0) instead st.
440 if (Reg == X86::ST0)
441 OS << "st(0)";
442 else
443 printRegName(OS, Reg);
444 }
+0
-144
lib/Target/X86/InstPrinter/X86IntelInstPrinter.h less more
None //= X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This class prints an X86 MCInst to Intel style .s file syntax.
9 //
10 //===----------------------------------------------------------------------===//
11
12 #ifndef LLVM_LIB_TARGET_X86_INSTPRINTER_X86INTELINSTPRINTER_H
13 #define LLVM_LIB_TARGET_X86_INSTPRINTER_X86INTELINSTPRINTER_H
14
15 #include "X86InstPrinterCommon.h"
16 #include "llvm/Support/raw_ostream.h"
17
18 namespace llvm {
19
20 class X86IntelInstPrinter final : public X86InstPrinterCommon {
21 public:
22 X86IntelInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
23 const MCRegisterInfo &MRI)
24 : X86InstPrinterCommon(MAI, MII, MRI) {}
25
26 void printRegName(raw_ostream &OS, unsigned RegNo) const override;
27 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
28 const MCSubtargetInfo &STI) override;
29 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
30
31 // Autogenerated by tblgen, returns true if we successfully printed an
32 // alias.
33 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
35 unsigned PrintMethodIdx, raw_ostream &O);
36
37 // Autogenerated by tblgen.
38 void printInstruction(const MCInst *MI, raw_ostream &O);
39 static const char *getRegisterName(unsigned RegNo);
40
41 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override;
42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
43 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
45 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
46 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O);
47 void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
48
49 void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
50 printMemReference(MI, OpNo, O);
51 }
52
53 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
54 printMemReference(MI, OpNo, O);
55 }
56
57 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
58 O << "byte ptr ";
59 printMemReference(MI, OpNo, O);
60 }
61 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
62 O << "word ptr ";
63 printMemReference(MI, OpNo, O);
64 }
65 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
66 O << "dword ptr ";
67 printMemReference(MI, OpNo, O);
68 }
69 void printqwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
70 O << "qword ptr ";
71 printMemReference(MI, OpNo, O);
72 }
73 void printxmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
74 O << "xmmword ptr ";
75 printMemReference(MI, OpNo, O);
76 }
77 void printymmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
78 O << "ymmword ptr ";
79 printMemReference(MI, OpNo, O);
80 }
81 void printzmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
82 O << "zmmword ptr ";
83 printMemReference(MI, OpNo, O);
84 }
85 void printtbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
86 O << "tbyte ptr ";
87 printMemReference(MI, OpNo, O);
88 }
89
90
91 void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
92 O << "byte ptr ";
93 printSrcIdx(MI, OpNo, O);
94 }
95 void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
96 O << "word ptr ";
97 printSrcIdx(MI, OpNo, O);
98 }
99 void printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
100 O << "dword ptr ";
101 printSrcIdx(MI, OpNo, O);
102 }
103 void printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
104 O << "qword ptr ";
105 printSrcIdx(MI, OpNo, O);
106 }
107 void printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
108 O << "byte ptr ";
109 printDstIdx(MI, OpNo, O);
110 }
111 void printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
112 O << "word ptr ";
113 printDstIdx(MI, OpNo, O);
114 }
115 void printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
116 O << "dword ptr ";
117 printDstIdx(MI, OpNo, O);
118 }
119 void printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
120 O << "qword ptr ";
121 printDstIdx(MI, OpNo, O);
122 }
123 void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
124 O << "byte ptr ";
125 printMemOffset(MI, OpNo, O);
126 }
127 void printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
128 O << "word ptr ";
129 printMemOffset(MI, OpNo, O);
130 }
131 void printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
132 O << "dword ptr ";
133 printMemOffset(MI, OpNo, O);
134 }
135 void printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
136 O << "qword ptr ";
137 printMemOffset(MI, OpNo, O);
138 }
139 };
140
141 } // end namespace llvm
142
143 #endif // LLVM_LIB_TARGET_X86_INSTPRINTER_X86INTELINSTPRINTER_H
1414 ;===------------------------------------------------------------------------===;
1515
1616 [common]
17 subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils
17 subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo Utils
1818
1919 [component_0]
2020 type = TargetGroup
2929 type = Library
3030 name = X86CodeGen
3131 parent = X86
32 required_libraries = Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target X86AsmPrinter X86Desc X86Info X86Utils GlobalISel ProfileData
32 required_libraries = Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target X86Desc X86Info X86Utils GlobalISel ProfileData
3333 add_to_library_groups = X86
0 add_llvm_library(LLVMX86Desc
1 X86ATTInstPrinter.cpp
2 X86IntelInstPrinter.cpp
3 X86InstComments.cpp
4 X86InstPrinterCommon.cpp
15 X86AsmBackend.cpp
26 X86MCTargetDesc.cpp
37 X86MCAsmInfo.cpp
1717 type = Library
1818 name = X86Desc
1919 parent = X86
20 required_libraries = MC MCDisassembler Object Support X86AsmPrinter X86Info
20 required_libraries = MC MCDisassembler Object Support X86Info X86Utils
2121 add_to_library_groups = X86
0 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This file includes code for rendering MCInst instances as AT&T-style
9 // assembly.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86ATTInstPrinter.h"
14 #include "X86BaseInfo.h"
15 #include "X86InstComments.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Casting.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/Format.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include
25 #include
26 #include
27
28 using namespace llvm;
29
30 #define DEBUG_TYPE "asm-printer"
31
32 // Include the auto-generated portion of the assembly writer.
33 #define PRINT_ALIAS_INSTR
34 #include "X86GenAsmWriter.inc"
35
36 void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
37 OS << markup("");
38 }
39
40 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
41 StringRef Annot, const MCSubtargetInfo &STI) {
42 // If verbose assembly is enabled, we can print some informative comments.
43 if (CommentStream)
44 HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII);
45
46 printInstFlags(MI, OS);
47
48 // Output CALLpcrel32 as "callq" in 64-bit mode.
49 // In Intel annotation it's always emitted as "call".
50 //
51 // TODO: Probably this hack should be redesigned via InstAlias in
52 // InstrInfo.td as soon as Requires clause is supported properly
53 // for InstAlias.
54 if (MI->getOpcode() == X86::CALLpcrel32 &&
55 (STI.getFeatureBits()[X86::Mode64Bit])) {
56 OS << "\tcallq\t";
57 printPCRelImm(MI, 0, OS);
58 }
59 // data16 and data32 both have the same encoding of 0x66. While data32 is
60 // valid only in 16 bit systems, data16 is valid in the rest.
61 // There seems to be some lack of support of the Requires clause that causes
62 // 0x66 to be interpreted as "data16" by the asm printer.
63 // Thus we add an adjustment here in order to print the "right" instruction.
64 else if (MI->getOpcode() == X86::DATA16_PREFIX &&
65 STI.getFeatureBits()[X86::Mode16Bit]) {
66 OS << "\tdata32";
67 }
68 // Try to print any aliases first.
69 else if (!printAliasInstr(MI, OS) &&
70 !printVecCompareInstr(MI, OS))
71 printInstruction(MI, OS);
72
73 // Next always print the annotation.
74 printAnnotation(OS, Annot);
75 }
76
77 bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
78 raw_ostream &OS) {
79 if (MI->getNumOperands() == 0 ||
80 !MI->getOperand(MI->getNumOperands() - 1).isImm())
81 return false;
82
83 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
84
85 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
86
87 // Custom print the vector compare instructions to get the immediate
88 // translated into the mnemonic.
89 switch (MI->getOpcode()) {
90 case X86::CMPPDrmi: case X86::CMPPDrri:
91 case X86::CMPPSrmi: case X86::CMPPSrri:
92 case X86::CMPSDrm: case X86::CMPSDrr:
93 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int:
94 case X86::CMPSSrm: case X86::CMPSSrr:
95 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int:
96 if (Imm >= 0 && Imm <= 7) {
97 OS << '\t';
98 printCMPMnemonic(MI, /*IsVCMP*/false, OS);
99
100 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
101 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
102 printdwordmem(MI, 2, OS);
103 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
104 printqwordmem(MI, 2, OS);
105 else
106 printxmmwordmem(MI, 2, OS);
107 } else
108 printOperand(MI, 2, OS);
109
110 // Skip operand 1 as its tied to the dest.
111
112 OS << ", ";
113 printOperand(MI, 0, OS);
114 return true;
115 }
116 break;
117
118 case X86::VCMPPDrmi: case X86::VCMPPDrri:
119 case X86::VCMPPDYrmi: case X86::VCMPPDYrri:
120 case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri:
121 case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri:
122 case X86::VCMPPDZrmi: case X86::VCMPPDZrri:
123 case X86::VCMPPSrmi: case X86::VCMPPSrri:
124 case X86::VCMPPSYrmi: case X86::VCMPPSYrri:
125 case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri:
126 case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri:
127 case X86::VCMPPSZrmi: case X86::VCMPPSZrri:
128 case X86::VCMPSDrm: case X86::VCMPSDrr:
129 case X86::VCMPSDZrm: case X86::VCMPSDZrr:
130 case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int:
131 case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int:
132 case X86::VCMPSSrm: case X86::VCMPSSrr:
133 case X86::VCMPSSZrm: case X86::VCMPSSZrr:
134 case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int:
135 case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int:
136 case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
137 case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
138 case X86::VCMPPDZrmik: case X86::VCMPPDZrrik:
139 case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
140 case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
141 case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
142 case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk:
143 case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk:
144 case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
145 case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
146 case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
147 case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
148 case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
149 case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
150 case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
151 case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
152 case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk:
153 case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk:
154 if (Imm >= 0 && Imm <= 31) {
155 OS << '\t';
156 printCMPMnemonic(MI, /*IsVCMP*/true, OS);
157
158 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2;
159
160 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
161 if (Desc.TSFlags & X86II::EVEX_B) {
162 // Broadcast form.
163 // Load size is based on W-bit.
164 if (Desc.TSFlags & X86II::VEX_W)
165 printqwordmem(MI, CurOp--, OS);
166 else
167 printdwordmem(MI, CurOp--, OS);
168
169 // Print the number of elements broadcasted.
170 unsigned NumElts;
171 if (Desc.TSFlags & X86II::EVEX_L2)
172 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
173 else if (Desc.TSFlags & X86II::VEX_L)
174 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
175 else
176 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
177 OS << "{1to" << NumElts << "}";
178 } else {
179 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
180 printdwordmem(MI, CurOp--, OS);
181 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
182 printqwordmem(MI, CurOp--, OS);
183 else if (Desc.TSFlags & X86II::EVEX_L2)
184 printzmmwordmem(MI, CurOp--, OS);
185 else if (Desc.TSFlags & X86II::VEX_L)
186 printymmwordmem(MI, CurOp--, OS);
187 else
188 printxmmwordmem(MI, CurOp--, OS);
189 }
190 } else {
191 if (Desc.TSFlags & X86II::EVEX_B)
192 OS << "{sae}, ";
193 printOperand(MI, CurOp--, OS);
194 }
195
196 OS << ", ";
197 printOperand(MI, CurOp--, OS);
198 OS << ", ";
199 printOperand(MI, 0, OS);
200 if (CurOp > 0) {
201 // Print mask operand.
202 OS << " {";
203 printOperand(MI, CurOp--, OS);
204 OS << "}";
205 }
206
207 return true;
208 }
209 break;
210
211 case X86::VPCOMBmi: case X86::VPCOMBri:
212 case X86::VPCOMDmi: case X86::VPCOMDri:
213 case X86::VPCOMQmi: case X86::VPCOMQri:
214 case X86::VPCOMUBmi: case X86::VPCOMUBri:
215 case X86::VPCOMUDmi: case X86::VPCOMUDri:
216 case X86::VPCOMUQmi: case X86::VPCOMUQri:
217 case X86::VPCOMUWmi: case X86::VPCOMUWri:
218 case X86::VPCOMWmi: case X86::VPCOMWri:
219 if (Imm >= 0 && Imm <= 7) {
220 OS << '\t';
221 printVPCOMMnemonic(MI, OS);
222
223 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem)
224 printxmmwordmem(MI, 2, OS);
225 else
226 printOperand(MI, 2, OS);
227
228 OS << ", ";
229 printOperand(MI, 1, OS);
230 OS << ", ";
231 printOperand(MI, 0, OS);
232 return true;
233 }
234 break;
235
236 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri:
237 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri:
238 case X86::VPCMPBZrmi: case X86::VPCMPBZrri:
239 case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri:
240 case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri:
241 case X86::VPCMPDZrmi: case X86::VPCMPDZrri:
242 case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri:
243 case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri:
244 case X86::VPCMPQZrmi: case X86::VPCMPQZrri:
245 case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri:
246 case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri:
247 case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri:
248 case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri:
249 case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri:
250 case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri:
251 case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri:
252 case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri:
253 case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri:
254 case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri:
255 case X86::VPCMPUWZ256rmi: case X86::VPCMPUWZ256rri:
256 case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri:
257 case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri:
258 case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri:
259 case X86::VPCMPWZrmi: case X86::VPCMPWZrri:
260 case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik:
261 case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik:
262 case X86::VPCMPBZrmik: case X86::VPCMPBZrrik:
263 case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik:
264 case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik:
265 case X86::VPCMPDZrmik: case X86::VPCMPDZrrik:
266 case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik:
267 case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik:
268 case X86::VPCMPQZrmik: case X86::VPCMPQZrrik:
269 case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
270 case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
271 case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik:
272 case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
273 case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
274 case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik:
275 case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
276 case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
277 case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik:
278 case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
279 case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik:
280 case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik:
281 case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik:
282 case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik:
283 case X86::VPCMPWZrmik: case X86::VPCMPWZrrik:
284 case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk:
285 case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk:
286 case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk:
287 case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk:
288 case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk:
289 case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk:
290 case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk:
291 case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk:
292 case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk:
293 case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk:
294 case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk:
295 case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk:
296 if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) {
297 OS << '\t';
298 printVPCMPMnemonic(MI, OS);
299
300 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2;
301
302 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
303 if (Desc.TSFlags & X86II::EVEX_B) {
304 // Broadcast form.
305 // Load size is based on W-bit as only D and Q are supported.
306 if (Desc.TSFlags & X86II::VEX_W)
307 printqwordmem(MI, CurOp--, OS);
308 else
309 printdwordmem(MI, CurOp--, OS);
310
311 // Print the number of elements broadcasted.
312 unsigned NumElts;
313 if (Desc.TSFlags & X86II::EVEX_L2)
314 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
315 else if (Desc.TSFlags & X86II::VEX_L)
316 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
317 else
318 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
319 OS << "{1to" << NumElts << "}";
320 } else {
321 if (Desc.TSFlags & X86II::EVEX_L2)
322 printzmmwordmem(MI, CurOp--, OS);
323 else if (Desc.TSFlags & X86II::VEX_L)
324 printymmwordmem(MI, CurOp--, OS);
325 else
326 printxmmwordmem(MI, CurOp--, OS);
327 }
328 } else {
329 printOperand(MI, CurOp--, OS);
330 }
331
332 OS << ", ";
333 printOperand(MI, CurOp--, OS);
334 OS << ", ";
335 printOperand(MI, 0, OS);
336 if (CurOp > 0) {
337 // Print mask operand.
338 OS << " {";
339 printOperand(MI, CurOp--, OS);
340 OS << "}";
341 }
342
343 return true;
344 }
345 break;
346 }
347
348 return false;
349 }
350
351 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
352 raw_ostream &O) {
353 const MCOperand &Op = MI->getOperand(OpNo);
354 if (Op.isReg()) {
355 printRegName(O, Op.getReg());
356 } else if (Op.isImm()) {
357 // Print immediates as signed values.
358 int64_t Imm = Op.getImm();
359 O << markup("");
360
361 // TODO: This should be in a helper function in the base class, so it can
362 // be used by other printers.
363
364 // If there are no instruction-specific comments, add a comment clarifying
365 // the hex value of the immediate operand when it isn't in the range
366 // [-256,255].
367 if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) {
368 // Don't print unnecessary hex sign bits.
369 if (Imm == (int16_t)(Imm))
370 *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm);
371 else if (Imm == (int32_t)(Imm))
372 *CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm);
373 else
374 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm);
375 }
376 } else {
377 assert(Op.isExpr() && "unknown operand kind in printOperand");
378 O << markup("
379 Op.getExpr()->print(O, &MAI);
380 O << markup(">");
381 }
382 }
383
384 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
385 raw_ostream &O) {
386 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
387 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
388 const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
389
390 O << markup("
391
392 // If this has a segment register, print it.
393 printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
394
395 if (DispSpec.isImm()) {
396 int64_t DispVal = DispSpec.getImm();
397 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
398 O << formatImm(DispVal);
399 } else {
400 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
401 DispSpec.getExpr()->print(O, &MAI);
402 }
403
404 if (IndexReg.getReg() || BaseReg.getReg()) {
405 O << '(';
406 if (BaseReg.getReg())
407 printOperand(MI, Op + X86::AddrBaseReg, O);
408
409 if (IndexReg.getReg()) {
410 O << ',';
411 printOperand(MI, Op + X86::AddrIndexReg, O);
412 unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
413 if (ScaleVal != 1) {
414 O << ',' << markup("
415 << markup(">");
416 }
417 }
418 O << ')';
419 }
420
421 O << markup(">");
422 }
423
424 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
425 raw_ostream &O) {
426 O << markup("
427
428 // If this has a segment register, print it.
429 printOptionalSegReg(MI, Op + 1, O);
430
431 O << "(";
432 printOperand(MI, Op, O);
433 O << ")";
434
435 O << markup(">");
436 }
437
438 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
439 raw_ostream &O) {
440 O << markup("
441
442 O << "%es:(";
443 printOperand(MI, Op, O);
444 O << ")";
445
446 O << markup(">");
447 }
448
449 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
450 raw_ostream &O) {
451 const MCOperand &DispSpec = MI->getOperand(Op);
452
453 O << markup("
454
455 // If this has a segment register, print it.
456 printOptionalSegReg(MI, Op + 1, O);
457
458 if (DispSpec.isImm()) {
459 O << formatImm(DispSpec.getImm());
460 } else {
461 assert(DispSpec.isExpr() && "non-immediate displacement?");
462 DispSpec.getExpr()->print(O, &MAI);
463 }
464
465 O << markup(">");
466 }
467
468 void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
469 raw_ostream &O) {
470 if (MI->getOperand(Op).isExpr())
471 return printOperand(MI, Op, O);
472
473 O << markup("getOperand(Op).getImm() & 0xff)
474 << markup(">");
475 }
476
477 void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
478 raw_ostream &OS) {
479 const MCOperand &Op = MI->getOperand(OpNo);
480 unsigned Reg = Op.getReg();
481 // Override the default printing to print st(0) instead st.
482 if (Reg == X86::ST0)
483 OS << markup("");
484 else
485 printRegName(OS, Reg);
486 }
0 //=- X86ATTInstPrinter.h - Convert X86 MCInst to assembly syntax --*- C++ -*-=//
1 //
2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3 // See https://llvm.org/LICENSE.txt for license information.
4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5 //
6 //===----------------------------------------------------------------------===//
7 //
8 // This class prints an X86 MCInst to AT&T style .s file syntax.
9 //
10 //===----------------------------------------------------------------------===//
11
12 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86ATTINSTPRINTER_H
13 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86ATTINSTPRINTER_H
14
15 #include "X86InstPrinterCommon.h"
16
17 namespace llvm {
18
19 class X86ATTInstPrinter final : public X86InstPrinterCommon {
20 public:
21 X86ATTInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
22 const MCRegisterInfo &MRI)
23 : X86InstPrinterCommon(MAI, MII, MRI), HasCustomInstComment(false) {}
24
25 void printRegName(raw_ostream &OS, unsigned RegNo) const override;
26 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
27 const MCSubtargetInfo &STI) override;
28 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
29
30 // Autogenerated by tblgen, returns true if we successfully printed an
31 // alias.
32 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
33 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
34 unsigned PrintMethodIdx, raw_ostream &O);
35
36 // Autogenerated by tblgen.
37 void printInstruction(const MCInst *MI, raw_ostream &OS);
38 static const char *getRegisterName(unsigned RegNo);
39
40 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
41 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
42 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
43 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
44 void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
45 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS);
46 void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
47
48 void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
49 printMemReference(MI, OpNo, O);
50 }
51 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
52 printMemReference(MI, OpNo, O);
53 }
54
55 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
56 printMemReference(MI, OpNo, O);
57 }
58 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
59 printMemReference(MI, OpNo, O);
60 }
61 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
62 printMemReference(MI, OpNo, O);
63 }
64 void printqwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
65 printMemReference(MI, OpNo, O);
66 }
67 void printxmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
68 printMemReference(MI, OpNo, O);
69 }
70 void printymmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
71 printMemReference(MI, OpNo, O);
72 }
73 void printzmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
74 printMemReference(MI, OpNo, O);
75 }
76 void printtbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
77 printMemReference(MI, OpNo, O);
78 }
79
80 void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
81 printSrcIdx(MI, OpNo, O);
82 }
83 void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
84 printSrcIdx(MI, OpNo, O);
85 }
86 void printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
87 printSrcIdx(MI, OpNo, O);
88 }
89 void printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
90 printSrcIdx(MI, OpNo, O);
91 }
92 void printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
93 printDstIdx(MI, OpNo, O);
94 }
95 void printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
96 printDstIdx(MI, OpNo, O);
97 }
98 void printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
99 printDstIdx(MI, OpNo, O);
100 }
101 void printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
102 printDstIdx(MI, OpNo, O);
103 }
104 void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
105 printMemOffset(MI, OpNo, O);
106 }
107 void printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
108 printMemOffset(MI, OpNo, O);
109 }
110 void printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
111 printMemOffset(MI, OpNo, O);
112 }
113 void printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
114 printMemOffset(MI, OpNo, O);
115 }
116
117 private:
118 bool HasCustomInstComment;
119 };
120
121 } // end namespace llvm
122
123 #endif // LLVM_LIB_TARGET_X86_MCTARGETDESC_X86ATTINSTPRINTER_H
0 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//