llvm.org GIT mirror llvm / e837dea
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
78 changed file(s) with 1357 addition(s) and 1329 deletion(s). Raw diff Collapse all Expand all
344344 /// CreateMachineInstr - Allocate a new MachineInstr. Use this instead
345345 /// of `new MachineInstr'.
346346 ///
347 MachineInstr *CreateMachineInstr(const TargetInstrDesc &TID,
347 MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID,
348348 DebugLoc DL,
349349 bool NoImp = false);
350350
1616 #define LLVM_CODEGEN_MACHINEINSTR_H
1717
1818 #include "llvm/CodeGen/MachineOperand.h"
19 #include "llvm/Target/TargetInstrDesc.h"
19 #include "llvm/MC/MCInstrDesc.h"
2020 #include "llvm/Target/TargetOpcodes.h"
2121 #include "llvm/ADT/ilist.h"
2222 #include "llvm/ADT/ilist_node.h"
2929
3030 template class SmallVectorImpl;
3131 class AliasAnalysis;
32 class TargetInstrDesc;
3332 class TargetInstrInfo;
3433 class TargetRegisterInfo;
3534 class MachineFunction;
5655 // function frame setup code.
5756 };
5857 private:
59 const TargetInstrDesc *TID; // Instruction descriptor.
58 const MCInstrDesc *MCID; // Instruction descriptor.
6059 uint16_t NumImplicitOps; // Number of implicit operands (which
6160 // are determined at construction time).
6261
9392 MachineInstr(MachineFunction &, const MachineInstr &);
9493
9594 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
96 /// TID NULL and no operands.
95 /// MCID NULL and no operands.
9796 MachineInstr();
9897
9998 // The next two constructors have DebugLoc and non-DebugLoc versions;
102101
103102 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
104103 /// implicit operands. It reserves space for the number of operands specified
105 /// by the TargetInstrDesc. The version with a DebugLoc should be preferred.
106 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
104 /// by the MCInstrDesc. The version with a DebugLoc should be preferred.
105 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
107106
108107 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
109108 /// the MachineInstr is created and added to the end of the specified basic
110109 /// block. The version with a DebugLoc should be preferred.
111 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
110 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
112111
113112 /// MachineInstr ctor - This constructor create a MachineInstr and add the
114113 /// implicit operands. It reserves space for number of operands specified by
115 /// TargetInstrDesc. An explicit DebugLoc is supplied.
116 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
114 /// MCInstrDesc. An explicit DebugLoc is supplied.
115 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
117116 bool NoImp = false);
118117
119118 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
120119 /// the MachineInstr is created and added to the end of the specified basic
121120 /// block.
122121 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
123 const TargetInstrDesc &TID);
122 const MCInstrDesc &MCID);
124123
125124 ~MachineInstr();
126125
182181
183182 /// getDesc - Returns the target instruction descriptor of this
184183 /// MachineInstr.
185 const TargetInstrDesc &getDesc() const { return *TID; }
184 const MCInstrDesc &getDesc() const { return *MCID; }
186185
187186 /// getOpcode - Returns the opcode of this MachineInstr.
188187 ///
189 int getOpcode() const { return TID->Opcode; }
188 int getOpcode() const { return MCID->Opcode; }
190189
191190 /// Access to explicit operands of the instruction.
192191 ///
463462
464463 /// hasUnmodeledSideEffects - Return true if this instruction has side
465464 /// effects that are not modeled by mayLoad / mayStore, etc.
466 /// For all instructions, the property is encoded in TargetInstrDesc::Flags
467 /// (see TargetInstrDesc::hasUnmodeledSideEffects(). The only exception is
465 /// For all instructions, the property is encoded in MCInstrDesc::Flags
466 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
468467 /// INLINEASM instruction, in which case the side effect property is encoded
469468 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
470469 ///
496495 /// setDesc - Replace the instruction descriptor (thus opcode) of
497496 /// the current instruction with a new one.
498497 ///
499 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
498 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
500499
501500 /// setDebugLoc - Replace current source information with new such.
502501 /// Avoid using this, the constructor argument is preferable.
2121
2222 namespace llvm {
2323
24 class TargetInstrDesc;
24 class MCInstrDesc;
2525 class MDNode;
2626
2727 namespace RegState {
179179 ///
180180 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
181181 DebugLoc DL,
182 const TargetInstrDesc &TID) {
183 return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL));
182 const MCInstrDesc &MCID) {
183 return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL));
184184 }
185185
186186 /// BuildMI - This version of the builder sets up the first operand as a
188188 ///
189189 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
190190 DebugLoc DL,
191 const TargetInstrDesc &TID,
191 const MCInstrDesc &MCID,
192192 unsigned DestReg) {
193 return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL))
193 return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL))
194194 .addReg(DestReg, RegState::Define);
195195 }
196196
201201 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
202202 MachineBasicBlock::iterator I,
203203 DebugLoc DL,
204 const TargetInstrDesc &TID,
204 const MCInstrDesc &MCID,
205205 unsigned DestReg) {
206 MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL);
206 MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);
207207 BB.insert(I, MI);
208208 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
209209 }
215215 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
216216 MachineBasicBlock::iterator I,
217217 DebugLoc DL,
218 const TargetInstrDesc &TID) {
219 MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL);
218 const MCInstrDesc &MCID) {
219 MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);
220220 BB.insert(I, MI);
221221 return MachineInstrBuilder(MI);
222222 }
227227 ///
228228 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
229229 DebugLoc DL,
230 const TargetInstrDesc &TID) {
231 return BuildMI(*BB, BB->end(), DL, TID);
230 const MCInstrDesc &MCID) {
231 return BuildMI(*BB, BB->end(), DL, MCID);
232232 }
233233
234234 /// BuildMI - This version of the builder inserts the newly-built
237237 ///
238238 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
239239 DebugLoc DL,
240 const TargetInstrDesc &TID,
240 const MCInstrDesc &MCID,
241241 unsigned DestReg) {
242 return BuildMI(*BB, BB->end(), DL, TID, DestReg);
242 return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
243243 }
244244
245245 inline unsigned getDefRegState(bool B) {
3333 class ScheduleDAG;
3434 class SDNode;
3535 class TargetInstrInfo;
36 class TargetInstrDesc;
36 class MCInstrDesc;
3737 class TargetMachine;
3838 class TargetRegisterClass;
3939 template class GraphWriter;
506506
507507 virtual ~ScheduleDAG();
508508
509 /// getInstrDesc - Return the TargetInstrDesc of this SUnit.
509 /// getInstrDesc - Return the MCInstrDesc of this SUnit.
510510 /// Return NULL for SDNodes without a machine opcode.
511 const TargetInstrDesc *getInstrDesc(const SUnit *SU) const {
511 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
512512 if (SU->isInstr()) return &SU->getInstr()->getDesc();
513513 return getNodeDesc(SU->getNode());
514514 }
578578 void EmitPhysRegCopy(SUnit *SU, DenseMap &VRBaseMap);
579579
580580 private:
581 // Return the TargetInstrDesc of this SDNode or NULL.
582 const TargetInstrDesc *getNodeDesc(const SDNode *Node) const;
581 // Return the MCInstrDesc of this SDNode or NULL.
582 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
583583 };
584584
585585 class SUnitIterator : public std::iterator
2424 namespace llvm {
2525
2626 class InstrItineraryData;
27 class TargetInstrDesc;
2827 class ScheduleDAG;
2928 class SUnit;
3029
0 //===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the McOperandInfo and McInstrDesc classes, which
10 // are used to describe target instructions and their operands.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_MC_MCINSTRDESC_H
15 #define LLVM_MC_MCINSTRDESC_H
16
17 #include "llvm/Support/DataTypes.h"
18
19 namespace llvm {
20
21 //===----------------------------------------------------------------------===//
22 // Machine Operand Flags and Description
23 //===----------------------------------------------------------------------===//
24
25 namespace MCOI {
26 // Operand constraints
27 enum OperandConstraint {
28 TIED_TO = 0, // Must be allocated the same register as.
29 EARLY_CLOBBER // Operand is an early clobber register operand
30 };
31
32 /// OperandFlags - These are flags set on operands, but should be considered
33 /// private, all access should go through the MCOperandInfo accessors.
34 /// See the accessors for a description of what these are.
35 enum OperandFlags {
36 LookupPtrRegClass = 0,
37 Predicate,
38 OptionalDef
39 };
40 }
41
42 /// MCOperandInfo - This holds information about one operand of a machine
43 /// instruction, indicating the register class for register operands, etc.
44 ///
45 class MCOperandInfo {
46 public:
47 /// RegClass - This specifies the register class enumeration of the operand
48 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
49 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
50 /// get a dynamic register class.
51 short RegClass;
52
53 /// Flags - These are flags from the MCOI::OperandFlags enum.
54 unsigned short Flags;
55
56 /// Lower 16 bits are used to specify which constraints are set. The higher 16
57 /// bits are used to specify the value of constraints (4 bits each).
58 unsigned Constraints;
59 /// Currently no other information.
60
61 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
62 /// requires a callback to look up its register class.
63 bool isLookupPtrRegClass() const { return Flags&(1 <
64
65 /// isPredicate - Set if this is one of the operands that made up of
66 /// the predicate operand that controls an isPredicable() instruction.
67 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
68
69 /// isOptionalDef - Set if this operand is a optional def.
70 ///
71 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
72 };
73
74
75 //===----------------------------------------------------------------------===//
76 // Machine Instruction Flags and Description
77 //===----------------------------------------------------------------------===//
78
79 /// MCInstrDesc flags - These should be considered private to the
80 /// implementation of the MCInstrDesc class. Clients should use the predicate
81 /// methods on MCInstrDesc, not use these directly. These all correspond to
82 /// bitfields in the MCInstrDesc::Flags field.
83 namespace MCID {
84 enum {
85 Variadic = 0,
86 HasOptionalDef,
87 Return,
88 Call,
89 Barrier,
90 Terminator,
91 Branch,
92 IndirectBranch,
93 Compare,
94 MoveImm,
95 Bitcast,
96 DelaySlot,
97 FoldableAsLoad,
98 MayLoad,
99 MayStore,
100 Predicable,
101 NotDuplicable,
102 UnmodeledSideEffects,
103 Commutable,
104 ConvertibleTo3Addr,
105 UsesCustomInserter,
106 Rematerializable,
107 CheapAsAMove,
108 ExtraSrcRegAllocReq,
109 ExtraDefRegAllocReq
110 };
111 }
112
113 /// MCInstrDesc - Describe properties that are true of each instruction in the
114 /// target description file. This captures information about side effects,
115 /// register use and many other things. There is one instance of this struct
116 /// for each target instruction class, and the MachineInstr class points to
117 /// this struct directly to describe itself.
118 class MCInstrDesc {
119 public:
120 unsigned short Opcode; // The opcode number
121 unsigned short NumOperands; // Num of args (may be more if variable_ops)
122 unsigned short NumDefs; // Num of args that are definitions
123 unsigned short SchedClass; // enum identifying instr sched class
124 const char * Name; // Name of the instruction record in td file
125 unsigned Flags; // Flags identifying machine instr class
126 uint64_t TSFlags; // Target Specific Flag values
127 const unsigned *ImplicitUses; // Registers implicitly read by this instr
128 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
129 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
130
131 /// getOperandConstraint - Returns the value of the specific constraint if
132 /// it is set. Returns -1 if it is not set.
133 int getOperandConstraint(unsigned OpNum,
134 MCOI::OperandConstraint Constraint) const {
135 if (OpNum < NumOperands &&
136 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
137 unsigned Pos = 16 + Constraint * 4;
138 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
139 }
140 return -1;
141 }
142
143 /// getOpcode - Return the opcode number for this descriptor.
144 unsigned getOpcode() const {
145 return Opcode;
146 }
147
148 /// getName - Return the name of the record in the .td file for this
149 /// instruction, for example "ADD8ri".
150 const char *getName() const {
151 return Name;
152 }
153
154 /// getNumOperands - Return the number of declared MachineOperands for this
155 /// MachineInstruction. Note that variadic (isVariadic() returns true)
156 /// instructions may have additional operands at the end of the list, and note
157 /// that the machine instruction may include implicit register def/uses as
158 /// well.
159 unsigned getNumOperands() const {
160 return NumOperands;
161 }
162
163 /// getNumDefs - Return the number of MachineOperands that are register
164 /// definitions. Register definitions always occur at the start of the
165 /// machine operand list. This is the number of "outs" in the .td file,
166 /// and does not include implicit defs.
167 unsigned getNumDefs() const {
168 return NumDefs;
169 }
170
171 /// isVariadic - Return true if this instruction can have a variable number of
172 /// operands. In this case, the variable operands will be after the normal
173 /// operands but before the implicit definitions and uses (if any are
174 /// present).
175 bool isVariadic() const {
176 return Flags & (1 << MCID::Variadic);
177 }
178
179 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
180 /// ARM instructions which can set condition code if 's' bit is set.
181 bool hasOptionalDef() const {
182 return Flags & (1 << MCID::HasOptionalDef);
183 }
184
185 /// getImplicitUses - Return a list of registers that are potentially
186 /// read by any instance of this machine instruction. For example, on X86,
187 /// the "adc" instruction adds two register operands and adds the carry bit in
188 /// from the flags register. In this case, the instruction is marked as
189 /// implicitly reading the flags. Likewise, the variable shift instruction on
190 /// X86 is marked as implicitly reading the 'CL' register, which it always
191 /// does.
192 ///
193 /// This method returns null if the instruction has no implicit uses.
194 const unsigned *getImplicitUses() const {
195 return ImplicitUses;
196 }
197
198 /// getNumImplicitUses - Return the number of implicit uses this instruction
199 /// has.
200 unsigned getNumImplicitUses() const {
201 if (ImplicitUses == 0) return 0;
202 unsigned i = 0;
203 for (; ImplicitUses[i]; ++i) /*empty*/;
204 return i;
205 }
206
207 /// getImplicitDefs - Return a list of registers that are potentially
208 /// written by any instance of this machine instruction. For example, on X86,
209 /// many instructions implicitly set the flags register. In this case, they
210 /// are marked as setting the FLAGS. Likewise, many instructions always
211 /// deposit their result in a physical register. For example, the X86 divide
212 /// instruction always deposits the quotient and remainder in the EAX/EDX
213 /// registers. For that instruction, this will return a list containing the
214 /// EAX/EDX/EFLAGS registers.
215 ///
216 /// This method returns null if the instruction has no implicit defs.
217 const unsigned *getImplicitDefs() const {
218 return ImplicitDefs;
219 }
220
221 /// getNumImplicitDefs - Return the number of implicit defs this instruction
222 /// has.
223 unsigned getNumImplicitDefs() const {
224 if (ImplicitDefs == 0) return 0;
225 unsigned i = 0;
226 for (; ImplicitDefs[i]; ++i) /*empty*/;
227 return i;
228 }
229
230 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
231 /// uses the specified physical register.
232 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
233 if (const unsigned *ImpUses = ImplicitUses)
234 for (; *ImpUses; ++ImpUses)
235 if (*ImpUses == Reg) return true;
236 return false;
237 }
238
239 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
240 /// defines the specified physical register.
241 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
242 if (const unsigned *ImpDefs = ImplicitDefs)
243 for (; *ImpDefs; ++ImpDefs)
244 if (*ImpDefs == Reg) return true;
245 return false;
246 }
247
248 /// getSchedClass - Return the scheduling class for this instruction. The
249 /// scheduling class is an index into the InstrItineraryData table. This
250 /// returns zero if there is no known scheduling information for the
251 /// instruction.
252 ///
253 unsigned getSchedClass() const {
254 return SchedClass;
255 }
256
257 bool isReturn() const {
258 return Flags & (1 << MCID::Return);
259 }
260
261 bool isCall() const {
262 return Flags & (1 << MCID::Call);
263 }
264
265 /// isBarrier - Returns true if the specified instruction stops control flow
266 /// from executing the instruction immediately following it. Examples include
267 /// unconditional branches and return instructions.
268 bool isBarrier() const {
269 return Flags & (1 << MCID::Barrier);
270 }
271
272 /// isTerminator - Returns true if this instruction part of the terminator for
273 /// a basic block. Typically this is things like return and branch
274 /// instructions.
275 ///
276 /// Various passes use this to insert code into the bottom of a basic block,
277 /// but before control flow occurs.
278 bool isTerminator() const {
279 return Flags & (1 << MCID::Terminator);
280 }
281
282 /// isBranch - Returns true if this is a conditional, unconditional, or
283 /// indirect branch. Predicates below can be used to discriminate between
284 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
285 /// get more information.
286 bool isBranch() const {
287 return Flags & (1 << MCID::Branch);
288 }
289
290 /// isIndirectBranch - Return true if this is an indirect branch, such as a
291 /// branch through a register.
292 bool isIndirectBranch() const {
293 return Flags & (1 << MCID::IndirectBranch);
294 }
295
296 /// isConditionalBranch - Return true if this is a branch which may fall
297 /// through to the next instruction or may transfer control flow to some other
298 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
299 /// information about this branch.
300 bool isConditionalBranch() const {
301 return isBranch() & !isBarrier() & !isIndirectBranch();
302 }
303
304 /// isUnconditionalBranch - Return true if this is a branch which always
305 /// transfers control flow to some other block. The
306 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
307 /// about this branch.
308 bool isUnconditionalBranch() const {
309 return isBranch() & isBarrier() & !isIndirectBranch();
310 }
311
312 // isPredicable - Return true if this instruction has a predicate operand that
313 // controls execution. It may be set to 'always', or may be set to other
314 /// values. There are various methods in TargetInstrInfo that can be used to
315 /// control and modify the predicate in this instruction.
316 bool isPredicable() const {
317 return Flags & (1 << MCID::Predicable);
318 }
319
320 /// isCompare - Return true if this instruction is a comparison.
321 bool isCompare() const {
322 return Flags & (1 << MCID::Compare);
323 }
324
325 /// isMoveImmediate - Return true if this instruction is a move immediate
326 /// (including conditional moves) instruction.
327 bool isMoveImmediate() const {
328 return Flags & (1 << MCID::MoveImm);
329 }
330
331 /// isBitcast - Return true if this instruction is a bitcast instruction.
332 ///
333 bool isBitcast() const {
334 return Flags & (1 << MCID::Bitcast);
335 }
336
337 /// isNotDuplicable - Return true if this instruction cannot be safely
338 /// duplicated. For example, if the instruction has a unique labels attached
339 /// to it, duplicating it would cause multiple definition errors.
340 bool isNotDuplicable() const {
341 return Flags & (1 << MCID::NotDuplicable);
342 }
343
344 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
345 /// which must be filled by the code generator.
346 bool hasDelaySlot() const {
347 return Flags & (1 << MCID::DelaySlot);
348 }
349
350 /// canFoldAsLoad - Return true for instructions that can be folded as
351 /// memory operands in other instructions. The most common use for this
352 /// is instructions that are simple loads from memory that don't modify
353 /// the loaded value in any way, but it can also be used for instructions
354 /// that can be expressed as constant-pool loads, such as V_SETALLONES
355 /// on x86, to allow them to be folded when it is beneficial.
356 /// This should only be set on instructions that return a value in their
357 /// only virtual register definition.
358 bool canFoldAsLoad() const {
359 return Flags & (1 << MCID::FoldableAsLoad);
360 }
361
362 //===--------------------------------------------------------------------===//
363 // Side Effect Analysis
364 //===--------------------------------------------------------------------===//
365
366 /// mayLoad - Return true if this instruction could possibly read memory.
367 /// Instructions with this flag set are not necessarily simple load
368 /// instructions, they may load a value and modify it, for example.
369 bool mayLoad() const {
370 return Flags & (1 << MCID::MayLoad);
371 }
372
373
374 /// mayStore - Return true if this instruction could possibly modify memory.
375 /// Instructions with this flag set are not necessarily simple store
376 /// instructions, they may store a modified value based on their operands, or
377 /// may not actually modify anything, for example.
378 bool mayStore() const {
379 return Flags & (1 << MCID::MayStore);
380 }
381
382 /// hasUnmodeledSideEffects - Return true if this instruction has side
383 /// effects that are not modeled by other flags. This does not return true
384 /// for instructions whose effects are captured by:
385 ///
386 /// 1. Their operand list and implicit definition/use list. Register use/def
387 /// info is explicit for instructions.
388 /// 2. Memory accesses. Use mayLoad/mayStore.
389 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
390 ///
391 /// Examples of side effects would be modifying 'invisible' machine state like
392 /// a control register, flushing a cache, modifying a register invisible to
393 /// LLVM, etc.
394 ///
395 bool hasUnmodeledSideEffects() const {
396 return Flags & (1 << MCID::UnmodeledSideEffects);
397 }
398
399 //===--------------------------------------------------------------------===//
400 // Flags that indicate whether an instruction can be modified by a method.
401 //===--------------------------------------------------------------------===//
402
403 /// isCommutable - Return true if this may be a 2- or 3-address
404 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
405 /// result if Y and Z are exchanged. If this flag is set, then the
406 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
407 /// instruction.
408 ///
409 /// Note that this flag may be set on instructions that are only commutable
410 /// sometimes. In these cases, the call to commuteInstruction will fail.
411 /// Also note that some instructions require non-trivial modification to
412 /// commute them.
413 bool isCommutable() const {
414 return Flags & (1 << MCID::Commutable);
415 }
416
417 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
418 /// which can be changed into a 3-address instruction if needed. Doing this
419 /// transformation can be profitable in the register allocator, because it
420 /// means that the instruction can use a 2-address form if possible, but
421 /// degrade into a less efficient form if the source and dest register cannot
422 /// be assigned to the same register. For example, this allows the x86
423 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
424 /// is the same speed as the shift but has bigger code size.
425 ///
426 /// If this returns true, then the target must implement the
427 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
428 /// is allowed to fail if the transformation isn't valid for this specific
429 /// instruction (e.g. shl reg, 4 on x86).
430 ///
431 bool isConvertibleTo3Addr() const {
432 return Flags & (1 << MCID::ConvertibleTo3Addr);
433 }
434
435 /// usesCustomInsertionHook - Return true if this instruction requires
436 /// custom insertion support when the DAG scheduler is inserting it into a
437 /// machine basic block. If this is true for the instruction, it basically
438 /// means that it is a pseudo instruction used at SelectionDAG time that is
439 /// expanded out into magic code by the target when MachineInstrs are formed.
440 ///
441 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
442 /// is used to insert this into the MachineBasicBlock.
443 bool usesCustomInsertionHook() const {
444 return Flags & (1 << MCID::UsesCustomInserter);
445 }
446
447 /// isRematerializable - Returns true if this instruction is a candidate for
448 /// remat. This flag is deprecated, please don't use it anymore. If this
449 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
450 /// verify the instruction is really rematable.
451 bool isRematerializable() const {
452 return Flags & (1 << MCID::Rematerializable);
453 }
454
455 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
456 /// less) than a move instruction. This is useful during certain types of
457 /// optimizations (e.g., remat during two-address conversion or machine licm)
458 /// where we would like to remat or hoist the instruction, but not if it costs
459 /// more than moving the instruction into the appropriate register. Note, we
460 /// are not marking copies from and to the same register class with this flag.
461 bool isAsCheapAsAMove() const {
462 return Flags & (1 << MCID::CheapAsAMove);
463 }
464
465 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
466 /// have special register allocation requirements that are not captured by the
467 /// operand register classes. e.g. ARM::STRD's two source registers must be an
468 /// even / odd pair, ARM::STM registers have to be in ascending order.
469 /// Post-register allocation passes should not attempt to change allocations
470 /// for sources of instructions with this flag.
471 bool hasExtraSrcRegAllocReq() const {
472 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
473 }
474
475 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
476 /// have special register allocation requirements that are not captured by the
477 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
478 /// even / odd pair, ARM::LDM registers have to be in ascending order.
479 /// Post-register allocation passes should not attempt to change allocations
480 /// for definitions of instructions with this flag.
481 bool hasExtraDefRegAllocReq() const {
482 return Flags & (1 << MCID::ExtraDefRegAllocReq);
483 }
484 };
485
486 } // end namespace llvm
487
488 #endif
0 //===-- llvm/MC/MCInstrInfo.h - Target Instruction Info ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_MC_MCINSTRINFO_H
14 #define LLVM_MC_MCINSTRINFO_H
15
16 #include "llvm/MC/MCInstrDesc.h"
17 #include
18
19 namespace llvm {
20
21 //---------------------------------------------------------------------------
22 ///
23 /// MCInstrInfo - Interface to description of machine instruction set
24 ///
25 class MCInstrInfo {
26 const MCInstrDesc *Desc; // Raw array to allow static init'n
27 unsigned NumOpcodes; // Number of entries in the desc array
28
29 public:
30 /// InitMCInstrInfo - Initialize MCInstrInfo, called by TableGen
31 /// auto-generated routines. *DO NOT USE*.
32 void InitMCInstrInfo(const MCInstrDesc *D, unsigned NO) {
33 Desc = D;
34 NumOpcodes = NO;
35 }
36
37 unsigned getNumOpcodes() const { return NumOpcodes; }
38
39 /// get - Return the machine instruction descriptor that corresponds to the
40 /// specified instruction opcode.
41 ///
42 const MCInstrDesc &get(unsigned Opcode) const {
43 assert(Opcode < NumOpcodes && "Invalid opcode!");
44 return Desc[Opcode];
45 }
46 };
47
48 } // End llvm namespace
49
50 #endif
5151 class MCRegisterInfo {
5252 private:
5353 const MCRegisterDesc *Desc; // Pointer to the descriptor array
54 unsigned NumRegs; // Number of entries in the array
54 unsigned NumRegs; // Number of entries in the array
5555
5656 public:
5757 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
+0
-493
include/llvm/Target/TargetInstrDesc.h less more
None //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
10 // are used to describe target instructions and their operands.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
15 #define LLVM_TARGET_TARGETINSTRDESC_H
16
17 #include "llvm/Support/DataTypes.h"
18
19 namespace llvm {
20
21 class TargetRegisterClass;
22 class TargetRegisterInfo;
23
24 //===----------------------------------------------------------------------===//
25 // Machine Operand Flags and Description
26 //===----------------------------------------------------------------------===//
27
28 namespace TOI {
29 // Operand constraints
30 enum OperandConstraint {
31 TIED_TO = 0, // Must be allocated the same register as.
32 EARLY_CLOBBER // Operand is an early clobber register operand
33 };
34
35 /// OperandFlags - These are flags set on operands, but should be considered
36 /// private, all access should go through the TargetOperandInfo accessors.
37 /// See the accessors for a description of what these are.
38 enum OperandFlags {
39 LookupPtrRegClass = 0,
40 Predicate,
41 OptionalDef
42 };
43 }
44
45 /// TargetOperandInfo - This holds information about one operand of a machine
46 /// instruction, indicating the register class for register operands, etc.
47 ///
48 class TargetOperandInfo {
49 public:
50 /// RegClass - This specifies the register class enumeration of the operand
51 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
52 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
53 /// get a dynamic register class.
54 short RegClass;
55
56 /// Flags - These are flags from the TOI::OperandFlags enum.
57 unsigned short Flags;
58
59 /// Lower 16 bits are used to specify which constraints are set. The higher 16
60 /// bits are used to specify the value of constraints (4 bits each).
61 unsigned Constraints;
62 /// Currently no other information.
63
64 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
65 /// requires a callback to look up its register class.
66 bool isLookupPtrRegClass() const { return Flags&(1 <
67
68 /// isPredicate - Set if this is one of the operands that made up of
69 /// the predicate operand that controls an isPredicable() instruction.
70 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
71
72 /// isOptionalDef - Set if this operand is a optional def.
73 ///
74 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
75 };
76
77
78 //===----------------------------------------------------------------------===//
79 // Machine Instruction Flags and Description
80 //===----------------------------------------------------------------------===//
81
82 /// TargetInstrDesc flags - These should be considered private to the
83 /// implementation of the TargetInstrDesc class. Clients should use the
84 /// predicate methods on TargetInstrDesc, not use these directly. These
85 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
86 namespace TID {
87 enum {
88 Variadic = 0,
89 HasOptionalDef,
90 Return,
91 Call,
92 Barrier,
93 Terminator,
94 Branch,
95 IndirectBranch,
96 Compare,
97 MoveImm,
98 Bitcast,
99 DelaySlot,
100 FoldableAsLoad,
101 MayLoad,
102 MayStore,
103 Predicable,
104 NotDuplicable,
105 UnmodeledSideEffects,
106 Commutable,
107 ConvertibleTo3Addr,
108 UsesCustomInserter,
109 Rematerializable,
110 CheapAsAMove,
111 ExtraSrcRegAllocReq,
112 ExtraDefRegAllocReq
113 };
114 }
115
116 /// TargetInstrDesc - Describe properties that are true of each
117 /// instruction in the target description file. This captures information about
118 /// side effects, register use and many other things. There is one instance of
119 /// this struct for each target instruction class, and the MachineInstr class
120 /// points to this struct directly to describe itself.
121 class TargetInstrDesc {
122 public:
123 unsigned short Opcode; // The opcode number
124 unsigned short NumOperands; // Num of args (may be more if variable_ops)
125 unsigned short NumDefs; // Num of args that are definitions
126 unsigned short SchedClass; // enum identifying instr sched class
127 const char * Name; // Name of the instruction record in td file
128 unsigned Flags; // Flags identifying machine instr class
129 uint64_t TSFlags; // Target Specific Flag values
130 const unsigned *ImplicitUses; // Registers implicitly read by this instr
131 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
132 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands
133
134 /// getOperandConstraint - Returns the value of the specific constraint if
135 /// it is set. Returns -1 if it is not set.
136 int getOperandConstraint(unsigned OpNum,
137 TOI::OperandConstraint Constraint) const {
138 if (OpNum < NumOperands &&
139 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
140 unsigned Pos = 16 + Constraint * 4;
141 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
142 }
143 return -1;
144 }
145
146 /// getOpcode - Return the opcode number for this descriptor.
147 unsigned getOpcode() const {
148 return Opcode;
149 }
150
151 /// getName - Return the name of the record in the .td file for this
152 /// instruction, for example "ADD8ri".
153 const char *getName() const {
154 return Name;
155 }
156
157 /// getNumOperands - Return the number of declared MachineOperands for this
158 /// MachineInstruction. Note that variadic (isVariadic() returns true)
159 /// instructions may have additional operands at the end of the list, and note
160 /// that the machine instruction may include implicit register def/uses as
161 /// well.
162 unsigned getNumOperands() const {
163 return NumOperands;
164 }
165
166 /// getNumDefs - Return the number of MachineOperands that are register
167 /// definitions. Register definitions always occur at the start of the
168 /// machine operand list. This is the number of "outs" in the .td file,
169 /// and does not include implicit defs.
170 unsigned getNumDefs() const {
171 return NumDefs;
172 }
173
174 /// isVariadic - Return true if this instruction can have a variable number of
175 /// operands. In this case, the variable operands will be after the normal
176 /// operands but before the implicit definitions and uses (if any are
177 /// present).
178 bool isVariadic() const {
179 return Flags & (1 << TID::Variadic);
180 }
181
182 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
183 /// ARM instructions which can set condition code if 's' bit is set.
184 bool hasOptionalDef() const {
185 return Flags & (1 << TID::HasOptionalDef);
186 }
187
188 /// getImplicitUses - Return a list of registers that are potentially
189 /// read by any instance of this machine instruction. For example, on X86,
190 /// the "adc" instruction adds two register operands and adds the carry bit in
191 /// from the flags register. In this case, the instruction is marked as
192 /// implicitly reading the flags. Likewise, the variable shift instruction on
193 /// X86 is marked as implicitly reading the 'CL' register, which it always
194 /// does.
195 ///
196 /// This method returns null if the instruction has no implicit uses.
197 const unsigned *getImplicitUses() const {
198 return ImplicitUses;
199 }
200
201 /// getNumImplicitUses - Return the number of implicit uses this instruction
202 /// has.
203 unsigned getNumImplicitUses() const {
204 if (ImplicitUses == 0) return 0;
205 unsigned i = 0;
206 for (; ImplicitUses[i]; ++i) /*empty*/;
207 return i;
208 }
209
210
211 /// getImplicitDefs - Return a list of registers that are potentially
212 /// written by any instance of this machine instruction. For example, on X86,
213 /// many instructions implicitly set the flags register. In this case, they
214 /// are marked as setting the FLAGS. Likewise, many instructions always
215 /// deposit their result in a physical register. For example, the X86 divide
216 /// instruction always deposits the quotient and remainder in the EAX/EDX
217 /// registers. For that instruction, this will return a list containing the
218 /// EAX/EDX/EFLAGS registers.
219 ///
220 /// This method returns null if the instruction has no implicit defs.
221 const unsigned *getImplicitDefs() const {
222 return ImplicitDefs;
223 }
224
225 /// getNumImplicitDefs - Return the number of implicit defs this instruction
226 /// has.
227 unsigned getNumImplicitDefs() const {
228 if (ImplicitDefs == 0) return 0;
229 unsigned i = 0;
230 for (; ImplicitDefs[i]; ++i) /*empty*/;
231 return i;
232 }
233
234 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
235 /// uses the specified physical register.
236 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
237 if (const unsigned *ImpUses = ImplicitUses)
238 for (; *ImpUses; ++ImpUses)
239 if (*ImpUses == Reg) return true;
240 return false;
241 }
242
243 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
244 /// defines the specified physical register.
245 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
246 if (const unsigned *ImpDefs = ImplicitDefs)
247 for (; *ImpDefs; ++ImpDefs)
248 if (*ImpDefs == Reg) return true;
249 return false;
250 }
251
252 /// getSchedClass - Return the scheduling class for this instruction. The
253 /// scheduling class is an index into the InstrItineraryData table. This
254 /// returns zero if there is no known scheduling information for the
255 /// instruction.
256 ///
257 unsigned getSchedClass() const {
258 return SchedClass;
259 }
260
261 bool isReturn() const {
262 return Flags & (1 << TID::Return);
263 }
264
265 bool isCall() const {
266 return Flags & (1 << TID::Call);
267 }
268
269 /// isBarrier - Returns true if the specified instruction stops control flow
270 /// from executing the instruction immediately following it. Examples include
271 /// unconditional branches and return instructions.
272 bool isBarrier() const {
273 return Flags & (1 << TID::Barrier);
274 }
275
276 /// isTerminator - Returns true if this instruction part of the terminator for
277 /// a basic block. Typically this is things like return and branch
278 /// instructions.
279 ///
280 /// Various passes use this to insert code into the bottom of a basic block,
281 /// but before control flow occurs.
282 bool isTerminator() const {
283 return Flags & (1 << TID::Terminator);
284 }
285
286 /// isBranch - Returns true if this is a conditional, unconditional, or
287 /// indirect branch. Predicates below can be used to discriminate between
288 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
289 /// get more information.
290 bool isBranch() const {
291 return Flags & (1 << TID::Branch);
292 }
293
294 /// isIndirectBranch - Return true if this is an indirect branch, such as a
295 /// branch through a register.
296 bool isIndirectBranch() const {
297 return Flags & (1 << TID::IndirectBranch);
298 }
299
300 /// isConditionalBranch - Return true if this is a branch which may fall
301 /// through to the next instruction or may transfer control flow to some other
302 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
303 /// information about this branch.
304 bool isConditionalBranch() const {
305 return isBranch() & !isBarrier() & !isIndirectBranch();
306 }
307
308 /// isUnconditionalBranch - Return true if this is a branch which always
309 /// transfers control flow to some other block. The
310 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
311 /// about this branch.
312 bool isUnconditionalBranch() const {
313 return isBranch() & isBarrier() & !isIndirectBranch();
314 }
315
316 // isPredicable - Return true if this instruction has a predicate operand that
317 // controls execution. It may be set to 'always', or may be set to other
318 /// values. There are various methods in TargetInstrInfo that can be used to
319 /// control and modify the predicate in this instruction.
320 bool isPredicable() const {
321 return Flags & (1 << TID::Predicable);
322 }
323
324 /// isCompare - Return true if this instruction is a comparison.
325 bool isCompare() const {
326 return Flags & (1 << TID::Compare);
327 }
328
329 /// isMoveImmediate - Return true if this instruction is a move immediate
330 /// (including conditional moves) instruction.
331 bool isMoveImmediate() const {
332 return Flags & (1 << TID::MoveImm);
333 }
334
335 /// isBitcast - Return true if this instruction is a bitcast instruction.
336 ///
337 bool isBitcast() const {
338 return Flags & (1 << TID::Bitcast);
339 }
340
341 /// isNotDuplicable - Return true if this instruction cannot be safely
342 /// duplicated. For example, if the instruction has a unique labels attached
343 /// to it, duplicating it would cause multiple definition errors.
344 bool isNotDuplicable() const {
345 return Flags & (1 << TID::NotDuplicable);
346 }
347
348 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
349 /// which must be filled by the code generator.
350 bool hasDelaySlot() const {
351 return Flags & (1 << TID::DelaySlot);
352 }
353
354 /// canFoldAsLoad - Return true for instructions that can be folded as
355 /// memory operands in other instructions. The most common use for this
356 /// is instructions that are simple loads from memory that don't modify
357 /// the loaded value in any way, but it can also be used for instructions
358 /// that can be expressed as constant-pool loads, such as V_SETALLONES
359 /// on x86, to allow them to be folded when it is beneficial.
360 /// This should only be set on instructions that return a value in their
361 /// only virtual register definition.
362 bool canFoldAsLoad() const {
363 return Flags & (1 << TID::FoldableAsLoad);
364 }
365
366 //===--------------------------------------------------------------------===//
367 // Side Effect Analysis
368 //===--------------------------------------------------------------------===//
369
370 /// mayLoad - Return true if this instruction could possibly read memory.
371 /// Instructions with this flag set are not necessarily simple load
372 /// instructions, they may load a value and modify it, for example.
373 bool mayLoad() const {
374 return Flags & (1 << TID::MayLoad);
375 }
376
377
378 /// mayStore - Return true if this instruction could possibly modify memory.
379 /// Instructions with this flag set are not necessarily simple store
380 /// instructions, they may store a modified value based on their operands, or
381 /// may not actually modify anything, for example.
382 bool mayStore() const {
383 return Flags & (1 << TID::MayStore);
384 }
385
386 /// hasUnmodeledSideEffects - Return true if this instruction has side
387 /// effects that are not modeled by other flags. This does not return true
388 /// for instructions whose effects are captured by:
389 ///
390 /// 1. Their operand list and implicit definition/use list. Register use/def
391 /// info is explicit for instructions.
392 /// 2. Memory accesses. Use mayLoad/mayStore.
393 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
394 ///
395 /// Examples of side effects would be modifying 'invisible' machine state like
396 /// a control register, flushing a cache, modifying a register invisible to
397 /// LLVM, etc.
398 ///
399 bool hasUnmodeledSideEffects() const {
400 return Flags & (1 << TID::UnmodeledSideEffects);
401 }
402
403 //===--------------------------------------------------------------------===//
404 // Flags that indicate whether an instruction can be modified by a method.
405 //===--------------------------------------------------------------------===//
406
407 /// isCommutable - Return true if this may be a 2- or 3-address
408 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
409 /// result if Y and Z are exchanged. If this flag is set, then the
410 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
411 /// instruction.
412 ///
413 /// Note that this flag may be set on instructions that are only commutable
414 /// sometimes. In these cases, the call to commuteInstruction will fail.
415 /// Also note that some instructions require non-trivial modification to
416 /// commute them.
417 bool isCommutable() const {
418 return Flags & (1 << TID::Commutable);
419 }
420
421 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
422 /// which can be changed into a 3-address instruction if needed. Doing this
423 /// transformation can be profitable in the register allocator, because it
424 /// means that the instruction can use a 2-address form if possible, but
425 /// degrade into a less efficient form if the source and dest register cannot
426 /// be assigned to the same register. For example, this allows the x86
427 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
428 /// is the same speed as the shift but has bigger code size.
429 ///
430 /// If this returns true, then the target must implement the
431 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
432 /// is allowed to fail if the transformation isn't valid for this specific
433 /// instruction (e.g. shl reg, 4 on x86).
434 ///
435 bool isConvertibleTo3Addr() const {
436 return Flags & (1 << TID::ConvertibleTo3Addr);
437 }
438
439 /// usesCustomInsertionHook - Return true if this instruction requires
440 /// custom insertion support when the DAG scheduler is inserting it into a
441 /// machine basic block. If this is true for the instruction, it basically
442 /// means that it is a pseudo instruction used at SelectionDAG time that is
443 /// expanded out into magic code by the target when MachineInstrs are formed.
444 ///
445 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
446 /// is used to insert this into the MachineBasicBlock.
447 bool usesCustomInsertionHook() const {
448 return Flags & (1 << TID::UsesCustomInserter);
449 }
450
451 /// isRematerializable - Returns true if this instruction is a candidate for
452 /// remat. This flag is deprecated, please don't use it anymore. If this
453 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
454 /// verify the instruction is really rematable.
455 bool isRematerializable() const {
456 return Flags & (1 << TID::Rematerializable);
457 }
458
459 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
460 /// less) than a move instruction. This is useful during certain types of
461 /// optimizations (e.g., remat during two-address conversion or machine licm)
462 /// where we would like to remat or hoist the instruction, but not if it costs
463 /// more than moving the instruction into the appropriate register. Note, we
464 /// are not marking copies from and to the same register class with this flag.
465 bool isAsCheapAsAMove() const {
466 return Flags & (1 << TID::CheapAsAMove);
467 }
468
469 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
470 /// have special register allocation requirements that are not captured by the
471 /// operand register classes. e.g. ARM::STRD's two source registers must be an
472 /// even / odd pair, ARM::STM registers have to be in ascending order.
473 /// Post-register allocation passes should not attempt to change allocations
474 /// for sources of instructions with this flag.
475 bool hasExtraSrcRegAllocReq() const {
476 return Flags & (1 << TID::ExtraSrcRegAllocReq);
477 }
478
479 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
480 /// have special register allocation requirements that are not captured by the
481 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
482 /// even / odd pair, ARM::LDM registers have to be in ascending order.
483 /// Post-register allocation passes should not attempt to change allocations
484 /// for definitions of instructions with this flag.
485 bool hasExtraDefRegAllocReq() const {
486 return Flags & (1 << TID::ExtraDefRegAllocReq);
487 }
488 };
489
490 } // end namespace llvm
491
492 #endif
1313 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
1414 #define LLVM_TARGET_TARGETINSTRINFO_H
1515
16 #include "llvm/Target/TargetInstrDesc.h"
16 #include "llvm/MC/MCInstrInfo.h"
1717 #include "llvm/CodeGen/MachineFunction.h"
1818
1919 namespace llvm {
3939 ///
4040 /// TargetInstrInfo - Interface to description of machine instruction set
4141 ///
42 class TargetInstrInfo {
43 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
44 unsigned NumOpcodes; // Number of entries in the desc array
45
42 class TargetInstrInfo : public MCInstrInfo {
4643 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
4744 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
4845 public:
49 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
46 TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes);
5047 virtual ~TargetInstrInfo();
51
52 unsigned getNumOpcodes() const { return NumOpcodes; }
53
54 /// get - Return the machine instruction descriptor that corresponds to the
55 /// specified instruction opcode.
56 ///
57 const TargetInstrDesc &get(unsigned Opcode) const {
58 assert(Opcode < NumOpcodes && "Invalid opcode!");
59 return Descriptors[Opcode];
60 }
6148
6249 /// getRegClass - Givem a machine instruction descriptor, returns the register
6350 /// class constraint for OpNum, or NULL.
64 const TargetRegisterClass *getRegClass(const TargetInstrDesc &TID,
51 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
6552 unsigned OpNum,
6653 const TargetRegisterInfo *TRI) const;
6754
676663 /// libcodegen, not in libtarget.
677664 class TargetInstrInfoImpl : public TargetInstrInfo {
678665 protected:
679 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
666 TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes)
680667 : TargetInstrInfo(desc, NumOpcodes) {}
681668 public:
682669 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
494494 }
495495
496496 /// getRegClass - Returns the register class associated with the enumeration
497 /// value. See class TargetOperandInfo.
497 /// value. See class MCOperandInfo.
498498 const TargetRegisterClass *getRegClass(unsigned i) const {
499499 assert(i < getNumRegClasses() && "Register Class ID out of range");
500500 return RegClassBegin[i];
420420 for (; I != E; ++I) {
421421 if (I->isDebugValue())
422422 continue;
423 const TargetInstrDesc &TID = I->getDesc();
424 if (TID.isCall())
423 const MCInstrDesc &MCID = I->getDesc();
424 if (MCID.isCall())
425425 Time += 10;
426 else if (TID.mayLoad() || TID.mayStore())
426 else if (MCID.mayLoad() || MCID.mayStore())
427427 Time += 2;
428428 else
429429 ++Time;
6161 MachineInstr *MI = MBBI++;
6262
6363 // If MI is a pseudo, expand it.
64 const TargetInstrDesc &TID = MI->getDesc();
65 if (TID.usesCustomInsertionHook()) {
64 const MCInstrDesc &MCID = MI->getDesc();
65 if (MCID.usesCustomInsertionHook()) {
6666 Changed = true;
6767 MachineBasicBlock *NewMBB =
6868 TLI->EmitInstrWithCustomInserter(MI, MBB);
650650 if (I->isDebugValue())
651651 continue;
652652
653 const TargetInstrDesc &TID = I->getDesc();
654 if (TID.isNotDuplicable())
653 const MCInstrDesc &MCID = I->getDesc();
654 if (MCID.isNotDuplicable())
655655 BBI.CannotBeCopied = true;
656656
657657 bool isPredicated = TII->isPredicated(I);
658 bool isCondBr = BBI.IsBrAnalyzable && TID.isConditionalBranch();
658 bool isCondBr = BBI.IsBrAnalyzable && MCID.isConditionalBranch();
659659
660660 if (!isCondBr) {
661661 if (!isPredicated) {
14131413
14141414 for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
14151415 E = FromBBI.BB->end(); I != E; ++I) {
1416 const TargetInstrDesc &TID = I->getDesc();
1416 const MCInstrDesc &MCID = I->getDesc();
14171417 // Do not copy the end of the block branches.
1418 if (IgnoreBr && TID.isBranch())
1418 if (IgnoreBr && MCID.isBranch())
14191419 break;
14201420
14211421 MachineInstr *MI = MF.CloneMachineInstr(I);
2121 #include "llvm/MC/MCContext.h"
2222 #include "llvm/Target/TargetRegisterInfo.h"
2323 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetInstrDesc.h"
2524 #include "llvm/Target/TargetInstrInfo.h"
2625 #include "llvm/Target/TargetMachine.h"
2726 #include "llvm/Assembly/Writer.h"
259259 return false;
260260
261261 // Ignore stuff that we obviously can't move.
262 const TargetInstrDesc &TID = MI->getDesc();
263 if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
262 const MCInstrDesc &MCID = MI->getDesc();
263 if (MCID.mayStore() || MCID.isCall() || MCID.isTerminator() ||
264264 MI->hasUnmodeledSideEffects())
265265 return false;
266266
267 if (TID.mayLoad()) {
267 if (MCID.mayLoad()) {
268268 // Okay, this instruction does a load. As a refinement, we allow the target
269269 // to decide whether the loaded value is actually a constant. If so, we can
270270 // actually use it as a load.
151151 /// of `new MachineInstr'.
152152 ///
153153 MachineInstr *
154 MachineFunction::CreateMachineInstr(const TargetInstrDesc &TID,
154 MachineFunction::CreateMachineInstr(const MCInstrDesc &MCID,
155155 DebugLoc DL, bool NoImp) {
156156 return new (InstructionRecycler.Allocate(Allocator))
157 MachineInstr(TID, DL, NoImp);
157 MachineInstr(MCID, DL, NoImp);
158158 }
159159
160160 /// CloneMachineInstr - Create a new MachineInstr which is a copy of the
2323 #include "llvm/CodeGen/MachineMemOperand.h"
2424 #include "llvm/CodeGen/MachineRegisterInfo.h"
2525 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/MC/MCInstrDesc.h"
2627 #include "llvm/MC/MCSymbol.h"
2728 #include "llvm/Target/TargetMachine.h"
2829 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetInstrDesc.h"
3030 #include "llvm/Target/TargetRegisterInfo.h"
3131 #include "llvm/Analysis/AliasAnalysis.h"
3232 #include "llvm/Analysis/DebugInfo.h"
456456 //===----------------------------------------------------------------------===//
457457
458458 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
459 /// TID NULL and no operands.
459 /// MCID NULL and no operands.
460460 MachineInstr::MachineInstr()
461 : TID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
461 : MCID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
462462 MemRefs(0), MemRefsEnd(0),
463463 Parent(0) {
464464 // Make sure that we get added to a machine basicblock
466466 }
467467
468468 void MachineInstr::addImplicitDefUseOperands() {
469 if (TID->ImplicitDefs)
470 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
469 if (MCID->ImplicitDefs)
470 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
471471 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
472 if (TID->ImplicitUses)
473 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
472 if (MCID->ImplicitUses)
473 for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
474474 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
475475 }
476476
477477 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
478478 /// implicit operands. It reserves space for the number of operands specified by
479 /// the TargetInstrDesc.
480 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
481 : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
479 /// the MCInstrDesc.
480 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
481 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
482482 MemRefs(0), MemRefsEnd(0), Parent(0) {
483483 if (!NoImp)
484 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
485 Operands.reserve(NumImplicitOps + TID->getNumOperands());
484 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
485 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
486486 if (!NoImp)
487487 addImplicitDefUseOperands();
488488 // Make sure that we get added to a machine basicblock
490490 }
491491
492492 /// MachineInstr ctor - As above, but with a DebugLoc.
493 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
493 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
494494 bool NoImp)
495 : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
495 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
496496 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
497497 if (!NoImp)
498 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
499 Operands.reserve(NumImplicitOps + TID->getNumOperands());
498 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
499 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
500500 if (!NoImp)
501501 addImplicitDefUseOperands();
502502 // Make sure that we get added to a machine basicblock
506506 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
507507 /// that the MachineInstr is created and added to the end of the specified
508508 /// basic block.
509 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
510 : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
509 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
510 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
511511 MemRefs(0), MemRefsEnd(0), Parent(0) {
512512 assert(MBB && "Cannot use inserting ctor with null basic block!");
513 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
514 Operands.reserve(NumImplicitOps + TID->getNumOperands());
513 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
514 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
515515 addImplicitDefUseOperands();
516516 // Make sure that we get added to a machine basicblock
517517 LeakDetector::addGarbageObject(this);
521521 /// MachineInstr ctor - As above, but with a DebugLoc.
522522 ///
523523 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
524 const TargetInstrDesc &tid)
525 : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
524 const MCInstrDesc &tid)
525 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
526526 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
527527 assert(MBB && "Cannot use inserting ctor with null basic block!");
528 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
529 Operands.reserve(NumImplicitOps + TID->getNumOperands());
528 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
529 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
530530 addImplicitDefUseOperands();
531531 // Make sure that we get added to a machine basicblock
532532 LeakDetector::addGarbageObject(this);
536536 /// MachineInstr ctor - Copies MachineInstr arg exactly
537537 ///
538538 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
539 : TID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
539 : MCID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
540540 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
541541 Parent(0), debugLoc(MI.getDebugLoc()) {
542542 Operands.reserve(MI.getNumOperands());
623623 Operands.back().AddRegOperandToRegInfo(RegInfo);
624624 // If the register operand is flagged as early, mark the operand as such
625625 unsigned OpNo = Operands.size() - 1;
626 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
626 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
627627 Operands[OpNo].setIsEarlyClobber(true);
628628 }
629629 return;
645645 if (Operands[OpNo].isReg()) {
646646 Operands[OpNo].AddRegOperandToRegInfo(0);
647647 // If the register operand is flagged as early, mark the operand as such
648 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
648 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
649649 Operands[OpNo].setIsEarlyClobber(true);
650650 }
651651
670670 if (Operands[OpNo].isReg()) {
671671 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
672672 // If the register operand is flagged as early, mark the operand as such
673 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
673 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
674674 Operands[OpNo].setIsEarlyClobber(true);
675675 }
676676
693693
694694 // If the register operand is flagged as early, mark the operand as such
695695 if (Operands[OpNo].isReg()
696 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
696 && MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
697697 Operands[OpNo].setIsEarlyClobber(true);
698698 }
699699 }
819819 /// OperandComplete - Return true if it's illegal to add a new operand
820820 ///
821821 bool MachineInstr::OperandsComplete() const {
822 unsigned short NumOperands = TID->getNumOperands();
823 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
822 unsigned short NumOperands = MCID->getNumOperands();
823 if (!MCID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
824824 return true; // Broken: we have all the operands of this instruction!
825825 return false;
826826 }
828828 /// getNumExplicitOperands - Returns the number of non-implicit operands.
829829 ///
830830 unsigned MachineInstr::getNumExplicitOperands() const {
831 unsigned NumOperands = TID->getNumOperands();
832 if (!TID->isVariadic())
831 unsigned NumOperands = MCID->getNumOperands();
832 if (!MCID->isVariadic())
833833 return NumOperands;
834834
835835 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
930930 /// operand list that is used to represent the predicate. It returns -1 if
931931 /// none is found.
932932 int MachineInstr::findFirstPredOperandIdx() const {
933 const TargetInstrDesc &TID = getDesc();
934 if (TID.isPredicable()) {
933 const MCInstrDesc &MCID = getDesc();
934 if (MCID.isPredicable()) {
935935 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
936 if (TID.OpInfo[i].isPredicate())
936 if (MCID.OpInfo[i].isPredicate())
937937 return i;
938938 }
939939
989989 }
990990
991991 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
992 const TargetInstrDesc &TID = getDesc();
993 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
992 const MCInstrDesc &MCID = getDesc();
993 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
994994 const MachineOperand &MO = getOperand(i);
995995 if (MO.isReg() && MO.isUse() &&
996 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
996 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
997997 if (UseOpIdx)
998998 *UseOpIdx = (unsigned)i;
999999 return true;
10491049 return false;
10501050 }
10511051
1052 const TargetInstrDesc &TID = getDesc();
1053 if (UseOpIdx >= TID.getNumOperands())
1052 const MCInstrDesc &MCID = getDesc();
1053 if (UseOpIdx >= MCID.getNumOperands())
10541054 return false;
10551055 const MachineOperand &MO = getOperand(UseOpIdx);
10561056 if (!MO.isReg() || !MO.isUse())
10571057 return false;
1058 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
1058 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
10591059 if (DefIdx == -1)
10601060 return false;
10611061 if (DefOpIdx)
10951095
10961096 /// copyPredicates - Copies predicate operand(s) from MI.
10971097 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1098 const TargetInstrDesc &TID = MI->getDesc();
1099 if (!TID.isPredicable())
1098 const MCInstrDesc &MCID = MI->getDesc();
1099 if (!MCID.isPredicable())
11001100 return;
11011101 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1102 if (TID.OpInfo[i].isPredicate()) {
1102 if (MCID.OpInfo[i].isPredicate()) {
11031103 // Predicated operands must be last operands.
11041104 addOperand(MI->getOperand(i));
11051105 }
11361136 AliasAnalysis *AA,
11371137 bool &SawStore) const {
11381138 // Ignore stuff that we obviously can't move.
1139 if (TID->mayStore() || TID->isCall()) {
1139 if (MCID->mayStore() || MCID->isCall()) {
11401140 SawStore = true;
11411141 return false;
11421142 }
11431143
11441144 if (isLabel() || isDebugValue() ||
1145 TID->isTerminator() || hasUnmodeledSideEffects())
1145 MCID->isTerminator() || hasUnmodeledSideEffects())
11461146 return false;
11471147
11481148 // See if this instruction does a load. If so, we have to guarantee that the
11501150 // destination. The check for isInvariantLoad gives the targe the chance to
11511151 // classify the load as always returning a constant, e.g. a constant pool
11521152 // load.
1153 if (TID->mayLoad() && !isInvariantLoad(AA))
1153 if (MCID->mayLoad() && !isInvariantLoad(AA))
11541154 // Otherwise, this is a real load. If there is a store between the load and
11551155 // end of block, or if the load is volatile, we can't move it.
11561156 return !SawStore && !hasVolatileMemoryRef();
11901190 /// have no volatile memory references.
11911191 bool MachineInstr::hasVolatileMemoryRef() const {
11921192 // An instruction known never to access memory won't have a volatile access.
1193 if (!TID->mayStore() &&
1194 !TID->mayLoad() &&
1195 !TID->isCall() &&
1193 if (!MCID->mayStore() &&
1194 !MCID->mayLoad() &&
1195 !MCID->isCall() &&
11961196 !hasUnmodeledSideEffects())
11971197 return false;
11981198
12161216 /// *all* loads the instruction does are invariant (if it does multiple loads).
12171217 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
12181218 // If the instruction doesn't load at all, it isn't an invariant load.
1219 if (!TID->mayLoad())
1219 if (!MCID->mayLoad())
12201220 return false;
12211221
12221222 // If the instruction has lost its memoperands, conservatively assume that
14201420 if (FirstOp) FirstOp = false; else OS << ",";
14211421 OS << " ";
14221422 if (i < getDesc().NumOperands) {
1423 const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1424 if (TOI.isPredicate())
1423 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1424 if (MCOI.isPredicate())
14251425 OS << "pred:";
1426 if (TOI.isOptionalDef())
1426 if (MCOI.isOptionalDef())
14271427 OS << "opt:";
14281428 }
14291429 if (isDebugValue() && MO.isMetadata()) {
10171017 /*UnfoldStore=*/false,
10181018 &LoadRegIndex);
10191019 if (NewOpc == 0) return 0;
1020 const TargetInstrDesc &TID = TII->get(NewOpc);
1021 if (TID.getNumDefs() != 1) return 0;
1022 const TargetRegisterClass *RC = TII->getRegClass(TID, LoadRegIndex, TRI);
1020 const MCInstrDesc &MID = TII->get(NewOpc);
1021 if (MID.getNumDefs() != 1) return 0;
1022 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI);
10231023 // Ok, we're unfolding. Create a temporary register and do the unfold.
10241024 unsigned Reg = MRI->createVirtualRegister(RC);
10251025
540540 }
541541
542542 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
543 const TargetInstrDesc &TI = MI->getDesc();
544 if (MI->getNumOperands() < TI.getNumOperands()) {
543 const MCInstrDesc &MCID = MI->getDesc();
544 if (MI->getNumOperands() < MCID.getNumOperands()) {
545545 report("Too few operands", MI);
546 *OS << TI.getNumOperands() << " operands expected, but "
546 *OS << MCID.getNumOperands() << " operands expected, but "
547547 << MI->getNumExplicitOperands() << " given.\n";
548548 }
549549
550550 // Check the MachineMemOperands for basic consistency.
551551 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
552552 E = MI->memoperands_end(); I != E; ++I) {
553 if ((*I)->isLoad() && !TI.mayLoad())
553 if ((*I)->isLoad() && !MCID.mayLoad())
554554 report("Missing mayLoad flag", MI);
555 if ((*I)->isStore() && !TI.mayStore())
555 if ((*I)->isStore() && !MCID.mayStore())
556556 report("Missing mayStore flag", MI);
557557 }
558558
574574 void
575575 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
576576 const MachineInstr *MI = MO->getParent();
577 const TargetInstrDesc &TI = MI->getDesc();
578 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
579
580 // The first TI.NumDefs operands must be explicit register defines
581 if (MONum < TI.getNumDefs()) {
577 const MCInstrDesc &MCID = MI->getDesc();
578 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
579
580 // The first MCID.NumDefs operands must be explicit register defines
581 if (MONum < MCID.getNumDefs()) {
582582 if (!MO->isReg())
583583 report("Explicit definition must be a register", MO, MONum);
584584 else if (!MO->isDef())
585585 report("Explicit definition marked as use", MO, MONum);
586586 else if (MO->isImplicit())
587587 report("Explicit definition marked as implicit", MO, MONum);
588 } else if (MONum < TI.getNumOperands()) {
588 } else if (MONum < MCID.getNumOperands()) {
589589 // Don't check if it's the last operand in a variadic instruction. See,
590590 // e.g., LDM_RET in the arm back end.
591 if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) {
592 if (MO->isDef() && !TOI.isOptionalDef())
591 if (MO->isReg() &&
592 !(MCID.isVariadic() && MONum == MCID.getNumOperands()-1)) {
593 if (MO->isDef() && !MCOI.isOptionalDef())
593594 report("Explicit operand marked as def", MO, MONum);
594595 if (MO->isImplicit())
595596 report("Explicit operand marked as implicit", MO, MONum);
596597 }
597598 } else {
598599 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
599 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
600 if (MO->isReg() && !MO->isImplicit() && !MCID.isVariadic() && MO->getReg())
600601 report("Extra explicit operand on non-variadic instruction", MO, MONum);
601602 }
602603
708709 }
709710
710711 // Check register classes.
711 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
712 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
712713 unsigned SubIdx = MO->getSubReg();
713714
714715 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
722723 }
723724 sr = s;
724725 }
725 if (const TargetRegisterClass *DRC = TII->getRegClass(TI, MONum, TRI)) {
726 if (const TargetRegisterClass *DRC = TII->getRegClass(MCID,MONum,TRI)) {
726727 if (!DRC->contains(sr)) {
727728 report("Illegal physical register for instruction", MO, MONum);
728729 *OS << TRI->getName(sr) << " is not a "
742743 }
743744 RC = SRC;
744745 }
745 if (const TargetRegisterClass *DRC = TII->getRegClass(TI, MONum, TRI)) {
746 if (const TargetRegisterClass *DRC = TII->getRegClass(MCID,MONum,TRI)) {
746747 if (!RC->hasSuperClassEq(DRC)) {
747748 report("Illegal virtual register for instruction", MO, MONum);
748749 *OS << "Expected a " << DRC->getName() << " register, but got a "
764765 LiveInts && !LiveInts->isNotInMIMap(MI)) {
765766 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
766767 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
767 if (TI.mayLoad() && !LI.liveAt(Idx.getUseIndex())) {
768 if (MCID.mayLoad() && !LI.liveAt(Idx.getUseIndex())) {
768769 report("Instruction loads from dead spill slot", MO, MONum);
769770 *OS << "Live stack: " << LI << '\n';
770771 }
771 if (TI.mayStore() && !LI.liveAt(Idx.getDefIndex())) {
772 if (MCID.mayStore() && !LI.liveAt(Idx.getDefIndex())) {
772773 report("Instruction stores to dead spill slot", MO, MONum);
773774 *OS << "Live stack: " << LI << '\n';
774775 }
352352 bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI,
353353 SmallSet &ImmDefRegs,
354354 DenseMap &ImmDefMIs) {
355 const TargetInstrDesc &TID = MI->getDesc();
356 if (!TID.isMoveImmediate())
357 return false;
358 if (TID.getNumDefs() != 1)
355 const MCInstrDesc &MCID = MI->getDesc();
356 if (!MCID.isMoveImmediate())
357 return false;
358 if (MCID.getNumDefs() != 1)
359359 return false;
360360 unsigned Reg = MI->getOperand(0).getReg();
361361 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
428428 continue;
429429 }
430430
431 const TargetInstrDesc &TID = MI->getDesc();
432
433 if (TID.isBitcast()) {
431 const MCInstrDesc &MCID = MI->getDesc();
432
433 if (MCID.isBitcast()) {
434434 if (OptimizeBitcastInstr(MI, MBB)) {
435435 // MI is deleted.
436436 Changed = true;
437437 MII = First ? I->begin() : llvm::next(PMII);
438438 continue;
439439 }
440 } else if (TID.isCompare()) {
440 } else if (MCID.isCompare()) {
441441 if (OptimizeCmpInstr(MI, MBB)) {
442442 // MI is deleted.
443443 Changed = true;
117117 // SkippedInstrs - Descriptors of instructions whose clobber list was
118118 // ignored because all registers were spilled. It is still necessary to
119119 // mark all the clobbered registers as used by the function.
120 SmallPtrSetTargetInstrDesc*, 4> SkippedInstrs;
120 SmallPtrSetMCInstrDesc*, 4> SkippedInstrs;
121121
122122 // isBulkSpilling - This flag is set when LiveRegMap will be cleared
123123 // completely after spilling all live registers. LiveRegMap entries should
776776 // Otherwise, sequentially allocate each instruction in the MBB.
777777 while (MII != MBB->end()) {
778778 MachineInstr *MI = MII++;
779 const TargetInstrDesc &TID = MI->getDesc();
779 const MCInstrDesc &MCID = MI->getDesc();
780780 DEBUG({
781781 dbgs() << "\n>> " << *MI << "Regs:";
782782 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
889889 VirtOpEnd = i+1;
890890 if (MO.isUse()) {
891891 hasTiedOps = hasTiedOps ||
892 TID.getOperandConstraint(i, TOI::TIED_TO) != -1;
892 MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1;
893893 } else {
894894 if (MO.isEarlyClobber())
895895 hasEarlyClobbers = true;
919919 // We didn't detect inline asm tied operands above, so just make this extra
920920 // pass for all inline asm.
921921 if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
922 (hasTiedOps && (hasPhysDefs || TID.getNumDefs() > 1))) {
922 (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) {
923923 handleThroughOperands(MI, VirtDead);
924924 // Don't attempt coalescing when we have funny stuff going on.
925925 CopyDst = 0;
964964 }
965965
966966 unsigned DefOpEnd = MI->getNumOperands();
967 if (TID.isCall()) {
967 if (MCID.isCall()) {
968968 // Spill all virtregs before a call. This serves two purposes: 1. If an
969969 // exception is thrown, the landing pad is going to expect to find
970970 // registers in their spill slots, and 2. we don't have to wade through
975975
976976 // The imp-defs are skipped below, but we still need to mark those
977977 // registers as used by the function.
978 SkippedInstrs.insert(&TID);
978 SkippedInstrs.insert(&MCID);
979979 }
980980
981981 // Third scan.
10611061 MRI->closePhysRegsUsed(*TRI);
10621062
10631063 // Add the clobber lists for all the instructions we skipped earlier.
1064 for (SmallPtrSetTargetInstrDesc*, 4>::const_iterator
1064 for (SmallPtrSetMCInstrDesc*, 4>::const_iterator
10651065 I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I)
10661066 if (const unsigned *Defs = (*I)->getImplicitDefs())
10671067 while (*Defs)
525525 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
526526 if (!DefMI)
527527 return false;
528 const TargetInstrDesc &TID = DefMI->getDesc();
529 if (!TID.isCommutable())
528 const MCInstrDesc &MCID = DefMI->getDesc();
529 if (!MCID.isCommutable())
530530 return false;
531531 // If DefMI is a two-address instruction then commuting it will change the
532532 // destination register.
686686 if (!DefMI)
687687 return false;
688688 assert(DefMI && "Defining instruction disappeared");
689 const TargetInstrDesc &TID = DefMI->getDesc();
690 if (!TID.isAsCheapAsAMove())
689 const MCInstrDesc &MCID = DefMI->getDesc();
690 if (!MCID.isAsCheapAsAMove())
691691 return false;
692692 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
693693 return false;
694694 bool SawStore = false;
695695 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
696696 return false;
697 if (TID.getNumDefs() != 1)
697 if (MCID.getNumDefs() != 1)
698698 return false;
699699 if (!DefMI->isImplicitDef()) {
700700 // Make sure the copy destination register class fits the instruction
701701 // definition register class. The mismatch can happen as a result of earlier
702702 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
703 const TargetRegisterClass *RC = tii_->getRegClass(TID, 0, tri_);
703 const TargetRegisterClass *RC = tii_->getRegClass(MCID, 0, tri_);
704704 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
705705 if (mri_->getRegClass(DstReg) != RC)
706706 return false;
711711 // If destination register has a sub-register index on it, make sure it
712712 // matches the instruction register class.
713713 if (DstSubIdx) {
714 const TargetInstrDesc &TID = DefMI->getDesc();
715 if (TID.getNumDefs() != 1)
714 const MCInstrDesc &MCID = DefMI->getDesc();
715 if (MCID.getNumDefs() != 1)
716716 return false;
717717 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
718718 const TargetRegisterClass *DstSubRC =
719719 DstRC->getSubRegisterRegClass(DstSubIdx);
720 const TargetRegisterClass *DefRC = tii_->getRegClass(TID, 0, tri_);
720 const TargetRegisterClass *DefRC = tii_->getRegClass(MCID, 0, tri_);
721721 if (DefRC == DstRC)
722722 DstSubIdx = 0;
723723 else if (DefRC != DstSubRC)
4444 ScheduleDAG::~ScheduleDAG() {}
4545
4646 /// getInstrDesc helper to handle SDNodes.
47 const TargetInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
47 const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
4848 if (!Node || !Node->isMachineOpcode()) return NULL;
4949 return &TII->get(Node->getMachineOpcode());
5050 }
235235 continue;
236236 }
237237
238 const TargetInstrDesc &TID = MI->getDesc();
239 assert(!TID.isTerminator() && !MI->isLabel() &&
238 const MCInstrDesc &MCID = MI->getDesc();
239 assert(!MCID.isTerminator() && !MI->isLabel() &&
240240 "Cannot schedule terminators or labels!");
241241 // Create the SUnit for this MI.
242242 SUnit *SU = NewSUnit(MI);
243 SU->isCall = TID.isCall();
244 SU->isCommutable = TID.isCommutable();
243 SU->isCall = MCID.isCall();
244 SU->isCommutable = MCID.isCommutable();
245245
246246 // Assign the Latency field of SU using target-provided information.
247247 if (UnitLatencies)
308308 if (SpecialAddressLatency != 0 && !UnitLatencies &&
309309 UseSU != &ExitSU) {
310310 MachineInstr *UseMI = UseSU->getInstr();
311 const TargetInstrDesc &UseTID = UseMI->getDesc();
311 const MCInstrDesc &UseMCID = UseMI->getDesc();
312312 int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
313313 assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
314314 if (RegUseIndex >= 0 &&
315 (UseTID.mayLoad() || UseTID.mayStore()) &&
316 (unsigned)RegUseIndex < UseTID.getNumOperands() &&
317 UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass())
315 (UseMCID.mayLoad() || UseMCID.mayStore()) &&
316 (unsigned)RegUseIndex < UseMCID.getNumOperands() &&
317 UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
318318 LDataLatency += SpecialAddressLatency;
319319 }
320320 // Adjust the dependence latency using operand def/use
351351 unsigned Count = I->second.second;
352352 const MachineInstr *UseMI = UseMO->getParent();
353353 unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
354 const TargetInstrDesc &UseTID = UseMI->getDesc();
354 const MCInstrDesc &UseMCID = UseMI->getDesc();
355355 // TODO: If we knew the total depth of the region here, we could
356356 // handle the case where the whole loop is inside the region but
357357 // is large enough that the isScheduleHigh trick isn't needed.
358 if (UseMOIdx < UseTID.getNumOperands()) {
358 if (UseMOIdx < UseMCID.getNumOperands()) {
359359 // Currently, we only support scheduling regions consisting of
360360 // single basic blocks. Check to see if the instruction is in
361361 // the same region by checking to see if it has the same parent.
362362 if (UseMI->getParent() != MI->getParent()) {
363363 unsigned Latency = SU->Latency;
364 if (UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass())
364 if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass())
365365 Latency += SpecialAddressLatency;
366366 // This is a wild guess as to the portion of the latency which
367367 // will be overlapped by work done outside the current
373373 /*isMustAlias=*/false,
374374 /*isArtificial=*/true));
375375 } else if (SpecialAddressLatency > 0 &&
376 UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
376 UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
377377 // The entire loop body is within the current scheduling region
378378 // and the latency of this operation is assumed to be greater
379379 // than the latency of the loop.
416416 // produce more precise dependence information.
417417 #define STORE_LOAD_LATENCY 1
418418 unsigned TrueMemOrderLatency = 0;
419 if (TID.isCall() || MI->hasUnmodeledSideEffects() ||
419 if (MCID.isCall() || MI->hasUnmodeledSideEffects() ||
420420 (MI->hasVolatileMemoryRef() &&
421 (!TID.mayLoad() || !MI->isInvariantLoad(AA)))) {
421 (!MCID.mayLoad() || !MI->isInvariantLoad(AA)))) {
422422 // Be conservative with these and add dependencies on all memory
423423 // references, even those that are known to not alias.
424424 for (std::map::iterator I =
457457 PendingLoads.clear();
458458 AliasMemDefs.clear();
459459 AliasMemUses.clear();
460 } else if (TID.mayStore()) {
460 } else if (MCID.mayStore()) {
461461 bool MayAlias = true;
462462 TrueMemOrderLatency = STORE_LOAD_LATENCY;
463463 if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
513513 /*Reg=*/0, /*isNormalMemory=*/false,
514514 /*isMustAlias=*/false,
515515 /*isArtificial=*/true));
516 } else if (TID.mayLoad()) {
516 } else if (MCID.mayLoad()) {
517517 bool MayAlias = true;
518518 TrueMemOrderLatency = 0;
519519 if (MI->isInvariantLoad(AA)) {
114114 // Use the itinerary for the underlying instruction to check for
115115 // free FU's in the scoreboard at the appropriate future cycles.
116116
117 const TargetInstrDesc *TID = DAG->getInstrDesc(SU);
118 if (TID == NULL) {
117 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
118 if (MCID == NULL) {
119119 // Don't check hazards for non-machineinstr Nodes.
120120 return NoHazard;
121121 }
122 unsigned idx = TID->getSchedClass();
122 unsigned idx = MCID->getSchedClass();
123123 for (const InstrStage *IS = ItinData->beginStage(idx),
124124 *E = ItinData->endStage(idx); IS != E; ++IS) {
125125 // We must find one of the stage's units free for every cycle the
172172
173173 // Use the itinerary for the underlying instruction to reserve FU's
174174 // in the scoreboard at the appropriate future cycles.
175 const TargetInstrDesc *TID = DAG->getInstrDesc(SU);
176 assert(TID && "The scheduler must filter non-machineinstrs");
177 if (DAG->TII->isZeroCost(TID->Opcode))
175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
176 assert(MCID && "The scheduler must filter non-machineinstrs");
177 if (DAG->TII->isZeroCost(MCID->Opcode))
178178 return;
179179
180180 ++IssueCount;
181181
182182 unsigned cycle = 0;
183183
184 unsigned idx = TID->getSchedClass();
184 unsigned idx = MCID->getSchedClass();
185185 for (const InstrStage *IS = ItinData->beginStage(idx),
186186 *E = ItinData->endStage(idx); IS != E; ++IS) {
187187 // We must reserve one of the stage's units for every cycle the
568568 case Intrinsic::dbg_value: {
569569 // This form of DBG_VALUE is target-independent.
570570 const DbgValueInst *DI = cast(Call);
571 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
571 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
572572 const Value *V = DI->getValue();
573573 if (!V) {
574574 // Currently the optimizer can produce this; insert an undef to
11111111 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
11121112 const TargetRegisterClass* RC) {
11131113 unsigned ResultReg = createResultReg(RC);
1114 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1114 const MCInstrDesc &II = TII.get(MachineInstOpcode);
11151115
11161116 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg);
11171117 return ResultReg;
11211121 const TargetRegisterClass *RC,
11221122 unsigned Op0, bool Op0IsKill) {
11231123 unsigned ResultReg = createResultReg(RC);
1124 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1124 const MCInstrDesc &II = TII.get(MachineInstOpcode);
11251125
11261126 if (II.getNumDefs() >= 1)
11271127 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
11411141 unsigned Op0, bool Op0IsKill,
11421142 unsigned Op1, bool Op1IsKill) {
11431143 unsigned ResultReg = createResultReg(RC);
1144 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1144 const MCInstrDesc &II = TII.get(MachineInstOpcode);
11451145
11461146 if (II.getNumDefs() >= 1)
11471147 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
11631163 unsigned Op1, bool Op1IsKill,
11641164 unsigned Op2, bool Op2IsKill) {
11651165 unsigned ResultReg = createResultReg(RC);
1166 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1166 const MCInstrDesc &II = TII.get(MachineInstOpcode);
11671167
11681168 if (II.getNumDefs() >= 1)
11691169 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
11861186 unsigned Op0, bool Op0IsKill,
11871187 uint64_t Imm) {
11881188 unsigned ResultReg = createResultReg(RC);
1189 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1189 const MCInstrDesc &II = TII.get(MachineInstOpcode);
11901190
11911191 if (II.getNumDefs() >= 1)
11921192 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
12071207 unsigned Op0, bool Op0IsKill,
12081208 uint64_t Imm1, uint64_t Imm2) {
12091209 unsigned ResultReg = createResultReg(RC);
1210 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1210 const MCInstrDesc &II = TII.get(MachineInstOpcode);
12111211
12121212 if (II.getNumDefs() >= 1)
12131213 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
12301230 unsigned Op0, bool Op0IsKill,
12311231 const ConstantFP *FPImm) {
12321232 unsigned ResultReg = createResultReg(RC);
1233 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1233 const MCInstrDesc &II = TII.get(MachineInstOpcode);
12341234
12351235 if (II.getNumDefs() >= 1)
12361236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
12521252 unsigned Op1, bool Op1IsKill,
12531253 uint64_t Imm) {
12541254 unsigned ResultReg = createResultReg(RC);
1255 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1255 const MCInstrDesc &II = TII.get(MachineInstOpcode);
12561256
12571257 if (II.getNumDefs() >= 1)
12581258 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
12741274 const TargetRegisterClass *RC,
12751275 uint64_t Imm) {
12761276 unsigned ResultReg = createResultReg(RC);
1277 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1277 const MCInstrDesc &II = TII.get(MachineInstOpcode);
12781278
12791279 if (II.getNumDefs() >= 1)
12801280 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
12901290 const TargetRegisterClass *RC,
12911291 uint64_t Imm1, uint64_t Imm2) {
12921292 unsigned ResultReg = createResultReg(RC);
1293 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1293 const MCInstrDesc &II = TII.get(MachineInstOpcode);
12941294
12951295 if (II.getNumDefs() >= 1)
12961296 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
105105 continue;
106106 Match = false;
107107 if (User->isMachineOpcode()) {
108 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
108 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
109109 const TargetRegisterClass *RC = 0;
110110 if (i+II.getNumDefs() < II.getNumOperands())
111111 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
177177 }
178178
179179 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
180 const TargetInstrDesc &II,
180 const MCInstrDesc &II,
181181 bool IsClone, bool IsCloned,
182182 DenseMap &VRBaseMap) {
183183 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
241241 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
242242 // Add an IMPLICIT_DEF instruction before every use.
243243 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
244 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
244 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
245245 // does not include operand register class info.
246246 if (!VReg) {
247247 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
264264 void
265265 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
266266 unsigned IIOpNum,
267 const TargetInstrDesc *II,
267 const MCInstrDesc *II,
268268 DenseMap &VRBaseMap,
269269 bool IsDebug, bool IsClone, bool IsCloned) {
270270 assert(Op.getValueType() != MVT::Other &&
274274 unsigned VReg = getVR(Op, VRBaseMap);
275275 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
276276
277 const TargetInstrDesc &TID = MI->getDesc();
278 bool isOptDef = IIOpNum < TID.getNumOperands() &&
279 TID.OpInfo[IIOpNum].isOptionalDef();
277 const MCInstrDesc &MCID = MI->getDesc();
278 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
279 MCID.OpInfo[IIOpNum].isOptionalDef();
280280
281281 // If the instruction requires a register in a different class, create
282282 // a new virtual register and copy the value into it.
285285 const TargetRegisterClass *DstRC = 0;
286286 if (IIOpNum < II->getNumOperands())
287287 DstRC = TII->getRegClass(*II, IIOpNum, TRI);
288 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
288 assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
289289 "Don't have operand info for this instruction!");
290290 if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) {
291291 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
311311 while (Idx > 0 &&
312312 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
313313 --Idx;
314 bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1;
314 bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
315315 if (isTied)
316316 isKill = false;
317317 }
329329 /// assertions only.
330330 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
331331 unsigned IIOpNum,
332 const TargetInstrDesc *II,
332 const MCInstrDesc *II,
333333 DenseMap &VRBaseMap,
334334 bool IsDebug, bool IsClone, bool IsCloned) {
335335 if (Op.isMachineOpcode()) {
555555 unsigned NumOps = Node->getNumOperands();
556556 assert((NumOps & 1) == 1 &&
557557 "REG_SEQUENCE must have an odd number of operands!");
558 const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
558 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
559559 for (unsigned i = 1; i != NumOps; ++i) {
560560 SDValue Op = Node->getOperand(i);
561561 if ((i & 1) == 0) {
596596 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
597597 }
598598 // Otherwise, we're going to create an instruction here.
599 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
599 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
600600 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
601601 if (SD->getKind() == SDDbgValue::SDNODE) {
602602 SDNode *Node = SD->getSDNode();
667667 // We want a unique VR for each IMPLICIT_DEF use.
668668 return;
669669
670 const TargetInstrDesc &II = TII->get(Opc);
670 const MCInstrDesc &II = TII->get(Opc);
671671 unsigned NumResults = CountResults(Node);
672672 unsigned NodeOperands = CountOperands(Node);
673673 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
696696 UsedRegs.push_back(cast(F->getOperand(1))->getReg());
697697 else {
698698 // Collect declared implicit uses.
699 const TargetInstrDesc &TID = TII->get(F->getMachineOpcode());
700 UsedRegs.append(TID.getImplicitUses(),
701 TID.getImplicitUses() + TID.getNumImplicitUses());
699 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
700 UsedRegs.append(MCID.getImplicitUses(),
701 MCID.getImplicitUses() + MCID.getNumImplicitUses());
702702 // In addition to declared implicit uses, we must also check for
703703 // direct RegisterSDNode operands.
704704 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
2121
2222 namespace llvm {
2323
24 class TargetInstrDesc;
24 class MCInstrDesc;
2525 class SDDbgValue;
2626
2727 class InstrEmitter {
4848 unsigned ResNo) const;
4949
5050 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
51 const TargetInstrDesc &II,
51 const MCInstrDesc &II,
5252 bool IsClone, bool IsCloned,
5353 DenseMap &VRBaseMap);
5454
6262 /// not in the required register class.
6363 void AddRegisterOperand(MachineInstr *MI, SDValue Op,
6464 unsigned IIOpNum,
65 const TargetInstrDesc *II,
65 const MCInstrDesc *II,
6666 DenseMap &VRBaseMap,
6767 bool IsDebug, bool IsClone, bool IsCloned);
6868
7272 /// assertions only.
7373 void AddOperand(MachineInstr *MI, SDValue Op,
7474 unsigned IIOpNum,
75 const TargetInstrDesc *II,
75 const MCInstrDesc *II,
7676 DenseMap &VRBaseMap,
7777 bool IsDebug, bool IsClone, bool IsCloned);
7878
248248 assert(N->getNodeId() == -1 && "Node already inserted!");
249249 N->setNodeId(NewSU->NodeNum);
250250
251 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
252 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
253 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
251 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
252 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
253 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
254254 NewSU->isTwoAddress = true;
255255 break;
256256 }
257257 }
258 if (TID.isCommutable())
258 if (MCID.isCommutable())
259259 NewSU->isCommutable = true;
260260
261261 // LoadNode may already exist. This can happen when there is another
421421 /// FIXME: Move to SelectionDAG?
422422 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
423423 const TargetInstrInfo *TII) {
424 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
425 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
426 unsigned NumRes = TID.getNumDefs();
427 for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
424 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
425 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
426 unsigned NumRes = MCID.getNumDefs();
427 for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
428428 if (Reg == *ImpDef)
429429 break;
430430 ++NumRes;
504504 }
505505 if (!Node->isMachineOpcode())
506506 continue;
507 const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode());
508 if (!TID.ImplicitDefs)
507 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
508 if (!MCID.ImplicitDefs)
509509 continue;
510 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
510 for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg) {
511511 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
512512 }
513513 }
301301 }
302302
303303 unsigned Idx = RegDefPos.GetIdx();
304 const TargetInstrDesc Desc = TII->get(Opcode);
304 const MCInstrDesc Desc = TII->get(Opcode);
305305 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI);
306306 RegClass = RC->getID();
307307 // FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a
836836 assert(N->getNodeId() == -1 && "Node already inserted!");
837837 N->setNodeId(NewSU->NodeNum);
838838
839 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
840 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
841 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
839 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
840 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
841 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
842842 NewSU->isTwoAddress = true;
843843 break;
844844 }
845845 }
846 if (TID.isCommutable())
846 if (MCID.isCommutable())
847847 NewSU->isCommutable = true;
848848
849849 InitNumRegDefsLeft(NewSU);
10231023 /// FIXME: Move to SelectionDAG?
10241024 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
10251025 const TargetInstrInfo *TII) {
1026 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
1027 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
1028 unsigned NumRes = TID.getNumDefs();
1029 for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
1026 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1027 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
1028 unsigned NumRes = MCID.getNumDefs();
1029 for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
10301030 if (Reg == *ImpDef)
10311031 break;
10321032 ++NumRes;
11071107
11081108 if (!Node->isMachineOpcode())
11091109 continue;
1110 const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode());
1111 if (!TID.ImplicitDefs)
1110 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
1111 if (!MCID.ImplicitDefs)
11121112 continue;
1113 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg)
1113 for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg)
11141114 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
11151115 }
11161116
26052605 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) {
26062606 if (SU->isTwoAddress) {
26072607 unsigned Opc = SU->getNode()->getMachineOpcode();
2608 const TargetInstrDesc &TID = TII->get(Opc);
2609 unsigned NumRes = TID.getNumDefs();
2610 unsigned NumOps = TID.getNumOperands() - NumRes;
2608 const MCInstrDesc &MCID = TII->get(Opc);
2609 unsigned NumRes = MCID.getNumDefs();
2610 unsigned NumOps = MCID.getNumOperands() - NumRes;
26112611 for (unsigned i = 0; i != NumOps; ++i) {
2612 if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
2612 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) {
26132613 SDNode *DU = SU->getNode()->getOperand(i).getNode();
26142614 if (DU->getNodeId() != -1 &&
26152615 Op->OrigNode == &(*SUnits)[DU->getNodeId()])
27892789
27902790 bool isLiveOut = hasOnlyLiveOutUses(SU);
27912791 unsigned Opc = Node->getMachineOpcode();
2792 const TargetInstrDesc &TID = TII->get(Opc);
2793 unsigned NumRes = TID.getNumDefs();
2794 unsigned NumOps = TID.getNumOperands() - NumRes;
2792 const MCInstrDesc &MCID = TII->get(Opc);
2793 unsigned NumRes = MCID.getNumDefs();
2794 unsigned NumOps = MCID.getNumOperands() - NumRes;
27952795 for (unsigned j = 0; j != NumOps; ++j) {
2796 if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
2796 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1)
27972797 continue;
27982798 SDNode *DU = SU->getNode()->getOperand(j).getNode();
27992799 if (DU->getNodeId() == -1)
110110
111111 unsigned ResNo = User->getOperand(2).getResNo();
112112 if (Def->isMachineOpcode()) {
113 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
113 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
114114 if (ResNo >= II.getNumDefs() &&
115115 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
116116 PhysReg = Reg;
254254 continue;
255255
256256 unsigned Opc = Node->getMachineOpcode();
257 const TargetInstrDesc &TID = TII->get(Opc);
258 if (TID.mayLoad())
257 const MCInstrDesc &MCID = TII->get(Opc);
258 if (MCID.mayLoad())
259259 // Cluster loads from "near" addresses into combined SUnits.
260260 ClusterNeighboringLoads(Node);
261261 }
389389
390390 if (MainNode->isMachineOpcode()) {
391391 unsigned Opc = MainNode->getMachineOpcode();
392 const TargetInstrDesc &TID = TII->get(Opc);
393 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
394 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
392 const MCInstrDesc &MCID = TII->get(Opc);
393 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
394 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
395395 SU->isTwoAddress = true;
396396 break;
397397 }
398398 }
399 if (TID.isCommutable())
399 if (MCID.isCommutable())
400400 SU->isCommutable = true;
401401 }
402402
353353 const MachineBasicBlock *MBB = I;
354354 for (MachineBasicBlock::const_iterator
355355 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
356 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
357
358 if ((TID.isCall() && !TID.isReturn()) ||
356 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
357
358 if ((MCID.isCall() && !MCID.isReturn()) ||
359359 II->isStackAligningInlineAsm()) {
360360 MFI->setHasCalls(true);
361361 goto done;
680680 // landing pad can thus be detected via the MachineModuleInfo.
681681 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
682682
683 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
683 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
684684 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
685685 .addSym(Label);
686686
26122612 if (EmitNodeInfo & OPFL_MemRefs) {
26132613 // Only attach load or store memory operands if the generated
26142614 // instruction may load or store.
2615 const TargetInstrDesc &TID = TM.getInstrInfo()->get(TargetOpc);
2616 bool mayLoad = TID.mayLoad();
2617 bool mayStore = TID.mayStore();
2615 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2616 bool mayLoad = MCID.mayLoad();
2617 bool mayStore = MCID.mayStore();
26182618
26192619 unsigned NumMemRefs = 0;
26202620 for (SmallVector::const_iterator I =
503503 bool FoundDef = false; // Not counting 2address def.
504504
505505 Uses.clear();
506 const TargetInstrDesc &TID = MII->getDesc();
506 const MCInstrDesc &MCID = MII->getDesc();
507507 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
508508 MachineOperand &MO = MII->getOperand(i);
509509 if (!MO.isReg())
520520 if (MO.getSubReg() || MII->isSubregToReg())
521521 return false;
522522
523 const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI);
523 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
524524 if (RC && !RC->contains(NewReg))
525525 return false;
526526
565565 SmallVector Uses;
566566 while (++MII != MBB->end()) {
567567 bool FoundKill = false;
568 const TargetInstrDesc &TID = MII->getDesc();
568 const MCInstrDesc &MCID = MII->getDesc();
569569 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
570570 MachineOperand &MO = MII->getOperand(i);
571571 if (!MO.isReg())
582582 if (MO.getSubReg())
583583 return false;
584584
585 const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI);
585 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
586586 if (RC && !RC->contains(NewReg))
587587 return false;
588588 if (MO.isKill())
528528
529529 bool hasIndirectBR = false;
530530 if (PreRegAlloc && !TailBB.empty()) {
531 const TargetInstrDesc &TID = TailBB.back().getDesc();
532 if (TID.isIndirectBranch()) {
531 const MCInstrDesc &MCID = TailBB.back().getDesc();
532 if (MCID.isIndirectBranch()) {
533533 MaxDuplicateCount = 20;
534534 hasIndirectBR = true;
535535 }
5858 // the two operands returned by findCommutedOpIndices.
5959 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
6060 bool NewMI) const {
61 const TargetInstrDesc &TID = MI->getDesc();
62 bool HasDef = TID.getNumDefs();
61 const MCInstrDesc &MCID = MI->getDesc();
62 bool HasDef = MCID.getNumDefs();
6363 if (HasDef && !MI->getOperand(0).isReg())
6464 // No idea how to commute this instruction. Target should implement its own.
6565 return 0;
8080 bool ChangeReg0 = false;
8181 if (HasDef && MI->getOperand(0).getReg() == Reg1) {
8282 // Must be two address instruction!
83 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
83 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
8484 "Expecting a two-address instruction!");
8585 Reg2IsKill = false;
8686 ChangeReg0 = true;
118118 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
119119 unsigned &SrcOpIdx1,
120120 unsigned &SrcOpIdx2) const {
121 const TargetInstrDesc &TID = MI->getDesc();
122 if (!TID.isCommutable())
121 const MCInstrDesc &MCID = MI->getDesc();
122 if (!MCID.isCommutable())
123123 return false;
124124 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
125125 // is not true, then the target must implement this.
126 SrcOpIdx1 = TID.getNumDefs();
126 SrcOpIdx1 = MCID.getNumDefs();
127127 SrcOpIdx2 = SrcOpIdx1 + 1;
128128 if (!MI->getOperand(SrcOpIdx1).isReg() ||
129129 !MI->getOperand(SrcOpIdx2).isReg())
136136 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
137137 const SmallVectorImpl &Pred) const {
138138 bool MadeChange = false;
139 const TargetInstrDesc &TID = MI->getDesc();
140 if (!TID.isPredicable())
139 const MCInstrDesc &MCID = MI->getDesc();
140 if (!MCID.isPredicable())
141141 return false;
142142
143143 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
144 if (TID.OpInfo[i].isPredicate()) {
144 if (MCID.OpInfo[i].isPredicate()) {
145145 MachineOperand &MO = MI->getOperand(i);
146146 if (MO.isReg()) {
147147 MO.setReg(Pred[j].getReg());
331331 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
332332 return true;
333333
334 const TargetInstrDesc &TID = MI->getDesc();
334 const MCInstrDesc &MCID = MI->getDesc();
335335
336336 // Avoid instructions obviously unsafe for remat.
337 if (TID.isNotDuplicable() || TID.mayStore() ||
337 if (MCID.isNotDuplicable() || MCID.mayStore() ||
338338 MI->hasUnmodeledSideEffects())
339339 return false;
340340
344344 return false;
345345
346346 // Avoid instructions which load from potentially varying memory.
347 if (TID.mayLoad() && !MI->isInvariantLoad(AA))
347 if (MCID.mayLoad() && !MI->isInvariantLoad(AA))
348348 return false;
349349
350350 // If any of the registers accessed are non-constant, conservatively assume
279279 /// isTwoAddrUse - Return true if the specified MI is using the specified
280280 /// register as a two-address operand.
281281 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
282 const TargetInstrDesc &TID = UseMI->getDesc();
283 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
282 const MCInstrDesc &MCID = UseMI->getDesc();
283 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
284284 MachineOperand &MO = UseMI->getOperand(i);
285285 if (MO.isReg() && MO.getReg() == Reg &&
286286 (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
442442 /// isTwoAddrUse - Return true if the specified MI uses the specified register
443443 /// as a two-address use. If so, return the destination register by reference.
444444 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
445 const TargetInstrDesc &TID = MI.getDesc();
446 unsigned NumOps = MI.isInlineAsm() ? MI.getNumOperands():TID.getNumOperands();
445 const MCInstrDesc &MCID = MI.getDesc();
446 unsigned NumOps = MI.isInlineAsm()
447 ? MI.getNumOperands() : MCID.getNumOperands();
447448 for (unsigned i = 0; i != NumOps; ++i) {
448449 const MachineOperand &MO = MI.getOperand(i);
449450 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
760761 static bool isSafeToDelete(MachineInstr *MI,
761762 const TargetInstrInfo *TII,
762763 SmallVector &Kills) {
763 const TargetInstrDesc &TID = MI->getDesc();
764 if (TID.mayStore() || TID.isCall())
764 const MCInstrDesc &MCID = MI->getDesc();
765 if (MCID.mayStore() || MCID.isCall())
765766 return false;
766 if (TID.isTerminator() || MI->hasUnmodeledSideEffects())
767 if (MCID.isTerminator() || MI->hasUnmodeledSideEffects())
767768 return false;
768769
769770 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
853854 MachineFunction::iterator &mbbi,
854855 unsigned SrcIdx, unsigned DstIdx, unsigned Dist,
855856 SmallPtrSet &Processed) {
856 const TargetInstrDesc &TID = mi->getDesc();
857 const MCInstrDesc &MCID = mi->getDesc();
857858 unsigned regA = mi->getOperand(DstIdx).getReg();
858859 unsigned regB = mi->getOperand(SrcIdx).getReg();
859860
875876 unsigned regCIdx = ~0U;
876877 bool TryCommute = false;
877878 bool AggressiveCommute = false;
878 if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
879 if (MCID.isCommutable() && mi->getNumOperands() >= 3 &&
879880 TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
880881 if (SrcIdx == SrcOp1)
881882 regCIdx = SrcOp2;
906907 if (TargetRegisterInfo::isVirtualRegister(regA))
907908 ScanUses(regA, &*mbbi, Processed);
908909
909 if (TID.isConvertibleTo3Addr()) {
910 if (MCID.isConvertibleTo3Addr()) {
910911 // This instruction is potentially convertible to a true
911912 // three-address instruction. Check if it is profitable.
912913 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
926927 // movq (%rax), %rcx
927928 // addq %rdx, %rcx
928929 // because it's preferable to schedule a load than a register copy.
929 if (TID.mayLoad() && !regBKilled) {
930 if (MCID.mayLoad() && !regBKilled) {
930931 // Determine if a load can be unfolded.
931932 unsigned LoadRegIndex;
932933 unsigned NewOpc =
935936 /*UnfoldStore=*/false,
936937 &LoadRegIndex);
937938 if (NewOpc != 0) {
938 const TargetInstrDesc &UnfoldTID = TII->get(NewOpc);
939 if (UnfoldTID.getNumDefs() == 1) {
939 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
940 if (UnfoldMCID.getNumDefs() == 1) {
940941 MachineFunction &MF = *mbbi->getParent();
941942
942943 // Unfold the load.
943944 DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi);
944945 const TargetRegisterClass *RC =
945 TII->getRegClass(UnfoldTID, LoadRegIndex, TRI);
946 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI);
946947 unsigned Reg = MRI->createVirtualRegister(RC);
947948 SmallVector NewMIs;
948949 if (!TII->unfoldMemoryOperand(MF, mi, Reg,
10661067 if (mi->isRegSequence())
10671068 RegSequences.push_back(&*mi);
10681069
1069 const TargetInstrDesc &TID = mi->getDesc();
1070 const MCInstrDesc &MCID = mi->getDesc();
10701071 bool FirstTied = true;
10711072
10721073 DistanceMap.insert(std::make_pair(mi, ++Dist));
10761077 // First scan through all the tied register uses in this instruction
10771078 // and record a list of pairs of tied operands for each register.
10781079 unsigned NumOps = mi->isInlineAsm()
1079 ? mi->getNumOperands() : TID.getNumOperands();
1080 ? mi->getNumOperands() : MCID.getNumOperands();
10801081 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
10811082 unsigned DstIdx = 0;
10821083 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
678678 VirtRegMap &VRM) {
679679 MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
680680 #ifndef NDEBUG
681 const TargetInstrDesc &TID = ReMatDefMI->getDesc();
682 assert(TID.getNumDefs() == 1 &&
681 const MCInstrDesc &MCID = ReMatDefMI->getDesc();
682 assert(MCID.getNumDefs() == 1 &&
683683 "Don't know how to remat instructions that define > 1 values!");
684684 #endif
685685 TII->reMaterialize(MBB, MII, DestReg, 0, ReMatDefMI, *TRI);
14821482 /// where SrcReg is r1 and it is tied to r0. Return true if after
14831483 /// commuting this instruction it will be r0 = op r2, r1.
14841484 static bool CommuteChangesDestination(MachineInstr *DefMI,
1485 const TargetInstrDesc &TID,
1485 const MCInstrDesc &MCID,
14861486 unsigned SrcReg,
14871487 const TargetInstrInfo *TII,
14881488 unsigned &DstIdx) {
1489 if (TID.getNumDefs() != 1 && TID.getNumOperands() != 3)
1489 if (MCID.getNumDefs() != 1 && MCID.getNumOperands() != 3)
14901490 return false;
14911491 if (!DefMI->getOperand(1).isReg() ||
14921492 DefMI->getOperand(1).getReg() != SrcReg)
15261526 MachineInstr &MI = *MII;
15271527 MachineBasicBlock::iterator DefMII = prior(MII);
15281528 MachineInstr *DefMI = DefMII;
1529 const TargetInstrDesc &TID = DefMI->getDesc();
1529 const MCInstrDesc &MCID = DefMI->getDesc();
15301530 unsigned NewDstIdx;
15311531 if (DefMII != MBB->begin() &&
1532 TID.isCommutable() &&
1533 CommuteChangesDestination(DefMI, TID, SrcReg, TII, NewDstIdx)) {
1532 MCID.isCommutable() &&
1533 CommuteChangesDestination(DefMI, MCID, SrcReg, TII, NewDstIdx)) {
15341534 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
15351535 unsigned NewReg = NewDstMO.getReg();
15361536 if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg))
16571657 /// isSafeToDelete - Return true if this instruction doesn't produce any side
16581658 /// effect and all of its defs are dead.
16591659 static bool isSafeToDelete(MachineInstr &MI) {
1660 const TargetInstrDesc &TID = MI.getDesc();
1661 if (TID.mayLoad() || TID.mayStore() || TID.isTerminator() ||
1662 TID.isCall() || TID.isBarrier() || TID.isReturn() ||
1660 const MCInstrDesc &MCID = MI.getDesc();
1661 if (MCID.mayLoad() || MCID.mayStore() || MCID.isTerminator() ||
1662 MCID.isCall() || MCID.isBarrier() || MCID.isReturn() ||
16631663 MI.isLabel() || MI.isDebugValue() ||
16641664 MI.hasUnmodeledSideEffects())
16651665 return false;
135135 MachineInstr *UpdateMI = NULL;
136136 MachineInstr *MemMI = NULL;
137137 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
138 const TargetInstrDesc &TID = MI->getDesc();
139 unsigned NumOps = TID.getNumOperands();
140 bool isLoad = !TID.mayStore();
138 const MCInstrDesc &MCID = MI->getDesc();
139 unsigned NumOps = MCID.getNumOperands();
140 bool isLoad = !MCID.mayStore();
141141 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
142142 const MachineOperand &Base = MI->getOperand(2);
143143 const MachineOperand &Offset = MI->getOperand(NumOps-3);
474474 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
475475 std::vector &Pred) const {
476476 // FIXME: This confuses implicit_def with optional CPSR def.
477 const TargetInstrDesc &TID = MI->getDesc();
478 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
477 const MCInstrDesc &MCID = MI->getDesc();
478 if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef())
479479 return false;
480480
481481 bool Found = false;
494494 /// By default, this returns true for every instruction with a
495495 /// PredicateOperand.
496496 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
497 const TargetInstrDesc &TID = MI->getDesc();
498 if (!TID.isPredicable())
499 return false;
500
501 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
497 const MCInstrDesc &MCID = MI->getDesc();
498 if (!MCID.isPredicable())
499 return false;
500
501 if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
502502 ARMFunctionInfo *AFI =
503503 MI->getParent()->getParent()->getInfo();
504504 return AFI->isThumb2Function();
524524 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
525525
526526 // Basic size info comes from the TSFlags field.
527 const TargetInstrDesc &TID = MI->getDesc();
528 uint64_t TSFlags = TID.TSFlags;
527 const MCInstrDesc &MCID = MI->getDesc();
528 uint64_t TSFlags = MCID.TSFlags;
529529
530530 unsigned Opc = MI->getOpcode();
531531 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
587587 // entry is one byte; TBH two byte each.
588588 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
589589 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
590 unsigned NumOps = TID.getNumOperands();
590 unsigned NumOps = MCID.getNumOperands();
591591 MachineOperand JTOP =
592 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
592 MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2));
593593 unsigned JTI = JTOP.getIndex();
594594 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
595595 assert(MJTI != 0);
13621362 unsigned FrameReg, int &Offset,
13631363 const ARMBaseInstrInfo &TII) {
13641364 unsigned Opcode = MI.getOpcode();
1365 const TargetInstrDesc &Desc = MI.getDesc();
1365 const MCInstrDesc &Desc = MI.getDesc();
13661366 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
13671367 bool isSub = false;
13681368
18021802 if (!ItinData || ItinData->isEmpty())
18031803 return 1;
18041804
1805 const TargetInstrDesc &Desc = MI->getDesc();
1805 const MCInstrDesc &Desc = MI->getDesc();
18061806 unsigned Class = Desc.getSchedClass();
18071807 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
18081808 if (UOps)
19051905
19061906 int
19071907 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
1908 const TargetInstrDesc &DefTID,
1908 const MCInstrDesc &DefMCID,
19091909 unsigned DefClass,
19101910 unsigned DefIdx, unsigned DefAlign) const {
1911 int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1911 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
19121912 if (RegNo <= 0)
19131913 // Def is the address writeback.
19141914 return ItinData->getOperandCycle(DefClass, DefIdx);
19231923 DefCycle = RegNo;
19241924 bool isSLoad = false;
19251925
1926 switch (DefTID.getOpcode()) {
1926 switch (DefMCID.getOpcode()) {
19271927 default: break;
19281928 case ARM::VLDMSIA:
19291929 case ARM::VLDMSIA_UPD:
19461946
19471947 int
19481948 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
1949 const TargetInstrDesc &DefTID,
1949 const MCInstrDesc &DefMCID,
19501950 unsigned DefClass,
19511951 unsigned DefIdx, unsigned DefAlign) const {
1952 int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1952 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
19531953 if (RegNo <= 0)
19541954 // Def is the address writeback.
19551955 return ItinData->getOperandCycle(DefClass, DefIdx);
19811981
19821982 int
19831983 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
1984 const TargetInstrDesc &UseTID,
1984 const MCInstrDesc &UseMCID,
19851985 unsigned UseClass,
19861986 unsigned UseIdx, unsigned UseAlign) const {
1987 int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
1987 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
19881988 if (RegNo <= 0)
19891989 return ItinData->getOperandCycle(UseClass, UseIdx);
19901990
19981998 UseCycle = RegNo;
19991999 bool isSStore = false;
20002000
2001 switch (UseTID.getOpcode()) {
2001 switch (UseMCID.getOpcode()) {
20022002 default: break;
20032003 case ARM::VSTMSIA:
20042004 case ARM::VSTMSIA_UPD:
20212021
20222022 int
20232023 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2024 const TargetInstrDesc &UseTID,
2024 const MCInstrDesc &UseMCID,
20252025 unsigned UseClass,
20262026 unsigned UseIdx, unsigned UseAlign) const {
2027 int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
2027 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
20282028 if (RegNo <= 0)
20292029 return ItinData->getOperandCycle(UseClass, UseIdx);
20302030
20502050
20512051 int
20522052 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2053 const TargetInstrDesc &DefTID,
2053 const MCInstrDesc &DefMCID,
20542054 unsigned DefIdx, unsigned DefAlign,
2055 const TargetInstrDesc &UseTID,
2055 const MCInstrDesc &UseMCID,
20562056 unsigned UseIdx, unsigned UseAlign) const {
2057 unsigned DefClass = DefTID.getSchedClass();
2058 unsigned UseClass = UseTID.getSchedClass();
2059
2060 if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands())
2057 unsigned DefClass = DefMCID.getSchedClass();
2058 unsigned UseClass = UseMCID.getSchedClass();
2059
2060 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
20612061 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
20622062
20632063 // This may be a def / use of a variable_ops instruction, the operand
20652065 // figure it out.
20662066 int DefCycle = -1;
20672067 bool LdmBypass = false;
2068 switch (DefTID.getOpcode()) {
2068 switch (DefMCID.getOpcode()) {
20692069 default:
20702070 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
20712071 break;
20762076 case ARM::VLDMSIA:
20772077 case ARM::VLDMSIA_UPD:
20782078 case ARM::VLDMSDB_UPD:
2079 DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
2079 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
20802080 break;
20812081
20822082 case ARM::LDMIA_RET:
20972097 case ARM::t2LDMIA_UPD:
20982098 case ARM::t2LDMDB_UPD:
20992099 LdmBypass = 1;
2100 DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
2100 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
21012101 break;
21022102 }
21032103
21062106 DefCycle = 2;
21072107
21082108 int UseCycle = -1;
2109 switch (UseTID.getOpcode()) {
2109 switch (UseMCID.getOpcode()) {
21102110 default:
21112111 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
21122112 break;
21172117 case ARM::VSTMSIA:
21182118 case ARM::VSTMSIA_UPD:
21192119 case ARM::VSTMSDB_UPD:
2120 UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
2120 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
21212121 break;
21222122
21232123 case ARM::STMIA:
21362136 case ARM::t2STMDB:
21372137 case ARM::t2STMIA_UPD:
21382138 case ARM::t2STMDB_UPD:
2139 UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
2139 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
21402140 break;
21412141 }
21422142
21492149 if (LdmBypass) {
21502150 // It's a variable_ops instruction so we can't use DefIdx here. Just use
21512151 // first def operand.
2152 if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1,
2152 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
21532153 UseClass, UseIdx))
21542154 --UseCycle;
21552155 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
21692169 DefMI->isRegSequence() || DefMI->isImplicitDef())
21702170 return 1;
21712171
2172 const TargetInstrDesc &DefTID = DefMI->getDesc();
2172 const MCInstrDesc &DefMCID = DefMI->getDesc();
21732173 if (!ItinData || ItinData->isEmpty())
2174 return DefTID.mayLoad() ? 3 : 1;
2175
2176 const TargetInstrDesc &UseTID = UseMI->getDesc();
2174 return DefMCID.mayLoad() ? 3 : 1;
2175
2176 const MCInstrDesc &UseMCID = UseMI->getDesc();
21772177 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
21782178 if (DefMO.getReg() == ARM::CPSR) {
21792179 if (DefMI->getOpcode() == ARM::FMSTAT) {
21822182 }
21832183
21842184 // CPSR set and branch can be paired in the same cycle.
2185 if (UseTID.isBranch())
2185 if (UseMCID.isBranch())
21862186 return 0;
21872187 }
21882188
21902190 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
21912191 unsigned UseAlign = UseMI->hasOneMemOperand()
21922192 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2193 int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
2194 UseTID, UseIdx, UseAlign);
2193 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2194 UseMCID, UseIdx, UseAlign);
21952195
21962196 if (Latency > 1 &&
21972197 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
21982198 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
21992199 // variants are one cycle cheaper.
2200 switch (DefTID.getOpcode()) {
2200 switch (DefMCID.getOpcode()) {
22012201 default: break;
22022202 case ARM::LDRrs:
22032203 case ARM::LDRBrs: {
22222222 }
22232223
22242224 if (DefAlign < 8 && Subtarget.isCortexA9())
2225 switch (DefTID.getOpcode()) {
2225 switch (DefMCID.getOpcode()) {
22262226 default: break;
22272227 case ARM::VLD1q8:
22282228 case ARM::VLD1q16:
23262326 if (!DefNode->isMachineOpcode())
23272327 return 1;
23282328
2329 const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode());
2330
2331 if (isZeroCost(DefTID.Opcode))
2329 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2330
2331 if (isZeroCost(DefMCID.Opcode))
23322332 return 0;
23332333
23342334 if (!ItinData || ItinData->isEmpty())
2335 return DefTID.mayLoad() ? 3 : 1;
2335 return DefMCID.mayLoad() ? 3 : 1;
23362336
23372337 if (!UseNode->isMachineOpcode()) {
2338 int Latency = ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx);
2338 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
23392339 if (Subtarget.isCortexA9())
23402340 return Latency <= 2 ? 1 : Latency - 1;
23412341 else
23422342 return Latency <= 3 ? 1 : Latency - 2;
23432343 }
23442344
2345 const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode());
2345 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
23462346 const MachineSDNode *DefMN = dyn_cast(DefNode);
23472347 unsigned DefAlign = !DefMN->memoperands_empty()
23482348 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
23492349 const MachineSDNode *UseMN = dyn_cast(UseNode);
23502350 unsigned UseAlign = !UseMN->memoperands_empty()
23512351 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2352 int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
2353 UseTID, UseIdx, UseAlign);
2352 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2353 UseMCID, UseIdx, UseAlign);
23542354
23552355 if (Latency > 1 &&
23562356 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
23572357 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
23582358 // variants are one cycle cheaper.
2359 switch (DefTID.getOpcode()) {
2359 switch (DefMCID.getOpcode()) {
23602360 default: break;
23612361 case ARM::LDRrs:
23622362 case ARM::LDRBrs: {
23832383 }
23842384
23852385 if (DefAlign < 8 && Subtarget.isCortexA9())
2386 switch (DefTID.getOpcode()) {
2386 switch (DefMCID.getOpcode()) {
23872387 default: break;
23882388 case ARM::VLD1q8Pseudo:
23892389 case ARM::VLD1q16Pseudo:
25022502 if (!ItinData || ItinData->isEmpty())
25032503 return 1;
25042504
2505 const TargetInstrDesc &TID = MI->getDesc();
2506 unsigned Class = TID.getSchedClass();
2505 const MCInstrDesc &MCID = MI->getDesc();
2506 unsigned Class = MCID.getSchedClass();
25072507 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2508 if (PredCost && TID.hasImplicitDefOfPhysReg(ARM::CPSR))
2508 if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR))
25092509 // When predicated, CPSR is an additional source operand for CPSR updating
25102510 // instructions, this apparently increases their latencies.
25112511 *PredCost = 1;
352352 SDNode *UseNode, unsigned UseIdx) const;
353353 private:
354354 int getVLDMDefCycle(const InstrItineraryData *ItinData,
355 const TargetInstrDesc &DefTID,
355 const MCInstrDesc &DefMCID,
356356 unsigned DefClass,
357357 unsigned DefIdx, unsigned DefAlign) const;
358358 int getLDMDefCycle(const InstrItineraryData *ItinData,
359 const TargetInstrDesc &DefTID,
359 const MCInstrDesc &DefMCID,
360360 unsigned DefClass,
361361 unsigned DefIdx, unsigned DefAlign) const;
362362 int getVSTMUseCycle(const InstrItineraryData *ItinData,
363 const TargetInstrDesc &UseTID,
363 const MCInstrDesc &UseMCID,
364364 unsigned UseClass,
365365 unsigned UseIdx, unsigned UseAlign) const;
366366 int getSTMUseCycle(const InstrItineraryData *ItinData,
367 const TargetInstrDesc &UseTID,
367 const MCInstrDesc &UseMCID,
368368 unsigned UseClass,
369369 unsigned UseIdx, unsigned UseAlign) const;
370370 int getOperandLatency(const InstrItineraryData *ItinData,
371 const TargetInstrDesc &DefTID,
371 const MCInstrDesc &DefMCID,
372372 unsigned DefIdx, unsigned DefAlign,
373 const Target