llvm.org GIT mirror llvm / e82f691
AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.compr Patch by Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326479 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
2 changed file(s) with 83 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
285285 break;
286286 }
287287 case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
288 unsigned IntrinsicID = MI.getOperand(0).getIntrinsicID();
289 switch (IntrinsicID) {
290 case Intrinsic::amdgcn_exp: {
288 switch (MI.getOperand(0).getIntrinsicID()) {
289 default:
290 return getInvalidInstructionMapping();
291 case Intrinsic::amdgcn_exp_compr:
292 OpdsMapping[0] = nullptr; // IntrinsicID
293 // FIXME: These are immediate values which can't be read from registers.
294 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
295 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
296 // FIXME: Could we support packed types here?
297 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
298 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
299 // FIXME: These are immediate values which can't be read from registers.
300 OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
301 OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
302 break;
303 case Intrinsic::amdgcn_exp:
291304 OpdsMapping[0] = nullptr; // IntrinsicID
292305 // FIXME: These are immediate values which can't be read from registers.
293306 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
302315 OpdsMapping[8] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
303316 break;
304317 }
305 }
306318 break;
307319 }
308320 case AMDGPU::G_LOAD:
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
3
4 --- |
5 define void @exp_compr_v2f16_s() {
6 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> , <2 x half> , i1 0, i1 0)
7 ret void
8 }
9 define void @exp_compr_v2f16_v() {
10 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> , <2 x half> , i1 0, i1 0)
11 ret void
12 }
13
14 declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1)
15 declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1)
16
17 ...
18
19 ---
20 name: exp_compr_v2f16_s
21 legalized: true
22
23 body: |
24 bb.0:
25 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
26 ; CHECK-LABEL: name: exp_compr_v2f16_s
27 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
28 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
29 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
30 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
31 ; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
32 ; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
33 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
34 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
35 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[C2]](s1), [[C3]](s1)
36 %0:_(s32) = G_CONSTANT i32 0
37 %1:_(s32) = G_CONSTANT i32 0
38 %2:_(s32) = COPY $sgpr0
39 %3:_(s32) = COPY $sgpr1
40 %6:_(s1) = G_CONSTANT i1 0
41 %7:_(s1) = G_CONSTANT i1 0
42 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7
43 ...
44 ---
45 name: exp_compr_v2f16_v
46 legalized: true
47
48 body: |
49 bb.0:
50 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
51 ; CHECK-LABEL: name: exp_compr_v2f16_v
52 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
53 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
54 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
55 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
56 ; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
57 ; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
58 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY]](s32), [[COPY1]](s32), [[C2]](s1), [[C3]](s1)
59 %0:_(s32) = G_CONSTANT i32 0
60 %1:_(s32) = G_CONSTANT i32 0
61 %2:_(s32) = COPY $vgpr0
62 %3:_(s32) = COPY $vgpr1
63 %6:_(s1) = G_CONSTANT i1 0
64 %7:_(s1) = G_CONSTANT i1 0
65 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7
66 ...