llvm.org GIT mirror llvm / e7ef041
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205986 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 6 years ago
4 changed file(s) with 9263 addition(s) and 448 deletion(s). Raw diff Collapse all Expand all
990990 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
991991 }
992992
993 // Base class for addrmode6 with specific alignment restrictions.
994 class AddrMode6Align : Operand,
995 ComplexPattern{
996 let PrintMethod = "printAddrMode6Operand";
997 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
998 let EncoderMethod = "getAddrMode6AddressOpValue";
999 let DecoderMethod = "DecodeAddrMode6Operand";
1000 }
1001
1002 // Special version of addrmode6 to handle no allowed alignment encoding for
1003 // VLD/VST instructions and checking the alignment is not specified.
1004 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1005 let Name = "AlignedMemoryNone";
1006 let DiagnosticType = "AlignedMemoryRequiresNone";
1007 }
1008 def addrmode6alignNone : AddrMode6Align {
1009 // The alignment specifier can only be omitted.
1010 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1011 }
1012
1013 // Special version of addrmode6 to handle 16-bit alignment encoding for
1014 // VLD/VST instructions and checking the alignment value.
1015 def AddrMode6Align16AsmOperand : AsmOperandClass {
1016 let Name = "AlignedMemory16";
1017 let DiagnosticType = "AlignedMemoryRequires16";
1018 }
1019 def addrmode6align16 : AddrMode6Align {
1020 // The alignment specifier can only be 16 or omitted.
1021 let ParserMatchClass = AddrMode6Align16AsmOperand;
1022 }
1023
1024 // Special version of addrmode6 to handle 32-bit alignment encoding for
1025 // VLD/VST instructions and checking the alignment value.
1026 def AddrMode6Align32AsmOperand : AsmOperandClass {
1027 let Name = "AlignedMemory32";
1028 let DiagnosticType = "AlignedMemoryRequires32";
1029 }
1030 def addrmode6align32 : AddrMode6Align {
1031 // The alignment specifier can only be 32 or omitted.
1032 let ParserMatchClass = AddrMode6Align32AsmOperand;
1033 }
1034
1035 // Special version of addrmode6 to handle 64-bit alignment encoding for
1036 // VLD/VST instructions and checking the alignment value.
1037 def AddrMode6Align64AsmOperand : AsmOperandClass {
1038 let Name = "AlignedMemory64";
1039 let DiagnosticType = "AlignedMemoryRequires64";
1040 }
1041 def addrmode6align64 : AddrMode6Align {
1042 // The alignment specifier can only be 64 or omitted.
1043 let ParserMatchClass = AddrMode6Align64AsmOperand;
1044 }
1045
1046 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1047 // for VLD/VST instructions and checking the alignment value.
1048 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1049 let Name = "AlignedMemory64or128";
1050 let DiagnosticType = "AlignedMemoryRequires64or128";
1051 }
1052 def addrmode6align64or128 : AddrMode6Align {
1053 // The alignment specifier can only be 64, 128 or omitted.
1054 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1055 }
1056
1057 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1058 // encoding for VLD/VST instructions and checking the alignment value.
1059 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1060 let Name = "AlignedMemory64or128or256";
1061 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1062 }
1063 def addrmode6align64or128or256 : AddrMode6Align {
1064 // The alignment specifier can only be 64, 128, 256 or omitted.
1065 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1066 }
1067
9931068 // Special version of addrmode6 to handle alignment encoding for VLD-dup
9941069 // instructions, specifically VLD4-dup.
9951070 def addrmode6dup : Operand,
10001075 // FIXME: This is close, but not quite right. The alignment specifier is
10011076 // different.
10021077 let ParserMatchClass = AddrMode6AsmOperand;
1078 }
1079
1080 // Base class for addrmode6dup with specific alignment restrictions.
1081 class AddrMode6DupAlign : Operand,
1082 ComplexPattern{
1083 let PrintMethod = "printAddrMode6Operand";
1084 let MIOperandInfo = (ops GPR:$addr, i32imm);
1085 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1086 }
1087
1088 // Special version of addrmode6 to handle no allowed alignment encoding for
1089 // VLD-dup instruction and checking the alignment is not specified.
1090 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1091 let Name = "DupAlignedMemoryNone";
1092 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1093 }
1094 def addrmode6dupalignNone : AddrMode6DupAlign {
1095 // The alignment specifier can only be omitted.
1096 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1097 }
1098
1099 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1100 // instruction and checking the alignment value.
1101 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1102 let Name = "DupAlignedMemory16";
1103 let DiagnosticType = "DupAlignedMemoryRequires16";
1104 }
1105 def addrmode6dupalign16 : AddrMode6DupAlign {
1106 // The alignment specifier can only be 16 or omitted.
1107 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1108 }
1109
1110 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1111 // instruction and checking the alignment value.
1112 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1113 let Name = "DupAlignedMemory32";
1114 let DiagnosticType = "DupAlignedMemoryRequires32";
1115 }
1116 def addrmode6dupalign32 : AddrMode6DupAlign {
1117 // The alignment specifier can only be 32 or omitted.
1118 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1119 }
1120
1121 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1122 // instructions and checking the alignment value.
1123 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1124 let Name = "DupAlignedMemory64";
1125 let DiagnosticType = "DupAlignedMemoryRequires64";
1126 }
1127 def addrmode6dupalign64 : AddrMode6DupAlign {
1128 // The alignment specifier can only be 64 or omitted.
1129 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1130 }
1131
1132 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1133 // for VLD instructions and checking the alignment value.
1134 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1135 let Name = "DupAlignedMemory64or128";
1136 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1137 }
1138 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1139 // The alignment specifier can only be 64, 128 or omitted.
1140 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
10031141 }
10041142
10051143 // addrmodepc := pc + reg
616616 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
617617
618618 // VLD1 : Vector Load (multiple single elements)
619 class VLD1D op7_4, string Dt>
619 class VLD1D op7_4, string Dt, Operand AddrMode>
620620 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
621 (ins addrmode6:$Rn), IIC_VLD1,
621 (ins AddrMode:$Rn), IIC_VLD1,
622622 "vld1", Dt, "$Vd, $Rn", "", []> {
623623 let Rm = 0b1111;
624624 let Inst{4} = Rn{4};
625625 let DecoderMethod = "DecodeVLDST1Instruction";
626626 }
627 class VLD1Q op7_4, string Dt>
627 class VLD1Q op7_4, string Dt, Operand AddrMode>
628628 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
629 (ins addrmode6:$Rn), IIC_VLD1x2,
629 (ins AddrMode:$Rn), IIC_VLD1x2,
630630 "vld1", Dt, "$Vd, $Rn", "", []> {
631631 let Rm = 0b1111;
632632 let Inst{5-4} = Rn{5-4};
633633 let DecoderMethod = "DecodeVLDST1Instruction";
634634 }
635635
636 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
637 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
638 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
639 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
640
641 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
642 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
643 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
644 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
636 def VLD1d8 : VLD1D<{0,0,0,?}, "8", addrmode6align64>;
637 def VLD1d16 : VLD1D<{0,1,0,?}, "16", addrmode6align64>;
638 def VLD1d32 : VLD1D<{1,0,0,?}, "32", addrmode6align64>;
639 def VLD1d64 : VLD1D<{1,1,0,?}, "64", addrmode6align64>;
640
641 def VLD1q8 : VLD1Q<{0,0,?,?}, "8", addrmode6align64or128>;
642 def VLD1q16 : VLD1Q<{0,1,?,?}, "16", addrmode6align64or128>;
643 def VLD1q32 : VLD1Q<{1,0,?,?}, "32", addrmode6align64or128>;
644 def VLD1q64 : VLD1Q<{1,1,?,?}, "64", addrmode6align64or128>;
645645
646646 // ...with address register writeback:
647 multiclass VLD1DWB op7_4, string Dt> {
647 multiclass VLD1DWB op7_4, string Dt, Operand AddrMode> {
648648 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
649 (ins addrmode6:$Rn), IIC_VLD1u,
649 (ins AddrMode:$Rn), IIC_VLD1u,
650650 "vld1", Dt, "$Vd, $Rn!",
651651 "$Rn.addr = $wb", []> {
652652 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
654654 let DecoderMethod = "DecodeVLDST1Instruction";
655655 }
656656 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
657 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
657 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
658658 "vld1", Dt, "$Vd, $Rn, $Rm",
659659 "$Rn.addr = $wb", []> {
660660 let Inst{4} = Rn{4};
661661 let DecoderMethod = "DecodeVLDST1Instruction";
662662 }
663663 }
664 multiclass VLD1QWB op7_4, string Dt> {
664 multiclass VLD1QWB op7_4, string Dt, Operand AddrMode> {
665665 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
666 (ins addrmode6:$Rn), IIC_VLD1x2u,
666 (ins AddrMode:$Rn), IIC_VLD1x2u,
667667 "vld1", Dt, "$Vd, $Rn!",
668668 "$Rn.addr = $wb", []> {
669669 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
671671 let DecoderMethod = "DecodeVLDST1Instruction";
672672 }
673673 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
674 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
674 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
675675 "vld1", Dt, "$Vd, $Rn, $Rm",
676676 "$Rn.addr = $wb", []> {
677677 let Inst{5-4} = Rn{5-4};
679679 }
680680 }
681681
682 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
683 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
684 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
685 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
686 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
687 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
688 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
689 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
682 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8", addrmode6align64>;
683 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16", addrmode6align64>;
684 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32", addrmode6align64>;
685 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64", addrmode6align64>;
686 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
687 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
688 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
689 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
690690
691691 // ...with 3 registers
692 class VLD1D3 op7_4, string Dt>
692 class VLD1D3 op7_4, string Dt, Operand AddrMode>
693693 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
694 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
694 (ins AddrMode:$Rn), IIC_VLD1x3, "vld1", Dt,
695695 "$Vd, $Rn", "", []> {
696696 let Rm = 0b1111;
697697 let Inst{4} = Rn{4};
698698 let DecoderMethod = "DecodeVLDST1Instruction";
699699 }
700 multiclass VLD1D3WB op7_4, string Dt> {
700 multiclass VLD1D3WB op7_4, string Dt, Operand AddrMode> {
701701 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
702 (ins addrmode6:$Rn), IIC_VLD1x2u,
702 (ins AddrMode:$Rn), IIC_VLD1x2u,
703703 "vld1", Dt, "$Vd, $Rn!",
704704 "$Rn.addr = $wb", []> {
705705 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
707707 let DecoderMethod = "DecodeVLDST1Instruction";
708708 }
709709 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
710 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
710 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
711711 "vld1", Dt, "$Vd, $Rn, $Rm",
712712 "$Rn.addr = $wb", []> {
713713 let Inst{4} = Rn{4};
715715 }
716716 }
717717
718 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
719 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
720 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
721 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
722
723 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
724 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
725 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
726 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
718 def VLD1d8T : VLD1D3<{0,0,0,?}, "8", addrmode6align64>;
719 def VLD1d16T : VLD1D3<{0,1,0,?}, "16", addrmode6align64>;
720 def VLD1d32T : VLD1D3<{1,0,0,?}, "32", addrmode6align64>;
721 def VLD1d64T : VLD1D3<{1,1,0,?}, "64", addrmode6align64>;
722
723 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8", addrmode6align64>;
724 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16", addrmode6align64>;
725 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32", addrmode6align64>;
726 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64", addrmode6align64>;
727727
728728 def VLD1d64TPseudo : VLDQQPseudo;
729729 def VLD1d64TPseudoWB_fixed : VLDQQWBfixedPseudo;
730730 def VLD1d64TPseudoWB_register : VLDQQWBregisterPseudo;
731731
732732 // ...with 4 registers
733 class VLD1D4 op7_4, string Dt>
733 class VLD1D4 op7_4, string Dt, Operand AddrMode>
734734 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
735 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
735 (ins AddrMode:$Rn), IIC_VLD1x4, "vld1", Dt,
736736 "$Vd, $Rn", "", []> {
737737 let Rm = 0b1111;
738738 let Inst{5-4} = Rn{5-4};
739739 let DecoderMethod = "DecodeVLDST1Instruction";
740740 }
741 multiclass VLD1D4WB op7_4, string Dt> {
741 multiclass VLD1D4WB op7_4, string Dt, Operand AddrMode> {
742742 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
743 (ins addrmode6:$Rn), IIC_VLD1x2u,
743 (ins AddrMode:$Rn), IIC_VLD1x2u,
744744 "vld1", Dt, "$Vd, $Rn!",
745745 "$Rn.addr = $wb", []> {
746746 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
748748 let DecoderMethod = "DecodeVLDST1Instruction";
749749 }
750750 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
751 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
751 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
752752 "vld1", Dt, "$Vd, $Rn, $Rm",
753753 "$Rn.addr = $wb", []> {
754754 let Inst{5-4} = Rn{5-4};
756756 }
757757 }
758758
759 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
760 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
761 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
762 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
763
764 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
765 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
766 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
767 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
759 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
760 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
761 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
762 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
763
764 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
765 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
766 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
767 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
768768
769769 def VLD1d64QPseudo : VLDQQPseudo;
770770 def VLD1d64QPseudoWB_fixed : VLDQQWBfixedPseudo;
772772
773773 // VLD2 : Vector Load (multiple 2-element structures)
774774 class VLD2 op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
775 InstrItinClass itin>
775 InstrItinClass itin, Operand AddrMode>
776776 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
777 (ins addrmode6:$Rn), itin,
777 (ins AddrMode:$Rn), itin,
778778 "vld2", Dt, "$Vd, $Rn", "", []> {
779779 let Rm = 0b1111;
780780 let Inst{5-4} = Rn{5-4};
781781 let DecoderMethod = "DecodeVLDST2Instruction";
782782 }
783783
784 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
785 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;
786 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;
787
788 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
789 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
790 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
784 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2,
785 addrmode6align64or128>;
786 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2,
787 addrmode6align64or128>;
788 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2,
789 addrmode6align64or128>;
790
791 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
792 addrmode6align64or128or256>;
793 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
794 addrmode6align64or128or256>;
795 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
796 addrmode6align64or128or256>;
791797
792798 def VLD2q8Pseudo : VLDQQPseudo;
793799 def VLD2q16Pseudo : VLDQQPseudo;
795801
796802 // ...with address register writeback:
797803 multiclass VLD2WB op11_8, bits<4> op7_4, string Dt,
798 RegisterOperand VdTy, InstrItinClass itin> {
804 RegisterOperand VdTy, InstrItinClass itin, Operand AddrMode> {
799805 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
800 (ins addrmode6:$Rn), itin,
806 (ins AddrMode:$Rn), itin,
801807 "vld2", Dt, "$Vd, $Rn!",
802808 "$Rn.addr = $wb", []> {
803809 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
805811 let DecoderMethod = "DecodeVLDST2Instruction";
806812 }
807813 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
808 (ins addrmode6:$Rn, rGPR:$Rm), itin,
814 (ins AddrMode:$Rn, rGPR:$Rm), itin,
809815 "vld2", Dt, "$Vd, $Rn, $Rm",
810816 "$Rn.addr = $wb", []> {
811817 let Inst{5-4} = Rn{5-4};
813819 }
814820 }
815821
816 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;
817 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;
818 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;
819
820 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
821 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
822 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
822 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u,
823 addrmode6align64or128>;
824 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u,
825 addrmode6align64or128>;
826 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u,
827 addrmode6align64or128>;
828
829 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
830 addrmode6align64or128or256>;
831 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
832 addrmode6align64or128or256>;
833 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
834 addrmode6align64or128or256>;
823835
824836 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo;
825837 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo;
829841 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo;
830842
831843 // ...with double-spaced registers
832 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
833 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
834 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
835 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
836 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
837 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
844 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2,
845 addrmode6align64or128>;
846 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,
847 addrmode6align64or128>;
848 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,
849 addrmode6align64or128>;
850 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u,
851 addrmode6align64or128>;
852 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,
853 addrmode6align64or128>;
854 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,
855 addrmode6align64or128>;
838856
839857 // VLD3 : Vector Load (multiple 3-element structures)
840858 class VLD3D op11_8, bits<4> op7_4, string Dt>
12921310 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
12931311
12941312 // VLD1DUP : Vector Load (single element to all lanes)
1295 class VLD1DUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1313 class VLD1DUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1314 Operand AddrMode>
12961315 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1297 (ins addrmode6dup:$Rn),
1316 (ins AddrMode:$Rn),
12981317 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
12991318 [(set VecListOneDAllLanes:$Vd,
1300 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1319 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
13011320 let Rm = 0b1111;
13021321 let Inst{4} = Rn{4};
13031322 let DecoderMethod = "DecodeVLD1DupInstruction";
13041323 }
1305 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1306 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1307 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1324 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8,
1325 addrmode6dupalignNone>;
1326 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16,
1327 addrmode6dupalign16>;
1328 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,
1329 addrmode6dupalign32>;
13081330
13091331 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
13101332 (VLD1DUPd32 addrmode6:$addr)>;
13111333
1312 class VLD1QDUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1334 class VLD1QDUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1335 Operand AddrMode>
13131336 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1314 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1337 (ins AddrMode:$Rn), IIC_VLD1dup,
13151338 "vld1", Dt, "$Vd, $Rn", "",
13161339 [(set VecListDPairAllLanes:$Vd,
1317 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1340 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
13181341 let Rm = 0b1111;
13191342 let Inst{4} = Rn{4};
13201343 let DecoderMethod = "DecodeVLD1DupInstruction";
13211344 }
13221345
1323 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1324 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1325 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
1346 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8,
1347 addrmode6dupalignNone>;
1348 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16,
1349 addrmode6dupalign16>;
1350 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
1351 addrmode6dupalign32>;
13261352
13271353 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
13281354 (VLD1DUPq32 addrmode6:$addr)>;
13291355
13301356 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
13311357 // ...with address register writeback:
1332 multiclass VLD1DUPWB op7_4, string Dt> {
1358 multiclass VLD1DUPWB op7_4, string Dt, Operand AddrMode> {
13331359 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
13341360 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1335 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1361 (ins AddrMode:$Rn), IIC_VLD1dupu,
13361362 "vld1", Dt, "$Vd, $Rn!",
13371363 "$Rn.addr = $wb", []> {
13381364 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
13411367 }
13421368 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
13431369 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1344 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1370 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
13451371 "vld1", Dt, "$Vd, $Rn, $Rm",
13461372 "$Rn.addr = $wb", []> {
13471373 let Inst{4} = Rn{4};
13481374 let DecoderMethod = "DecodeVLD1DupInstruction";
13491375 }
13501376 }
1351 multiclass VLD1QDUPWB op7_4, string Dt> {
1377 multiclass VLD1QDUPWB op7_4, string Dt, Operand AddrMode> {
13521378 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
13531379 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1354 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1380 (ins AddrMode:$Rn), IIC_VLD1dupu,
13551381 "vld1", Dt, "$Vd, $Rn!",
13561382 "$Rn.addr = $wb", []> {
13571383 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
13601386 }
13611387 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
13621388 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1363 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1389 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
13641390 "vld1", Dt, "$Vd, $Rn, $Rm",
13651391 "$Rn.addr = $wb", []> {
13661392 let Inst{4} = Rn{4};
13681394 }
13691395 }
13701396
1371 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1372 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1373 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1374
1375 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1376 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1377 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1397 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8", addrmode6dupalignNone>;
1398 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16", addrmode6dupalign16>;
1399 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32", addrmode6dupalign32>;
1400
1401 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8", addrmode6dupalignNone>;
1402 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16", addrmode6dupalign16>;
1403 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32", addrmode6dupalign32>;
13781404
13791405 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1380 class VLD2DUP op7_4, string Dt, RegisterOperand VdTy>
1406 class VLD2DUP op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
13811407 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1382 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1408 (ins AddrMode:$Rn), IIC_VLD2dup,
13831409 "vld2", Dt, "$Vd, $Rn", "", []> {
13841410 let Rm = 0b1111;
13851411 let Inst{4} = Rn{4};
13861412 let DecoderMethod = "DecodeVLD2DupInstruction";
13871413 }
13881414
1389 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;
1390 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
1391 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
1392
1415 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1416 addrmode6dupalign16>;
1417 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1418 addrmode6dupalign32>;
1419 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1420 addrmode6dupalign64>;
1421
1422 // HACK this one, VLD2DUPd8x2 must be changed at the same time with VLD2b8 or
1423 // "vld2.8 {d0[], d2[]}, [r4:32]" will become "vld2.8 {d0, d2}, [r4:32]".
13931424 // ...with double-spaced registers
1394 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;
1395 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1396 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1425 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1426 addrmode6dupalign16>;
1427 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1428 addrmode6dupalign32>;
1429 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1430 addrmode6dupalign64>;
13971431
13981432 // ...with address register writeback:
1399 multiclass VLD2DUPWB op7_4, string Dt, RegisterOperand VdTy> {
1433 multiclass VLD2DUPWB op7_4, string Dt, RegisterOperand VdTy,
1434 Operand AddrMode> {
14001435 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
14011436 (outs VdTy:$Vd, GPR:$wb),
1402 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
1437 (ins AddrMode:$Rn), IIC_VLD2dupu,
14031438 "vld2", Dt, "$Vd, $Rn!",
14041439 "$Rn.addr = $wb", []> {
14051440 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
14081443 }
14091444 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
14101445 (outs VdTy:$Vd, GPR:$wb),
1411 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1446 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD2dupu,
14121447 "vld2", Dt, "$Vd, $Rn, $Rm",
14131448 "$Rn.addr = $wb", []> {
14141449 let Inst{4} = Rn{4};
14161451 }
14171452 }
14181453
1419 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;
1420 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
1421 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
1422
1423 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;
1424 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1425 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1454 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes,
1455 addrmode6dupalign16>;
1456 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes,
1457 addrmode6dupalign32>;
1458 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes,
1459 addrmode6dupalign64>;
1460
1461 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes,
1462 addrmode6dupalign16>;
1463 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1464 addrmode6dupalign32>;
1465 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1466 addrmode6dupalign64>;
14261467
14271468 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
14281469 class VLD3DUP op7_4, string Dt>
14481489 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
14491490
14501491 // ...with address register writeback:
1451 class VLD3DUPWB op7_4, string Dt>
1492 class VLD3DUPWB op7_4, string Dt, Operand AddrMode>
14521493 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1453 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1494 (ins AddrMode:$Rn, am6offset:$Rm), IIC_VLD3dupu,
14541495 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
14551496 "$Rn.addr = $wb", []> {
14561497 let Inst{4} = 0;
14571498 let DecoderMethod = "DecodeVLD3DupInstruction";
14581499 }
14591500
1460 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1461 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1462 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1463
1464 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1465 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1466 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1501 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8", addrmode6dupalign64>;
1502 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16", addrmode6dupalign64>;
1503 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32", addrmode6dupalign64>;
1504
1505 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8", addrmode6dupalign64>;
1506 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16", addrmode6dupalign64>;
1507 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32", addrmode6dupalign64>;
14671508
14681509 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo;
14691510 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo;
15591600 "$addr.addr = $wb">;
15601601
15611602 // VST1 : Vector Store (multiple single elements)
1562 class VST1D op7_4, string Dt>
1563 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1603 class VST1D op7_4, string Dt, Operand AddrMode>
1604 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
15641605 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
15651606 let Rm = 0b1111;
15661607 let Inst{4} = Rn{4};
15671608 let DecoderMethod = "DecodeVLDST1Instruction";
15681609 }
1569 class VST1Q op7_4, string Dt>
1570 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
1610 class VST1Q op7_4, string Dt, Operand AddrMode>
1611 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
15711612 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
15721613 let Rm = 0b1111;
15731614 let Inst{5-4} = Rn{5-4};
15741615 let DecoderMethod = "DecodeVLDST1Instruction";
15751616 }
15761617
1577 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1578 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1579 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1580 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1581
1582 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1583 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1584 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1585 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1618 def VST1d8 : VST1D<{0,0,0,?}, "8", addrmode6align64>;
1619 def VST1d16 : VST1D<{0,1,0,?}, "16", addrmode6align64>;
1620 def VST1d32 : VST1D<{1,0,0,?}, "32", addrmode6align64>;
1621 def VST1d64 : VST1D<{1,1,0,?}, "64", addrmode6align64>;
1622
1623 def VST1q8 : VST1Q<{0,0,?,?}, "8", addrmode6align64or128>;
1624 def VST1q16 : VST1Q<{0,1,?,?}, "16", addrmode6align64or128>;
1625 def VST1q32 : VST1Q<{1,0,?,?}, "32", addrmode6align64or128>;
1626 def VST1q64 : VST1Q<{1,1,?,?}, "64", addrmode6align64or128>;
15861627
15871628 // ...with address register writeback:
1588 multiclass VST1DWB op7_4, string Dt> {
1629 multiclass VST1DWB op7_4, string Dt, Operand AddrMode> {
15891630 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1590 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1631 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
15911632 "vst1", Dt, "$Vd, $Rn!",
15921633 "$Rn.addr = $wb", []> {
15931634 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
15951636 let DecoderMethod = "DecodeVLDST1Instruction";
15961637 }
15971638 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1598 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1639 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
15991640 IIC_VLD1u,
16001641 "vst1", Dt, "$Vd, $Rn, $Rm",
16011642 "$Rn.addr = $wb", []> {
16031644 let DecoderMethod = "DecodeVLDST1Instruction";
16041645 }
16051646 }
1606 multiclass VST1QWB op7_4, string Dt> {
1647 multiclass VST1QWB op7_4, string Dt, Operand AddrMode> {
16071648 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1608 (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1649 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
16091650 "vst1", Dt, "$Vd, $Rn!",
16101651 "$Rn.addr = $wb", []> {
16111652 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
16131654 let DecoderMethod = "DecodeVLDST1Instruction";
16141655 }
16151656 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1616 (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1657 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
16171658 IIC_VLD1x2u,
16181659 "vst1", Dt, "$Vd, $Rn, $Rm",
16191660 "$Rn.addr = $wb", []> {
16221663 }
16231664 }
16241665
1625 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1626 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1627 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1628 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1629
1630 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1631 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1632 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1633 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1666 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8", addrmode6align64>;
1667 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16", addrmode6align64>;
1668 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32", addrmode6align64>;
1669 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64", addrmode6align64>;
1670
1671 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
1672 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
1673 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
1674 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
16341675
16351676 // ...with 3 registers
1636 class VST1D3 op7_4, string Dt>
1677 class VST1D3 op7_4, string Dt, Operand AddrMode>
16371678 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1638 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1679 (ins AddrMode:$Rn, VecListThreeD:$Vd),
16391680 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
16401681 let Rm = 0b1111;
16411682 let Inst{4} = Rn{4};
16421683 let DecoderMethod = "DecodeVLDST1Instruction";
16431684 }
1644 multiclass VST1D3WB op7_4, string Dt> {
1685 multiclass VST1D3WB op7_4, string Dt, Operand AddrMode> {
16451686 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1646 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1687 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
16471688 "vst1", Dt, "$Vd, $Rn!",
16481689 "$Rn.addr = $wb", []> {
16491690 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
16511692 let DecoderMethod = "DecodeVLDST1Instruction";
16521693 }
16531694 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1654 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1695 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
16551696 IIC_VLD1x3u,
16561697 "vst1", Dt, "$Vd, $Rn, $Rm",
16571698 "$Rn.addr = $wb", []> {
16601701 }
16611702 }
16621703
1663 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1664 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1665 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1666 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1667
1668 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1669 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1670 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1671 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1704 def VST1d8T : VST1D3<{0,0,0,?}, "8", addrmode6align64>;
1705 def VST1d16T : VST1D3<{0,1,0,?}, "16", addrmode6align64>;
1706 def VST1d32T : VST1D3<{1,0,0,?}, "32", addrmode6align64>;
1707 def VST1d64T : VST1D3<{1,1,0,?}, "64", addrmode6align64>;
1708
1709 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8", addrmode6align64>;
1710 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16", addrmode6align64>;
1711 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32", addrmode6align64>;
1712 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64", addrmode6align64>;
16721713
16731714 def VST1d64TPseudo : VSTQQPseudo;
16741715 def VST1d64TPseudoWB_fixed : VSTQQWBfixedPseudo;
16751716 def VST1d64TPseudoWB_register : VSTQQWBPseudo;
16761717
16771718 // ...with 4 registers
1678 class VST1D4 op7_4, string Dt>
1719 class VST1D4 op7_4, string Dt, Operand AddrMode>
16791720 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1680 (ins addrmode6:$Rn, VecListFourD:$Vd),
1721 (ins AddrMode:$Rn, VecListFourD:$Vd),
16811722 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
16821723 []> {
16831724 let Rm = 0b1111;
16841725 let Inst{5-4} = Rn{5-4};
16851726 let DecoderMethod = "DecodeVLDST1Instruction";
16861727 }
1687 multiclass VST1D4WB op7_4, string Dt> {
1728 multiclass VST1D4WB op7_4, string Dt, Operand AddrMode> {
16881729 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1689 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1730 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
16901731 "vst1", Dt, "$Vd, $Rn!",
16911732 "$Rn.addr = $wb", []> {
16921733 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
16941735 let DecoderMethod = "DecodeVLDST1Instruction";
16951736 }
16961737 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1697 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1738 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
16981739 IIC_VLD1x4u,
16991740 "vst1", Dt, "$Vd, $Rn, $Rm",
17001741 "$Rn.addr = $wb", []> {
17031744 }
17041745 }
17051746
1706 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1707 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1708 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1709 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1710
1711 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1712 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1713 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1714 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1747 def VST1d8Q : VST1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
1748 def VST1d16Q : VST1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
1749 def VST1d32Q : VST1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
1750 def VST1d64Q : VST1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
1751
1752 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1753 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1754 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1755 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
17151756
17161757 def VST1d64QPseudo : VSTQQPseudo;
17171758 def VST1d64QPseudoWB_fixed : VSTQQWBfixedPseudo;
17191760
17201761 // VST2 : Vector Store (multiple 2-element structures)
17211762 class VST2 op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1722 InstrItinClass itin>
1723 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1763 InstrItinClass itin, Operand AddrMode>
1764 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
17241765 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
17251766 let Rm = 0b1111;
17261767 let Inst{5-4} = Rn{5-4};
17271768 let DecoderMethod = "DecodeVLDST2Instruction";
17281769 }
17291770
1730 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
1731 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;
1732 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;
1733
1734 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1735 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1736 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1771 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2,
1772 addrmode6align64or128>;
1773 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2,
1774 addrmode6align64or128>;
1775 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2,
1776 addrmode6align64or128>;
1777
1778 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1779 addrmode6align64or128or256>;
1780 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
1781 addrmode6align64or128or256>;
1782 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2,
1783 addrmode6align64or128or256>;
17371784
17381785 def VST2q8Pseudo : VSTQQPseudo;
17391786 def VST2q16Pseudo : VSTQQPseudo;
17411788
17421789 // ...with address register writeback:
17431790 multiclass VST2DWB op11_8, bits<4> op7_4, string Dt,
1744 RegisterOperand VdTy> {
1791 RegisterOperand VdTy, Operand AddrMode> {
17451792 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1746 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1793 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
17471794 "vst2", Dt, "$Vd, $Rn!",
17481795 "$Rn.addr = $wb", []> {
17491796 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
17511798 let DecoderMethod = "DecodeVLDST2Instruction";
17521799 }
17531800 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1754 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1801 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
17551802 "vst2", Dt, "$Vd, $Rn, $Rm",
17561803 "$Rn.addr = $wb", []> {
17571804 let Inst{5-4} = Rn{5-4};
17581805 let DecoderMethod = "DecodeVLDST2Instruction";
17591806 }
17601807 }
1761 multiclass VST2QWB op7_4, string Dt> {
1808 multiclass VST2QWB op7_4, string Dt, Operand AddrMode> {
17621809 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1763 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1810 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
17641811 "vst2", Dt, "$Vd, $Rn!",
17651812 "$Rn.addr = $wb", []> {
17661813 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
17681815 let DecoderMethod = "DecodeVLDST2Instruction";
17691816 }
17701817 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1771 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1818 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
17721819 IIC_VLD1u,
17731820 "vst2", Dt, "$Vd, $Rn, $Rm",
17741821 "$Rn.addr = $wb", []> {
17771824 }
17781825 }
17791826
1780 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;
1781 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;
1782 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;
1783
1784 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1785 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1786 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1827 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair,
1828 addrmode6align64or128>;
1829 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair,
1830 addrmode6align64or128>;
1831 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair,
1832 addrmode6align64or128>;
1833
1834 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1835 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1836 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32", addrmode6align64or128or256>;
17871837
17881838 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo;
17891839 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo;
17931843 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo;
17941844
17951845 // ...with double-spaced registers
1796 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
1797 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
1798 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
1799 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
1800 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
1801 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
1846 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2,
1847 addrmode6align64or128>;
1848 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2,
1849 addrmode6align64or128>;
1850 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2,
1851 addrmode6align64or128>;
1852 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced,
1853 addrmode6align64or128>;
1854 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced,
1855 addrmode6align64or128>;
1856 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced,
1857 addrmode6align64or128>;
18021858
18031859 // VST3 : Vector Store (multiple 3-element structures)
18041860 class VST3D op11_8, bits<4> op7_4, string Dt>
63106366 // VLD1 single-lane pseudo-instructions. These need special handling for
63116367 // the lane index that an InstAlias can't handle, so we use these instead.
63126368 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
6313 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6369 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6370 pred:$p)>;
63146371 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
6315 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6372 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6373 pred:$p)>;
63166374 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
6317 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6375 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6376 pred:$p)>;
63186377
63196378 def VLD1LNdWB_fixed_Asm_8 :
63206379 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
6321 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6380 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6381 pred:$p)>;
63226382 def VLD1LNdWB_fixed_Asm_16 :
63236383 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
6324 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6384 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6385 pred:$p)>;
63256386 def VLD1LNdWB_fixed_Asm_32 :
63266387 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
6327 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6388 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6389 pred:$p)>;
63286390 def VLD1LNdWB_register_Asm_8 :
63296391 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
6330 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
6392 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
63316393 rGPR:$Rm, pred:$p)>;
63326394 def VLD1LNdWB_register_Asm_16 :
63336395 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
6334 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
6396 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
63356397 rGPR:$Rm, pred:$p)>;
63366398 def VLD1LNdWB_register_Asm_32 :
63376399 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
6338 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
6400 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
63396401 rGPR:$Rm, pred:$p)>;
63406402
63416403
63426404 // VST1 single-lane pseudo-instructions. These need special handling for
63436405 // the lane index that an InstAlias can't handle, so we use these instead.
63446406 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
6345 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6407 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6408 pred:$p)>;
63466409 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
6347 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6410 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6411 pred:$p)>;
63486412 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
6349 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6413 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6414 pred:$p)>;
63506415
63516416 def VST1LNdWB_fixed_Asm_8 :
63526417 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
6353 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6418 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6419 pred:$p)>;
63546420 def VST1LNdWB_fixed_Asm_16 :
63556421 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
6356 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6422 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6423 pred:$p)>;
63576424 def VST1LNdWB_fixed_Asm_32 :
63586425 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
6359 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6426 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6427 pred:$p)>;
63606428 def VST1LNdWB_register_Asm_8 :
63616429 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
6362 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
6430 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
63636431 rGPR:$Rm, pred:$p)>;
63646432 def VST1LNdWB_register_Asm_16 :
63656433 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
6366 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
6434 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
63676435 rGPR:$Rm, pred:$p)>;
63686436 def VST1LNdWB_register_Asm_32 :
63696437 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
6370 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
6438 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
63716439 rGPR:$Rm, pred:$p)>;
63726440
63736441 // VLD2 single-lane pseudo-instructions. These need special handling for
63746442 // the lane index that an InstAlias can't handle, so we use these instead.
63756443 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
6376 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6444 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6445 pred:$p)>;
63776446 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6378 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6447 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6448 pred:$p)>;
63796449 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6380 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6450 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>;
63816451 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6382 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6452 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6453 pred:$p)>;
63836454 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6384 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6455 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6456 pred:$p)>;
63856457
63866458 def VLD2LNdWB_fixed_Asm_8 :
63876459 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
6388 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6460 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6461 pred:$p)>;
63896462 def VLD2LNdWB_fixed_Asm_16 :
63906463 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6391 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6464 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6465 pred:$p)>;
63926466 def VLD2LNdWB_fixed_Asm_32 :
63936467 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6394 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6468 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6469 pred:$p)>;
63956470 def VLD2LNqWB_fixed_Asm_16 :
63966471 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6397 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6472 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6473 pred:$p)>;
63986474 def VLD2LNqWB_fixed_Asm_32 :
63996475 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6400 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6476 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6477 pred:$p)>;
64016478 def VLD2LNdWB_register_Asm_8 :
64026479 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
6403 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
6480 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
64046481 rGPR:$Rm, pred:$p)>;
64056482 def VLD2LNdWB_register_Asm_16 :
64066483 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6407 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6484 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
64086485 rGPR:$Rm, pred:$p)>;
64096486 def VLD2LNdWB_register_Asm_32 :
64106487 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6411 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6488 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
64126489 rGPR:$Rm, pred:$p)>;
64136490 def VLD2LNqWB_register_Asm_16 :
64146491 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6415 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6492 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
64166493 rGPR:$Rm, pred:$p)>;
64176494 def VLD2LNqWB_register_Asm_32 :
64186495 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6419 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6496 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
64206497 rGPR:$Rm, pred:$p)>;
64216498
64226499
64236500 // VST2 single-lane pseudo-instructions. These need special handling for
64246501 // the lane index that an InstAlias can't handle, so we use these instead.
64256502 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
6426 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6503 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6504 pred:$p)>;
64276505 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6428 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6506 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6507 pred:$p)>;
64296508 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6430 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6509 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6510 pred:$p)>;
64316511 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6432 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6512 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6513 pred:$p)>;
64336514 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6434 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6515 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6516 pred:$p)>;
64356517
64366518 def VST2LNdWB_fixed_Asm_8 :
64376519 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
6438 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6520 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6521 pred:$p)>;
64396522 def VST2LNdWB_fixed_Asm_16 :
64406523 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6441 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6524 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6525 pred:$p)>;
64426526 def VST2LNdWB_fixed_Asm_32 :
64436527 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6444 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6528 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6529 pred:$p)>;
64456530 def VST2LNqWB_fixed_Asm_16 :
64466531 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6447 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6532 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6533 pred:$p)>;
64486534 def VST2LNqWB_fixed_Asm_32 :
64496535 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6450 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6536 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6537 pred:$p)>;
64516538 def VST2LNdWB_register_Asm_8 :
64526539 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
6453 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
6540 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
64546541 rGPR:$Rm, pred:$p)>;
64556542 def VST2LNdWB_register_Asm_16 :
64566543 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6457 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6544 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
64586545 rGPR:$Rm, pred:$p)>;
64596546 def VST2LNdWB_register_Asm_32 :
64606547 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6461 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6548 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
64626549 rGPR:$Rm, pred:$p)>;
64636550 def VST2LNqWB_register_Asm_16 :
64646551 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6465 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6552 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
64666553 rGPR:$Rm, pred:$p)>;
64676554 def VST2LNqWB_register_Asm_32 :
64686555 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6469 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6556 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
64706557 rGPR:$Rm, pred:$p)>;
64716558
64726559 // VLD3 all-lanes pseudo-instructions. These need special handling for
64736560 // the lane index that an InstAlias can't handle, so we use these instead.
64746561 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6475 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6562 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6563 pred:$p)>;
64766564 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6477 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6565 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6566 pred:$p)>;
64786567 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6479 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6568 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6569 pred:$p)>;
64806570 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6481 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6571 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6572 pred:$p)>;
64826573 def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6483 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6574 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6575 pred:$p)>;
64846576 def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6485 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6577 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6578 pred:$p)>;
64866579
64876580 def VLD3DUPdWB_fixed_Asm_8 :
64886581 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6489 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6582 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6583 pred:$p)>;
64906584 def VLD3DUPdWB_fixed_Asm_16 :
64916585 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6492 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6586 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6587 pred:$p)>;
64936588 def VLD3DUPdWB_fixed_Asm_32 :
64946589 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6495 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6590 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6591 pred:$p)>;
64966592 def VLD3DUPqWB_fixed_Asm_8 :
64976593 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6498 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6594 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6595 pred:$p)>;
64996596 def VLD3DUPqWB_fixed_Asm_16 :
65006597 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6501 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6598 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6599 pred:$p)>;
65026600 def VLD3DUPqWB_fixed_Asm_32 :
65036601 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6504 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6602 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6603 pred:$p)>;
65056604 def VLD3DUPdWB_register_Asm_8 :
65066605 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6507 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6606 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
65086607 rGPR:$Rm, pred:$p)>;
65096608 def VLD3DUPdWB_register_Asm_16 :
65106609 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6511 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6610 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
65126611 rGPR:$Rm, pred:$p)>;
65136612 def VLD3DUPdWB_register_Asm_32 :
65146613 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6515 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6614 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
65166615 rGPR:$Rm, pred:$p)>;
65176616 def VLD3DUPqWB_register_Asm_8 :
65186617 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6519 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6618 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
65206619 rGPR:$Rm, pred:$p)>;
65216620 def VLD3DUPqWB_register_Asm_16 :
65226621 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6523 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6622 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
65246623 rGPR:$Rm, pred:$p)>;
65256624 def VLD3DUPqWB_register_Asm_32 :
65266625 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6527 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6626 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
65286627 rGPR:$Rm, pred:$p)>;
65296628
65306629
65316630 // VLD3 single-lane pseudo-instructions. These need special handling for
65326631 // the lane index that an InstAlias can't handle, so we use these instead.
65336632 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6534 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6633 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6634 pred:$p)>;
65356635 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6536 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6636 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6637 pred:$p)>;
65376638 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6538 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6639 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6640 pred:$p)>;
65396641 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6540 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6642 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6643 pred:$p)>;
65416644 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6542 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6645 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6646 pred:$p)>;
65436647
65446648 def VLD3LNdWB_fixed_Asm_8 :
65456649 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6546 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6650 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6651 pred:$p)>;
65476652 def VLD3LNdWB_fixed_Asm_16 :
65486653 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6549 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6654 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6655 pred:$p)>;
65506656 def VLD3LNdWB_fixed_Asm_32 :
65516657 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6552 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6658 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6659 pred:$p)>;
65536660 def VLD3LNqWB_fixed_Asm_16 :
65546661 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6555 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6662 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6663 pred:$p)>;
65566664 def VLD3LNqWB_fixed_Asm_32 :
65576665 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6558 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6666 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6667 pred:$p)>;
65596668 def VLD3LNdWB_register_Asm_8 :
65606669 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6561 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6670 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
65626671 rGPR:$Rm, pred:$p)>;
65636672 def VLD3LNdWB_register_Asm_16 :
65646673 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6565 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6566 rGPR:$Rm, pred:$p)>;
6674 (ins VecListThreeDHWordIndexed:$list,
6675 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
65676676 def VLD3LNdWB_register_Asm_32 :
65686677 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6569 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6678 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
65706679 rGPR:$Rm, pred:$p)>;
65716680 def VLD3LNqWB_register_Asm_16 :
65726681 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6573 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6574 rGPR:$Rm, pred:$p)>;
6682 (ins VecListThreeQHWordIndexed:$list,
6683 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
65756684 def VLD3LNqWB_register_Asm_32 :
65766685 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6577 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6686 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
65786687 rGPR:$Rm, pred:$p)>;
65796688
65806689 // VLD3 multiple structure pseudo-instructions. These need special handling for
65816690 // the vector operands that the normal instructions don't yet model.
65826691 // FIXME: Remove these when the register classes and instructions are updated.
65836692 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6584 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6693 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
65856694 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6586 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6695 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
65876696 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6588 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6697 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
65896698 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6590 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6699 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
65916700 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6592 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6701 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
65936702 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6594 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6703 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
65956704
65966705 def VLD3dWB_fixed_Asm_8 :
65976706 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6598 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6707 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
65996708 def VLD3dWB_fixed_Asm_16 :
66006709 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6601 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6710 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
66026711 def VLD3dWB_fixed_Asm_32 :
66036712 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6604 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6713 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
66056714 def VLD3qWB_fixed_Asm_8 :
66066715 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6607 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6716 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
66086717 def VLD3qWB_fixed_Asm_16 :
66096718 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6610 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6719 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
66116720 def VLD3qWB_fixed_Asm_32 :
66126721 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6613 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6722 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
66146723 def VLD3dWB_register_Asm_8 :
66156724 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6616 (ins VecListThreeD:$list, addrmode6:$addr,
6725 (ins VecListThreeD:$list, addrmode6align64:$addr,
66176726 rGPR:$Rm, pred:$p)>;
66186727 def VLD3dWB_register_Asm_16 :
66196728 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6620 (ins VecListThreeD:$list, addrmode6:$addr,
6729 (ins VecListThreeD:$list, addrmode6align64:$addr,
66216730 rGPR:$Rm, pred:$p)>;
66226731 def VLD3dWB_register_Asm_32 :
66236732 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6624 (ins VecListThreeD:$list, addrmode6:$addr,
6733 (ins VecListThreeD:$list, addrmode6align64:$addr,
66256734 rGPR:$Rm, pred:$p)>;
66266735 def VLD3qWB_register_Asm_8 :
66276736 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6628 (ins VecListThreeQ:$list, addrmode6:$addr,
6737 (ins VecListThreeQ:$list, addrmode6align64:$addr,
66296738 rGPR:$Rm, pred:$p)>;
66306739 def VLD3qWB_register_Asm_16 :
66316740 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6632 (ins VecListThreeQ:$list, addrmode6:$addr,
6741 (ins VecListThreeQ:$list, addrmode6align64:$addr,
66336742 rGPR:$Rm, pred:$p)>;
66346743 def VLD3qWB_register_Asm_32 :
66356744 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6636 (ins VecListThreeQ:$list, addrmode6:$addr,
6745 (ins VecListThreeQ:$list, addrmode6align64:$addr,
66376746 rGPR:$Rm, pred:$p)>;
66386747
66396748 // VST3 single-lane pseudo-instructions. These need special handling for
66406749 // the lane index that an InstAlias can't handle, so we use these instead.
66416750 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6642 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6751 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6752 pred:$p)>;
66436753 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6644 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6754 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6755 pred:$p)>;
66456756 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6646 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6757 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6758 pred:$p)>;
66476759 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6648 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6760 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6761 pred:$p)>;
66496762 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6650 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6763 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6764 pred:$p)>;
66516765
66526766 def VST3LNdWB_fixed_Asm_8 :
66536767 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6654 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6768 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6769 pred:$p)>;
66556770 def VST3LNdWB_fixed_Asm_16 :
66566771 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6657 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6772 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6773 pred:$p)>;
66586774 def VST3LNdWB_fixed_Asm_32 :
66596775 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6660 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6776 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6777 pred:$p)>;
66616778 def VST3LNqWB_fixed_Asm_16 :
66626779 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6663 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6780 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6781 pred:$p)>;
66646782 def VST3LNqWB_fixed_Asm_32 :
66656783 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6666 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6784 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6785 pred:$p)>;
66676786 def VST3LNdWB_register_Asm_8 :
66686787 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6669 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6788 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
66706789 rGPR:$Rm, pred:$p)>;
66716790 def VST3LNdWB_register_Asm_16 :
66726791 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6673 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6674 rGPR:$Rm, pred:$p)>;
6792 (ins VecListThreeDHWordIndexed:$list,
6793 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
66756794 def VST3LNdWB_register_Asm_32 :
66766795 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6677 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6796 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
66786797 rGPR:$Rm, pred:$p)>;
66796798 def VST3LNqWB_register_Asm_16 :
66806799 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6681 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6682 rGPR:$Rm, pred:$p)>;
6800 (ins VecListThreeQHWordIndexed:$list,
6801 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
66836802 def VST3LNqWB_register_Asm_32 :
66846803 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6685 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6804 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
66866805 rGPR:$Rm, pred:$p)>;
66876806
66886807
66906809 // the vector operands that the normal instructions don't yet model.
66916810 // FIXME: Remove these when the register classes and instructions are updated.
66926811 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6693 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6812 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
66946813 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6695 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6814 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
66966815 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6697 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6816 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
66986817 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6699 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6818 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
67006819 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6701 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6820 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
67026821 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6703 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6822 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
67046823
67056824 def VST3dWB_fixed_Asm_8 :
67066825 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6707 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6826 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
67086827 def VST3dWB_fixed_Asm_16 :
67096828 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6710 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6829 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
67116830 def VST3dWB_fixed_Asm_32 :
67126831 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6713 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6832 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
67146833 def VST3qWB_fixed_Asm_8 :
67156834 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6716 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6835 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
67176836 def VST3qWB_fixed_Asm_16 :
67186837 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6719 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6838 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
67206839 def VST3qWB_fixed_Asm_32 :
67216840 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6722 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6841 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
67236842 def VST3dWB_register_Asm_8 :
67246843 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6725 (ins VecListThreeD:$list, addrmode6:$addr,
6844 (ins VecListThreeD:$list, addrmode6align64:$addr,
67266845 rGPR:$Rm, pred:$p)>;
67276846 def VST3dWB_register_Asm_16 :
67286847 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6729 (ins VecListThreeD:$list, addrmode6:$addr,
6848 (ins VecListThreeD:$list, addrmode6align64:$addr,
67306849 rGPR:$Rm, pred:$p)>;
67316850 def VST3dWB_register_Asm_32 :
67326851 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6733 (ins VecListThreeD:$list, addrmode6:$addr,
6852 (ins VecListThreeD:$list, addrmode6align64:$addr,
67346853 rGPR:$Rm, pred:$p)>;
67356854 def VST3qWB_register_Asm_8 :
67366855 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6737 (ins VecListThreeQ:$list, addrmode6:$addr,
6856 (ins VecListThreeQ:$list, addrmode6align64:$addr,
67386857 rGPR:$Rm, pred:$p)>;
67396858 def VST3qWB_register_Asm_16 :
67406859 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6741 (ins VecListThreeQ:$list, addrmode6:$addr,
6860 (ins VecListThreeQ:$list, addrmode6align64:$addr,
67426861 rGPR:$Rm, pred:$p)>;
67436862 def VST3qWB_register_Asm_32 :
67446863 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6745 (ins VecListThreeQ:$list, addrmode6:$addr,
6864 (ins VecListThreeQ:$list, addrmode6align64:$addr,
67466865 rGPR:$Rm, pred:$p)>;
67476866
67486867 // VLD4 all-lanes pseudo-instructions. These need special handling for
67496868 // the lane index that an InstAlias can't handle, so we use these instead.
67506869 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6751 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6870 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6871 pred:$p)>;
67526872 def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6753 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6873 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6874 pred:$p)>;
67546875 def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6755 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6876 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
6877 pred:$p)>;
67566878 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6757 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6879 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
6880 pred:$p)>;
67586881 def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6759 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6882 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
6883 pred:$p)>;
67606884 def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6761 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6885 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
6886 pred:$p)>;
67626887
67636888 def VLD4DUPdWB_fixed_Asm_8 :
67646889 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6765 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6890 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6891 pred:$p)>;
67666892 def VLD4DUPdWB_fixed_Asm_16 :
67676893 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6768 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6894 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6895 pred:$p)>;
67696896 def VLD4DUPdWB_fixed_Asm_32 :
67706897 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6771 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6898 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
6899 pred:$p)>;
67726900 def VLD4DUPqWB_fixed_Asm_8 :
67736901 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6774 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6902 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
6903 pred:$p)>;
67756904 def VLD4DUPqWB_fixed_Asm_16 :
67766905 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6777 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6906 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
6907 pred:$p)>;
67786908 def VLD4DUPqWB_fixed_Asm_32 :
67796909 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6780 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6910 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
6911 pred:$p)>;
67816912 def VLD4DUPdWB_register_Asm_8 :
67826913 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6783 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6914 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
67846915 rGPR:$Rm, pred:$p)>;
67856916 def VLD4DUPdWB_register_Asm_16 :
67866917 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6787 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6918 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
67886919 rGPR:$Rm, pred:$p)>;
67896920 def VLD4DUPdWB_register_Asm_32 :
67906921 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6791 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6792 rGPR:$Rm, pred:$p)>;
6922 (ins VecListFourDAllLanes:$list,
6923 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
67936924 def VLD4DUPqWB_register_Asm_8 :
67946925 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6795 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6926 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
67966927 rGPR:$Rm, pred:$p)>;
67976928 def VLD4DUPqWB_register_Asm_16 :
67986929 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6799 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6930 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
68006931 rGPR:$Rm, pred:$p)>;
68016932 def VLD4DUPqWB_register_Asm_32 :
68026933 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6803 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6804 rGPR:$Rm, pred:$p)>;
6934 (ins VecListFourQAllLanes:$list,
6935 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
68056936
68066937
68076938 // VLD4 single-lane pseudo-instructions. These need special handling for
68086939 // the lane index that an InstAlias can't handle, so we use these instead.
68096940 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6810 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6941 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
6942 pred:$p)>;
68116943 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6812 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6944 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
6945 pred:$p)>;
68136946 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6814 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6947 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
6948 pred:$p)>;
68156949 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6816 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6950 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
6951 pred:$p)>;
68176952 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6818 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6953 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
6954 pred:$p)>;
68196955
68206956 def VLD4LNdWB_fixed_Asm_8 :
68216957 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6822 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6958 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
6959 pred:$p)>;
68236960 def VLD4LNdWB_fixed_Asm_16 :
68246961 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6825 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6962 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
6963 pred:$p)>;
68266964 def VLD4LNdWB_fixed_Asm_32 :
68276965 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6828 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6966 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
6967 pred:$p)>;
68296968 def VLD4LNqWB_fixed_Asm_16 :
68306969 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6831 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6970 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
6971 pred:$p)>;
68326972 def VLD4LNqWB_fixed_Asm_32 :
68336973 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6834 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6974 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
6975 pred:$p)>;
68356976 def VLD4LNdWB_register_Asm_8 :
68366977 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6837 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6978 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
68386979 rGPR:$Rm, pred:$p)>;
68396980 def VLD4LNdWB_register_Asm_16 :
68406981 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6841 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6982 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
68426983 rGPR:$Rm, pred:$p)>;
68436984 def VLD4LNdWB_register_Asm_32 :
68446985 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6845 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6846 rGPR:$Rm, pred:$p)>;
6986 (ins VecListFourDWordIndexed:$list,
6987 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
68476988 def VLD4LNqWB_register_Asm_16 :
68486989 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6849 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6990 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
68506991 rGPR:$Rm, pred:$p)>;
68516992 def VLD4LNqWB_register_Asm_32 :
68526993 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6853 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6854 rGPR:$Rm, pred:$p)>;
6994 (ins VecListFourQWordIndexed:$list,
6995 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
68556996
68566997
68576998
68597000 // the vector operands that the normal instructions don't yet model.
68607001 // FIXME: Remove these when the register classes and instructions are updated.
68617002 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6862 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7003 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7004 pred:$p)>;
68637005 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6864 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7006 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7007 pred:$p)>;
68657008 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6866 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7009 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7010 pred:$p)>;
68677011 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6868 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7012 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7013 pred:$p)>;
68697014 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6870 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7015 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7016 pred:$p)>;
68717017 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6872 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7018 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7019 pred:$p)>;
68737020
68747021 def VLD4dWB_fixed_Asm_8 :
68757022 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6876 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7023 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7024 pred:$p)>;
68777025 def VLD4dWB_fixed_Asm_16 :
68787026 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6879 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7027 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7028 pred:$p)>;
68807029 def VLD4dWB_fixed_Asm_32 :
68817030 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6882 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7031 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7032 pred:$p)>;
68837033 def VLD4qWB_fixed_Asm_8 :
68847034 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6885 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7035 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7036 pred:$p)>;
68867037 def VLD4qWB_fixed_Asm_16 :
68877038 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6888 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7039 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7040 pred:$p)>;
68897041 def VLD4qWB_fixed_Asm_32 :
68907042 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6891 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7043 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7044 pred:$p)>;
68927045 def VLD4dWB_register_Asm_8 :
68937046 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6894 (ins VecListFourD:$list, addrmode6:$addr,
7047 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
68957048 rGPR:$Rm, pred:$p)>;
68967049 def VLD4dWB_register_Asm_16 :
68977050 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6898 (ins VecListFourD:$list, addrmode6:$addr,
7051 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
68997052 rGPR:$Rm, pred:$p)>;
69007053 def VLD4dWB_register_Asm_32 :
69017054 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6902 (ins VecListFourD:$list, addrmode6:$addr,
7055 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
69037056 rGPR:$Rm, pred:$p)>;
69047057 def VLD4qWB_register_Asm_8 :
69057058 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6906 (ins VecListFourQ:$list, addrmode6:$addr,
7059 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
69077060 rGPR:$Rm, pred:$p)>;
69087061 def VLD4qWB_register_Asm_16 :
69097062 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6910 (ins VecListFourQ:$list, addrmode6:$addr,
7063 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
69117064 rGPR:$Rm, pred:$p)>;
69127065 def VLD4qWB_register_Asm_32 :
69137066 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6914 (ins VecListFourQ:$list, addrmode6:$addr,
7067 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
69157068 rGPR:$Rm, pred:$p)>;
69167069
69177070 // VST4 single-lane pseudo-instructions. These need special handling for
69187071 // the lane index that an InstAlias can't handle, so we use these instead.
69197072 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6920 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
7073 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7074 pred:$p)>;
69217075 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6922 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
7076 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7077 pred:$p)>;
69237078 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6924 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
7079 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7080 pred:$p)>;
69257081 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6926 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
7082 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7083 pred:$p)>;
69277084 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6928 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
7085 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7086 pred:$p)>;
69297087
69307088 def VST4LNdWB_fixed_Asm_8 :
69317089 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6932 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
7090 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7091 pred:$p)>;
69337092 def VST4LNdWB_fixed_Asm_16 :
69347093 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6935 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
7094 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7095 pred:$p)>;
69367096 def VST4LNdWB_fixed_Asm_32 :
69377097 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6938 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
7098 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7099 pred:$p)>;
69397100 def VST4LNqWB_fixed_Asm_16 :
69407101 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6941 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
7102 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7103 pred:$p)>;
69427104 def VST4LNqWB_fixed_Asm_32 :
69437105 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6944 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
7106 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7107 pred:$p)>;
69457108 def VST4LNdWB_register_Asm_8 :
69467109 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6947 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
7110 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
69487111 rGPR:$Rm, pred:$p)>;
69497112 def VST4LNdWB_register_Asm_16 :
69507113 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6951 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
7114 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
69527115 rGPR:$Rm, pred:$p)>;
69537116 def VST4LNdWB_register_Asm_32 :
69547117 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6955 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6956 rGPR:$Rm, pred:$p)>;
7118 (ins VecListFourDWordIndexed:$list,
7119 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
69577120 def VST4LNqWB_register_Asm_16 :
69587121 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6959 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
7122 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
69607123 rGPR:$Rm, pred:$p)>;
69617124 def VST4LNqWB_register_Asm_32 :
69627125 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6963 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6964 rGPR:$Rm, pred:$p)>;
7126 (ins VecListFourQWordIndexed:$list,
7127 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
69657128
69667129
69677130 // VST4 multiple structure pseudo-instructions. These need special handling for
69687131 // the vector operands that the normal instructions don't yet model.
69697132 // FIXME: Remove these when the register classes and instructions are updated.
69707133 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6971 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7134 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7135 pred:$p)>;
69727136 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6973 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7137 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7138 pred:$p)>;
69747139 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6975 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7140 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7141 pred:$p)>;
69767142 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6977 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7143 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7144 pred:$p)>;
69787145 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6979 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7146 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7147 pred:$p)>;
69807148 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6981 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7149 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7150 pred:$p)>;
69827151
69837152 def VST4dWB_fixed_Asm_8 :
69847153 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6985 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7154 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7155 pred:$p)>;
69867156 def VST4dWB_fixed_Asm_16 :
69877157 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6988 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7158 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7159 pred:$p)>;
69897160 def VST4dWB_fixed_Asm_32 :
69907161 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6991 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
7162 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7163 pred:$p)>;
69927164 def VST4qWB_fixed_Asm_8 :
69937165 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6994 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7166 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7167 pred:$p)>;
69957168 def VST4qWB_fixed_Asm_16 :
69967169 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6997 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7170 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7171 pred:$p)>;
69987172 def VST4qWB_fixed_Asm_32 :
69997173 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7000 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7174 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7175 pred:$p)>;
70017176 def VST4dWB_register_Asm_8 :
70027177 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7003 (ins VecListFourD:$list, addrmode6:$addr,
7178 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
70047179 rGPR:$Rm, pred:$p)>;
70057180 def VST4dWB_register_Asm_16 :
70067181 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7007 (ins VecListFourD:$list, addrmode6:$addr,
7182 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
70087183 rGPR:$Rm, pred:$p)>;
70097184 def VST4dWB_register_Asm_32 :
70107185 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7011 (ins VecListFourD:$list, addrmode6:$addr,
7186 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
70127187 rGPR:$Rm, pred:$p)>;
70137188 def VST4qWB_register_Asm_8 :
70147189 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7015 (ins VecListFourQ:$list, addrmode6:$addr,
7190 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
70167191 rGPR:$Rm, pred:$p)>;
70177192 def VST4qWB_register_Asm_16 :
70187193 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7019 (ins VecListFourQ:$list, addrmode6:$addr,
7194 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
70207195 rGPR:$Rm, pred:$p)>;
70217196 def VST4qWB_register_Asm_32 :
70227197 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7023 (ins VecListFourQ:$list, addrmode6:$addr,
7198 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
70247199 rGPR:$Rm, pred:$p)>;
70257200
70267201 // VMOV/VMVN takes an optional datatype suffix
415415 k_Token
416416 } Kind;
417417
418 SMLoc StartLoc, EndLoc;
418 SMLoc StartLoc, EndLoc, AlignmentLoc;
419419 SmallVector Registers;
420420
421421 struct CCOp {
632632 /// operand.
633633 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
634634
635 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
636 SMLoc getAlignmentLoc() const {
637 assert(Kind == k_Memory && "Invalid access!");
638 return AlignmentLoc;
639 }
640
635641 ARMCC::CondCodes getCondCode() const {
636642 assert(Kind == k_CondCode && "Invalid access!");
637643 return CC.Val;
10881094 bool isPostIdxReg() const {
10891095 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
10901096 }
1091 bool isMemNoOffset(bool alignOK = false) const {
1097 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
10921098 if (!isMem())
10931099 return false;
10941100 // No offset of any kind.
10951101 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1096 (alignOK || Memory.Alignment == 0);
1102 (alignOK || Memory.Alignment == Alignment);
10971103 }
10981104 bool isMemPCRelImm12() const {
10991105 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
11081114 }
11091115 bool isAlignedMemory() const {
11101116 return isMemNoOffset(true);
1117 }
1118 bool isAlignedMemoryNone() const {
1119 return isMemNoOffset(false, 0);
1120 }
1121 bool isDupAlignedMemoryNone() const {
1122 return isMemNoOffset(false, 0);
1123 }
1124 bool isAlignedMemory16() const {
1125 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1126 return true;
1127 return isMemNoOffset(false, 0);
1128 }
1129 bool isDupAlignedMemory16() const {
1130 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1131 return true;
1132 return isMemNoOffset(false, 0);
1133 }
1134 bool isAlignedMemory32() const {
1135 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1136 return true;
1137 return isMemNoOffset(false, 0);
1138 }
1139 bool isDupAlignedMemory32() const {
1140 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1141 return true;
1142 return isMemNoOffset(false, 0);
1143 }
1144 bool isAlignedMemory64() const {
1145 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1146 return true;
1147 return isMemNoOffset(false, 0);
1148 }
1149 bool isDupAlignedMemory64() const {
1150 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1151 return true;
1152 return isMemNoOffset(false, 0);
1153 }
1154 bool isAlignedMemory64or128() const {
1155 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1156 return true;
1157 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1158 return true;
1159 return isMemNoOffset(false, 0);
1160 }
1161 bool isDupAlignedMemory64or128() const {
1162 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1163 return true;
1164 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1165 return true;
1166 return isMemNoOffset(false, 0);
1167 }
1168 bool isAlignedMemory64or128or256() const {
1169 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1170 return true;
1171 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1172 return true;
1173 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1174 return true;
1175 return isMemNoOffset(false, 0);
11111176 }
11121177 bool isAddrMode2() const {
11131178 if (!isMem() || Memory.Alignment != 0) return false;
19251990 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
19261991 }
19271992
1993 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
1994 addAlignedMemoryOperands(Inst, N);
1995 }
1996
1997 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
1998 addAlignedMemoryOperands(Inst, N);
1999 }
2000
2001 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2002 addAlignedMemoryOperands(Inst, N);
2003 }
2004
2005 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2006 addAlignedMemoryOperands(Inst, N);
2007 }
2008
2009 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2010 addAlignedMemoryOperands(Inst, N);
2011 }
2012
2013 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2014 addAlignedMemoryOperands(Inst, N);
2015 }
2016
2017 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2018 addAlignedMemoryOperands(Inst, N);
2019 }
2020
2021 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2022 addAlignedMemoryOperands(Inst, N);
2023 }
2024
2025 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2026 addAlignedMemoryOperands(Inst, N);
2027 }
2028
2029 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2030 addAlignedMemoryOperands(Inst, N);
2031 }
2032
2033 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2034 addAlignedMemoryOperands(Inst, N);
2035 }
2036
19282037 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
19292038 assert(N == 3 && "Invalid number of operands!");
19302039 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
25222631 unsigned ShiftImm,
25232632 unsigned Alignment,
25242633 bool isNegative,
2525 SMLoc S, SMLoc E) {
2634 SMLoc S, SMLoc E,
2635 SMLoc AlignmentLoc = SMLoc()) {
25262636 ARMOperand *Op = new ARMOperand(k_Memory);
25272637 Op->Memory.BaseRegNum = BaseRegNum;
25282638 Op->Memory.OffsetImm = OffsetImm;
25332643 Op->Memory.isNegative = isNegative;
25342644 Op->StartLoc = S;
25352645 Op->EndLoc = E;
2646 Op->AlignmentLoc = AlignmentLoc;
25362647 return Op;
25372648 }
25382649
43454456 if (Parser.getTok().is(AsmToken::Colon)) {
43464457 Parser.Lex(); // Eat the ':'.
43474458 E = Parser.getTok().getLoc();
4459 SMLoc AlignmentLoc = Tok.getLoc();
43484460
43494461 const MCExpr *Expr;
43504462 if (getParser().parseExpression(Expr))
43794491 // the is*() predicates.
43804492 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
43814493 ARM_AM::no_shift, 0, Align,
4382 false, S, E));
4494 false, S, E, AlignmentLoc));
43834495
43844496 // If there's a pre-indexing writeback marker, '!', just add it as a token
43854497 // operand.
79668078 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
79678079 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
79688080 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8081 }
8082 case Match_AlignedMemoryRequiresNone:
8083 case Match_DupAlignedMemoryRequiresNone:
8084 case Match_AlignedMemoryRequires16:
8085 case Match_DupAlignedMemoryRequires16:
8086 case Match_AlignedMemoryRequires32:
8087 case Match_DupAlignedMemoryRequires32:
8088 case Match_AlignedMemoryRequires64:
8089 case Match_DupAlignedMemoryRequires64:
8090 case Match_AlignedMemoryRequires64or128:
8091 case Match_DupAlignedMemoryRequires64or128:
8092 case Match_AlignedMemoryRequires64or128or256:
8093 {
8094 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getAlignmentLoc();
8095 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8096 switch (MatchResult) {
8097 default:
8098 llvm_unreachable("Missing Match_Aligned type");
8099 case Match_AlignedMemoryRequiresNone:
8100 case Match_DupAlignedMemoryRequiresNone:
8101 return Error(ErrorLoc, "alignment must be omitted");
8102 case Match_AlignedMemoryRequires16:
8103 case Match_DupAlignedMemoryRequires16:
8104 return Error(ErrorLoc, "alignment must be 16 or omitted");
8105 case Match_AlignedMemoryRequires32:
8106 case Match_DupAlignedMemoryRequires32:
8107 return Error(ErrorLoc, "alignment must be 32 or omitted");
8108 case Match_AlignedMemoryRequires64:
8109 case Match_DupAlignedMemoryRequires64:
8110 return Error(ErrorLoc, "alignment must be 64 or omitted");
8111 case Match_AlignedMemoryRequires64or128:
8112 case Match_DupAlignedMemoryRequires64or128:
8113 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8114 case Match_AlignedMemoryRequires64or128or256:
8115 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8116 }
79698117 }
79708118 }
79718119
0 @ RUN: not llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s > %t 2> %e
1 @ RUN: FileCheck < %t %s
2 @ RUN: FileCheck --check-prefix=CHECK-ERRORS < %e %s
3
4 vld1.8 {d0}, [r4]
5 vld1.8 {d0}, [r4:16]
6 vld1.8 {d0}, [r4:32]
7 vld1.8 {d0}, [r4:64]
8 vld1.8 {d0}, [r4:128]
9 vld1.8 {d0}, [r4:256]
10
11 @ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07]
12 @ CHECK-ERRORS: error: alignment must be 64 or omitted
13 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]
14 @ CHECK-ERRORS: ^
15 @ CHECK-ERRORS: error: alignment must be 64 or omitted
16 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]
17 @ CHECK-ERRORS: ^
18 @ CHECK: vld1.8 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x07]
19 @ CHECK-ERRORS: error: alignment must be 64 or omitted
20 @ CHECK-ERRORS: vld1.8 {d0}, [r4:128]
21 @ CHECK-ERRORS: ^
22 @ CHECK-ERRORS: error: alignment must be 64 or omitted
23 @ CHECK-ERRORS: vld1.8 {d0}, [r4:256]
24 @ CHECK-ERRORS: ^
25
26 vld1.8 {d0}, [r4]!
27 vld1.8 {d0}, [r4:16]!
28 vld1.8 {d0}, [r4:32]!
29 vld1.8 {d0}, [r4:64]!
30 vld1.8 {d0}, [r4:128]!
31 vld1.8 {d0}, [r4:256]!
32
33 @ CHECK: vld1.8 {d0}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x07]
34 @ CHECK-ERRORS: error: alignment must be 64 or omitted
35 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]!
36 @ CHECK-ERRORS: ^
37 @ CHECK-ERRORS: error: alignment must be 64 or omitted
38 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]!
39 @ CHECK-ERRORS: ^
40 @ CHECK: vld1.8 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x07]
41 @ CHECK-ERRORS: error: alignment must be 64 or omitted
42 @ CHECK-ERRORS: vld1.8 {d0}, [r4:128]!
43 @ CHECK-ERRORS: ^
44 @ CHECK-ERRORS: error: alignment must be 64 or omitted
45 @ CHECK-ERRORS: vld1.8 {d0}, [r4:256]!
46 @ CHECK-ERRORS: ^
47
48 vld1.8 {d0}, [r4], r6
49 vld1.8 {d0}, [r4:16], r6
50 vld1.8 {d0}, [r4:32], r6
51 vld1.8 {d0}, [r4:64], r6
52 vld1.8 {d0}, [r4:128], r6
53 vld1.8 {d0}, [r4:256], r6
54
55 @ CHECK: vld1.8 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x07]
56 @ CHECK-ERRORS: error: alignment must be 64 or omitted
57 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16], r6
58 @ CHECK-ERRORS: ^
59 @ CHECK-ERRORS: error: alignment must be 64 or omitted
60 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32], r6
61 @ CHECK-ERRORS: ^
62 @ CHECK: vld1.8 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x07]
63 @ CHECK-ERRORS: error: alignment must be 64 or omitted
64 @ CHECK-ERRORS: vld1.8 {d0}, [r4:128], r6
65 @ CHECK-ERRORS: ^
66 @ CHECK-ERRORS: error: alignment must be 64 or omitted
67 @ CHECK-ERRORS: vld1.8 {d0}, [r4:256], r6
68 @ CHECK-ERRORS: ^
69
70 vld1.8 {d0, d1}, [r4]
71 vld1.8 {d0, d1}, [r4:16]
72 vld1.8 {d0, d1}, [r4:32]
73 vld1.8 {d0, d1}, [r4:64]
74 vld1.8 {d0, d1}, [r4:128]
75 vld1.8 {d0, d1}, [r4:256]
76
77 @ CHECK: vld1.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x0a]
78 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
79 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16]
80 @ CHECK-ERRORS: ^
81 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
82 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32]
83 @ CHECK-ERRORS: ^
84 @ CHECK: vld1.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x0a]
85 @ CHECK: vld1.8 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x0a]
86 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
87 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256]
88 @ CHECK-ERRORS: ^
89
90 vld1.8 {d0, d1}, [r4]!
91 vld1.8 {d0, d1}, [r4:16]!
92 vld1.8 {d0, d1}, [r4:32]!
93 vld1.8 {d0, d1}, [r4:64]!
94 vld1.8 {d0, d1}, [r4:128]!
95 vld1.8 {d0, d1}, [r4:256]!
96
97 @ CHECK: vld1.8 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x0a]
98 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
99 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16]!
100 @ CHECK-ERRORS: ^
101 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
102 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32]!
103 @ CHECK-ERRORS: ^
104 @ CHECK: vld1.8 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x0a]
105 @ CHECK: vld1.8 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x0a]
106 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
107 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256]!
108 @ CHECK-ERRORS: ^
109
110 vld1.8 {d0, d1}, [r4], r6
111 vld1.8 {d0, d1}, [r4:16], r6
112 vld1.8 {d0, d1}, [r4:32], r6
113 vld1.8 {d0, d1}, [r4:64], r6
114 vld1.8 {d0, d1}, [r4:128], r6
115 vld1.8 {d0, d1}, [r4:256], r6
116
117 @ CHECK: vld1.8 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x0a]
118 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
119 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16], r6
120 @ CHECK-ERRORS: ^
121 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
122 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32], r6
123 @ CHECK-ERRORS: ^
124 @ CHECK: vld1.8 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x0a]
125 @ CHECK: vld1.8 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x0a]
126 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
127 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256], r6
128 @ CHECK-ERRORS: ^
129
130 vld1.8 {d0, d1, d2}, [r4]
131 vld1.8 {d0, d1, d2}, [r4:16]
132 vld1.8 {d0, d1, d2}, [r4:32]
133 vld1.8 {d0, d1, d2}, [r4:64]
134 vld1.8 {d0, d1, d2}, [r4:128]
135 vld1.8 {d0, d1, d2}, [r4:256]
136
137 @ CHECK: vld1.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x06]
138 @ CHECK-ERRORS: error: alignment must be 64 or omitted
139 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16]
140 @ CHECK-ERRORS: ^
141 @ CHECK-ERRORS: error: alignment must be 64 or omitted
142 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32]
143 @ CHECK-ERRORS: ^
144 @ CHECK: vld1.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x06]
145 @ CHECK-ERRORS: error: alignment must be 64 or omitted
146 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128]
147 @ CHECK-ERRORS: ^
148 @ CHECK-ERRORS: error: alignment must be 64 or omitted
149 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256]
150 @ CHECK-ERRORS: ^
151
152 vld1.8 {d0, d1, d2}, [r4]!
153 vld1.8 {d0, d1, d2}, [r4:16]!
154 vld1.8 {d0, d1, d2}, [r4:32]!
155 vld1.8 {d0, d1, d2}, [r4:64]!
156 vld1.8 {d0, d1, d2}, [r4:128]!
157 vld1.8 {d0, d1, d2}, [r4:256]!
158
159 @ CHECK: vld1.8 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x06]
160 @ CHECK-ERRORS: error: alignment must be 64 or omitted
161 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16]!
162 @ CHECK-ERRORS: ^
163 @ CHECK-ERRORS: error: alignment must be 64 or omitted
164 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32]!
165 @ CHECK-ERRORS: ^
166 @ CHECK: vld1.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x06]
167 @ CHECK-ERRORS: error: alignment must be 64 or omitted
168 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128]!
169 @ CHECK-ERRORS: ^
170 @ CHECK-ERRORS: error: alignment must be 64 or omitted
171 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256]!
172 @ CHECK-ERRORS: ^
173
174 vld1.8 {d0, d1, d2}, [r4], r6
175 vld1.8 {d0, d1, d2}, [r4:16], r6
176 vld1.8 {d0, d1, d2}, [r4:32], r6
177 vld1.8 {d0, d1, d2}, [r4:64], r6
178 vld1.8 {d0, d1, d2}, [r4:128], r6
179 vld1.8 {d0, d1, d2}, [r4:256], r6
180
181 @ CHECK: vld1.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x06]
182 @ CHECK-ERRORS: error: alignment must be 64 or omitted
183 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16], r6
184 @ CHECK-ERRORS: ^
185 @ CHECK-ERRORS: error: alignment must be 64 or omitted
186 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32], r6
187 @ CHECK-ERRORS: ^
188 @ CHECK: vld1.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x06]
189 @ CHECK-ERRORS: error: alignment must be 64 or omitted
190 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128], r6
191 @ CHECK-ERRORS: ^
192 @ CHECK-ERRORS: error: alignment must be 64 or omitted
193 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256], r6
194 @ CHECK-ERRORS: ^
195
196 vld1.8 {d0, d1, d2, d3}, [r4]
197 vld1.8 {d0, d1, d2, d3}, [r4:16]
198 vld1.8 {d0, d1, d2, d3}, [r4:32]
199 vld1.8 {d0, d1, d2, d3}, [r4:64]
200 vld1.8 {d0, d1, d2, d3}, [r4:128]
201 vld1.8 {d0, d1, d2, d3}, [r4:256]
202
203 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x02]
204 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
205 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16]
206 @ CHECK-ERRORS: ^
207 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
208 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32]
209 @ CHECK-ERRORS: ^
210 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x02]
211 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x02]
212 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x3f,0x02]
213
214 vld1.8 {d0, d1, d2, d3}, [r4]!
215 vld1.8 {d0, d1, d2, d3}, [r4:16]!
216 vld1.8 {d0, d1, d2, d3}, [r4:32]!
217 vld1.8 {d0, d1, d2, d3}, [r4:64]!
218 vld1.8 {d0, d1, d2, d3}, [r4:128]!
219 vld1.8 {d0, d1, d2, d3}, [r4:256]!
220
221 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x02]
222 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
223 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16]!
224 @ CHECK-ERRORS: ^
225 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
226 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32]!
227 @ CHECK-ERRORS: ^
228 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x02]
229 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x02]
230 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x3d,0x02]
231
232 vld1.8 {d0, d1, d2, d3}, [r4], r6
233 vld1.8 {d0, d1, d2, d3}, [r4:16], r6
234 vld1.8 {d0, d1, d2, d3}, [r4:32], r6
235 vld1.8 {d0, d1, d2, d3}, [r4:64], r6
236 vld1.8 {d0, d1, d2, d3}, [r4:128], r6
237 vld1.8 {d0, d1, d2, d3}, [r4:256], r6
238
239 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x02]
240 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
241 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16], r6
242 @ CHECK-ERRORS: ^
243 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
244 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32], r6
245 @ CHECK-ERRORS: ^
246 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x02]
247 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x02]
248 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x36,0x02]
249
250 vld1.8 {d0[2]}, [r4]
251 vld1.8 {d0[2]}, [r4:16]
252 vld1.8 {d0[2]}, [r4:32]
253 vld1.8 {d0[2]}, [r4:64]
254 vld1.8 {d0[2]}, [r4:128]
255 vld1.8 {d0[2]}, [r4:256]
256
257 @ CHECK: vld1.8 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x00]
258 @ CHECK-ERRORS: error: alignment must be omitted
259 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16]
260 @ CHECK-ERRORS: ^
261 @ CHECK-ERRORS: error: alignment must be omitted
262 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32]
263 @ CHECK-ERRORS: ^
264 @ CHECK-ERRORS: error: alignment must be omitted
265 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64]
266 @ CHECK-ERRORS: ^
267 @ CHECK-ERRORS: error: alignment must be omitted
268 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128]
269 @ CHECK-ERRORS: ^
270 @ CHECK-ERRORS: error: alignment must be omitted
271 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256]
272 @ CHECK-ERRORS: ^
273
274 vld1.8 {d0[2]}, [r4]!
275 vld1.8 {d0[2]}, [r4:16]!
276 vld1.8 {d0[2]}, [r4:32]!
277 vld1.8 {d0[2]}, [r4:64]!
278 vld1.8 {d0[2]}, [r4:128]!
279 vld1.8 {d0[2]}, [r4:256]!
280
281 @ CHECK: vld1.8 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x00]
282 @ CHECK-ERRORS: error: alignment must be omitted
283 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16]!
284 @ CHECK-ERRORS: ^
285 @ CHECK-ERRORS: error: alignment must be omitted
286 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32]!
287 @ CHECK-ERRORS: ^
288 @ CHECK-ERRORS: error: alignment must be omitted
289 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64]!
290 @ CHECK-ERRORS: ^
291 @ CHECK-ERRORS: error: alignment must be omitted
292 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128]!
293 @ CHECK-ERRORS: ^
294 @ CHECK-ERRORS: error: alignment must be omitted
295 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256]!
296 @ CHECK-ERRORS: ^
297
298 vld1.8 {d0[2]}, [r4], r6
299 vld1.8 {d0[2]}, [r4:16], r6
300 vld1.8 {d0[2]}, [r4:32], r6
301 vld1.8 {d0[2]}, [r4:64], r6
302 vld1.8 {d0[2]}, [r4:128], r6
303 vld1.8 {d0[2]}, [r4:256], r6
304
305 @ CHECK: vld1.8 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x00]
306 @ CHECK-ERRORS: error: alignment must be omitted
307 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16], r6
308 @ CHECK-ERRORS: ^
309 @ CHECK-ERRORS: error: alignment must be omitted
310 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32], r6
311 @ CHECK-ERRORS: ^
312 @ CHECK-ERRORS: error: alignment must be omitted
313 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64], r6
314 @ CHECK-ERRORS: ^
315 @ CHECK-ERRORS: error: alignment must be omitted
316 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128], r6
317 @ CHECK-ERRORS: ^
318 @ CHECK-ERRORS: error: alignment must be omitted
319 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256], r6
320 @ CHECK-ERRORS: ^
321
322 vld1.8 {d0[]}, [r4]
323 vld1.8 {d0[]}, [r4:16]
324 vld1.8 {d0[]}, [r4:32]
325 vld1.8 {d0[]}, [r4:64]
326 vld1.8 {d0[]}, [r4:128]
327 vld1.8 {d0[]}, [r4:256]
328
329 @ CHECK: vld1.8 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0c]
330 @ CHECK-ERRORS: error: alignment must be omitted
331 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16]
332 @ CHECK-ERRORS: ^
333 @ CHECK-ERRORS: error: alignment must be omitted
334 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32]
335 @ CHECK-ERRORS: ^
336 @ CHECK-ERRORS: error: alignment must be omitted
337 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64]
338 @ CHECK-ERRORS: ^
339 @ CHECK-ERRORS: error: alignment must be omitted
340 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128]
341 @ CHECK-ERRORS: ^
342 @ CHECK-ERRORS: error: alignment must be omitted
343 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256]
344 @ CHECK-ERRORS: ^
345
346 vld1.8 {d0[]}, [r4]!
347 vld1.8 {d0[]}, [r4:16]!
348 vld1.8 {d0[]}, [r4:32]!
349 vld1.8 {d0[]}, [r4:64]!
350 vld1.8 {d0[]}, [r4:128]!
351 vld1.8 {d0[]}, [r4:256]!
352
353 @ CHECK: vld1.8 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0c]
354 @ CHECK-ERRORS: error: alignment must be omitted
355 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16]!
356 @ CHECK-ERRORS: ^
357 @ CHECK-ERRORS: error: alignment must be omitted
358 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32]!
359 @ CHECK-ERRORS: ^
360 @ CHECK-ERRORS: error: alignment must be omitted
361 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64]!
362 @ CHECK-ERRORS: ^
363 @ CHECK-ERRORS: error: alignment must be omitted
364 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128]!
365 @ CHECK-ERRORS: ^
366 @ CHECK-ERRORS: error: alignment must be omitted
367 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256]!
368 @ CHECK-ERRORS: ^
369
370 vld1.8 {d0[]}, [r4], r6
371 vld1.8 {d0[]}, [r4:16], r6
372 vld1.8 {d0[]}, [r4:32], r6
373 vld1.8 {d0[]}, [r4:64], r6
374 vld1.8 {d0[]}, [r4:128], r6
375 vld1.8 {d0[]}, [r4:256], r6
376
377 @ CHECK: vld1.8 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0c]
378 @ CHECK-ERRORS: error: alignment must be omitted
379 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16], r6
380 @ CHECK-ERRORS: ^
381 @ CHECK-ERRORS: error: alignment must be omitted
382 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32], r6
383 @ CHECK-ERRORS: ^
384 @ CHECK-ERRORS: error: alignment must be omitted
385 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64], r6
386 @ CHECK-ERRORS: ^
387 @ CHECK-ERRORS: error: alignment must be omitted
388 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128], r6
389 @ CHECK-ERRORS: ^
390 @ CHECK-ERRORS: error: alignment must be omitted
391 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256], r6
392 @ CHECK-ERRORS: ^
393
394 vld1.8 {d0[], d1[]}, [r4]
395 vld1.8 {d0[], d1[]}, [r4:16]
396 vld1.8 {d0[], d1[]}, [r4:32]
397 vld1.8 {d0[], d1[]}, [r4:64]
398 vld1.8 {d0[], d1[]}, [r4:128]
399 vld1.8 {d0[], d1[]}, [r4:256]
400
401 @ CHECK: vld1.8 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0c]
402 @ CHECK-ERRORS: error: alignment must be omitted
403 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16]
404 @ CHECK-ERRORS: ^
405 @ CHECK-ERRORS: error: alignment must be omitted
406 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32]
407 @ CHECK-ERRORS: ^
408 @ CHECK-ERRORS: error: alignment must be omitted
409 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64]
410 @ CHECK-ERRORS: ^
411 @ CHECK-ERRORS: error: alignment must be omitted
412 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128]
413 @ CHECK-ERRORS: ^
414 @ CHECK-ERRORS: error: alignment must be omitted
415 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256]
416 @ CHECK-ERRORS: ^
417
418 vld1.8 {d0[], d1[]}, [r4]!
419 vld1.8 {d0[], d1[]}, [r4:16]!
420 vld1.8 {d0[], d1[]}, [r4:32]!
421 vld1.8 {d0[], d1[]}, [r4:64]!
422 vld1.8 {d0[], d1[]}, [r4:128]!
423 vld1.8 {d0[], d1[]}, [r4:256]!
424
425 @ CHECK: vld1.8 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0c]
426 @ CHECK-ERRORS: error: alignment must be omitted
427 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16]!
428 @ CHECK-ERRORS: ^
429 @ CHECK-ERRORS: error: alignment must be omitted
430 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32]!
431 @ CHECK-ERRORS: ^
432 @ CHECK-ERRORS: error: alignment must be omitted
433 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64]!
434 @ CHECK-ERRORS: ^
435 @ CHECK-ERRORS: error: alignment must be omitted
436 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128]!
437 @ CHECK-ERRORS: ^
438 @ CHECK-ERRORS: error: alignment must be omitted
439 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256]!
440 @ CHECK-ERRORS: ^
441
442 vld1.8 {d0[], d1[]}, [r4], r6
443 vld1.8 {d0[], d1[]}, [r4:16], r6
444 vld1.8 {d0[], d1[]}, [r4:32], r6
445 vld1.8 {d0[], d1[]}, [r4:64], r6
446 vld1.8 {d0[], d1[]}, [r4:128], r6
447 vld1.8 {d0[], d1[]}, [r4:256], r6
448
449 @ CHECK: vld1.8 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0c]
450 @ CHECK-ERRORS: error: alignment must be omitted
451 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16], r6
452 @ CHECK-ERRORS: ^
453 @ CHECK-ERRORS: error: alignment must be omitted
454 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32], r6
455 @ CHECK-ERRORS: ^
456 @ CHECK-ERRORS: error: alignment must be omitted
457 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64], r6
458 @ CHECK-ERRORS: ^
459 @ CHECK-ERRORS: error: alignment must be omitted
460 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128], r6
461 @ CHECK-ERRORS: ^
462 @ CHECK-ERRORS: error: alignment must be omitted
463 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256], r6
464 @ CHECK-ERRORS: ^
465
466 vld1.16 {d0}, [r4]
467 vld1.16 {d0}, [r4:16]
468 vld1.16 {d0}, [r4:32]
469 vld1.16 {d0}, [r4:64]
470 vld1.16 {d0}, [r4:128]
471 vld1.16 {d0}, [r4:256]
472
473 @ CHECK: vld1.16 {d0}, [r4] @ encoding: [0x24,0xf9,0x4f,0x07]
474 @ CHECK-ERRORS: error: alignment must be 64 or omitted
475 @ CHECK-ERRORS: vld1.16 {d0}, [r4:16]
476 @ CHECK-ERRORS: ^
477 @ CHECK-ERRORS: error: alignment must be 64 or omitted
478 @ CHECK-ERRORS: vld1.16 {d0}, [r4:32]
479 @ CHECK-ERRORS: ^
480 @ CHECK: vld1.16 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x07]
481 @ CHECK-ERRORS: error: alignment must be 64 or omitted
482 @ CHECK-ERRORS: vld1.16 {d0}, [r4:128]
483 @ CHECK-ERRORS: ^
484 @ CHECK-ERRORS: error: alignment must be 64 or omitted
485 @ CHECK-ERRORS: vld1.16 {d0}, [r4:256]
486 @ CHECK-ERRORS: ^
487
488 vld1.16 {d0}, [r4]!
489 vld1.16 {d0}, [r4:16]!
490 vld1.16 {d0}, [r4:32]!
491 vld1.16 {d0}, [r4:64]!
492 vld1.16 {d0}, [r4:128]!
493 vld1.16 {d0}, [r4:256]!
494
495 @ CHECK: vld1.16 {d0}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x07]
496 @ CHECK-ERRORS: error: alignment must be 64 or omitted
497 @ CHECK-ERRORS: vld1.16 {d0}, [r4:16]!
498 @ CHECK-ERRORS: ^
499 @ CHECK-ERRORS: error: alignment must be 64 or omitted
500 @ CHECK-ERRORS: vld1.16 {d0}, [r4:32]!
501 @ CHECK-ERRORS: ^
502 @ CHECK: vld1.16 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x07]
503 @ CHECK-ERRORS: error: alignment must be 64 or omitted
504 @ CHECK-ERRORS: vld1.16 {d0}, [r4:128]!
505 @ CHECK-ERRORS: ^
506 @ CHECK-ERRORS: error: alignment must be 64 or omitted
507 @ CHECK-ERRORS: vld1.16 {d0}, [r4:256]!
508 @ CHECK-ERRORS: ^
509
510 vld1.16 {d0}, [r4], r6
511 vld1.16 {d0}, [r4:16], r6
512 vld1.16 {d0}, [r4:32], r6
513 vld1.16 {d0}, [r4:64], r6
514 vld1.16 {d0}, [r4:128], r6
515 vld1.16 {d0}, [r4:256], r6
516
517 @ CHECK: vld1.16 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x07]
518 @ CHECK-ERRORS: error: alignment must be 64 or omitted
519 @ CHECK-ERRORS: vld1.16 {d0}, [r4:16], r6
520 @ CHECK-ERRORS: ^
521 @ CHECK-ERRORS: error: alignment must be 64 or omitted
522 @ CHECK-ERRORS: vld1.16 {d0}, [r4:32], r6
523 @ CHECK-ERRORS: ^
524 @ CHECK: vld1.16 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x07]
525 @ CHECK-ERRORS: error: alignment must be 64 or omitted
526 @ CHECK-ERRORS: vld1.16 {d0}, [r4:128], r6
527 @ CHECK-ERRORS: ^
528 @ CHECK-ERRORS: error: alignment must be 64 or omitted
529 @ CHECK-ERRORS: vld1.16 {d0}, [r4:256], r6
530 @ CHECK-ERRORS: ^
531
532 vld1.16 {d0, d1}, [r4]
533 vld1.16 {d0, d1}, [r4:16]
534 vld1.16 {d0, d1}, [r4:32]
535 vld1.16 {d0, d1}, [r4:64]
536 vld1.16 {d0, d1}, [r4:128]
537 vld1.16 {d0, d1}, [r4:256]
538
539 @ CHECK: vld1.16 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x4f,0x0a]
540 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
541 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16]
542 @ CHECK-ERRORS: ^
543 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
544 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32]
545 @ CHECK-ERRORS: ^
546 @ CHECK: vld1.16 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x0a]
547 @ CHECK: vld1.16 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x0a]
548 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
549 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256]
550 @ CHECK-ERRORS: ^
551
552 vld1.16 {d0, d1}, [r4]!
553 vld1.16 {d0, d1}, [r4:16]!
554 vld1.16 {d0, d1}, [r4:32]!
555 vld1.16 {d0, d1}, [r4:64]!
556 vld1.16 {d0, d1}, [r4:128]!
557 vld1.16 {d0, d1}, [r4:256]!
558
559 @ CHECK: vld1.16 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x0a]
560 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
561 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16]!
562 @ CHECK-ERRORS: ^
563 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
564 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32]!
565 @ CHECK-ERRORS: ^
566 @ CHECK: vld1.16 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x0a]
567 @ CHECK: vld1.16 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x0a]
568 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
569 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256]!
570 @ CHECK-ERRORS: ^
571
572 vld1.16 {d0, d1}, [r4], r6
573 vld1.16 {d0, d1}, [r4:16], r6
574 vld1.16 {d0, d1}, [r4:32], r6
575 vld1.16 {d0, d1}, [r4:64], r6
576 vld1.16 {d0, d1}, [r4:128], r6
577 vld1.16 {d0, d1}, [r4:256], r6
578
579 @ CHECK: vld1.16 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x0a]
580 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
581 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16], r6
582 @ CHECK-ERRORS: ^
583 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
584 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32], r6
585 @ CHECK-ERRORS: ^
586 @ CHECK: vld1.16 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x0a]
587 @ CHECK: vld1.16 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x0a]
588 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
589 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256], r6
590 @ CHECK-ERRORS: ^
591
592 vld1.16 {d0, d1, d2}, [r4]
593 vld1.16 {d0, d1, d2}, [r4:16]
594 vld1.16 {d0, d1, d2}, [r4:32]
595 vld1.16 {d0, d1, d2}, [r4:64]
596 vld1.16 {d0, d1, d2}, [r4:128]
597 vld1.16 {d0, d1, d2}, [r4:256]
598
599 @ CHECK: vld1.16 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x06]
600 @ CHECK-ERRORS: error: alignment must be 64 or omitted
601 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16]
602 @ CHECK-ERRORS: ^
603 @ CHECK-ERRORS: error: alignment must be 64 or omitted
604 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32]
605 @ CHECK-ERRORS: ^
606 @ CHECK: vld1.16 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x06]
607 @ CHECK-ERRORS: error: alignment must be 64 or omitted
608 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128]
609 @ CHECK-ERRORS: ^
610 @ CHECK-ERRORS: error: alignment must be 64 or omitted
611 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256]
612 @ CHECK-ERRORS: ^
613
614 vld1.16 {d0, d1, d2}, [r4]!
615 vld1.16 {d0, d1, d2}, [r4:16]!
616 vld1.16 {d0, d1, d2}, [r4:32]!
617 vld1.16 {d0, d1, d2}, [r4:64]!
618 vld1.16 {d0, d1, d2}, [r4:128]!
619 vld1.16 {d0, d1, d2}, [r4:256]!
620
621 @ CHECK: vld1.16 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x06]
622 @ CHECK-ERRORS: error: alignment must be 64 or omitted
623 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16]!
624 @ CHECK-ERRORS: ^
625 @ CHECK-ERRORS: error: alignment must be 64 or omitted
626 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32]!
627 @ CHECK-ERRORS: ^
628 @ CHECK: vld1.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x06]
629 @ CHECK-ERRORS: error: alignment must be 64 or omitted
630 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128]!
631 @ CHECK-ERRORS: ^
632 @ CHECK-ERRORS: error: alignment must be 64 or omitted
633 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256]!
634 @ CHECK-ERRORS: ^
635
636 vld1.16 {d0, d1, d2}, [r4], r6
637 vld1.16 {d0, d1, d2}, [r4:16], r6
638 vld1.16 {d0, d1, d2}, [r4:32], r6
639 vld1.16 {d0, d1, d2}, [r4:64], r6
640 vld1.16 {d0, d1, d2}, [r4:128], r6
641 vld1.16 {d0, d1, d2}, [r4:256], r6
642
643 @ CHECK: vld1.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x06]
644 @ CHECK-ERRORS: error: alignment must be 64 or omitted
645 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16], r6
646 @ CHECK-ERRORS: ^
647 @ CHECK-ERRORS: error: alignment must be 64 or omitted
648 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32], r6
649 @ CHECK-ERRORS: ^
650 @ CHECK: vld1.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x06]
651 @ CHECK-ERRORS: error: alignment must be 64 or omitted
652 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128], r6
653 @ CHECK-ERRORS: ^
654 @ CHECK-ERRORS: error: alignment must be 64 or omitted
655 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256], r6
656 @ CHECK-ERRORS: ^
657
658 vld1.16 {d0, d1, d2, d3}, [r4]
659 vld1.16 {d0, d1, d2, d3}, [r4:16]
660 vld1.16 {d0, d1, d2, d3}, [r4:32]
661 vld1.16 {d0, d1, d2, d3}, [r4:64]
662 vld1.16 {d0, d1, d2, d3}, [r4:128]
663 vld1.16 {d0, d1, d2, d3}, [r4:256]
664
665 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x02]
666 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
667 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16]
668 @ CHECK-ERRORS: ^
669 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
670 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32]
671 @ CHECK-ERRORS: ^
672 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x02]
673 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x02]
674 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x7f,0x02]
675
676 vld1.16 {d0, d1, d2, d3}, [r4]!
677 vld1.16 {d0, d1, d2, d3}, [r4:16]!
678 vld1.16 {d0, d1, d2, d3}, [r4:32]!
679 vld1.16 {d0, d1, d2, d3}, [r4:64]!
680 vld1.16 {d0, d1, d2, d3}, [r4:128]!
681 vld1.16 {d0, d1, d2, d3}, [r4:256]!
682
683 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x02]
684 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16]!
685 @ CHECK-ERRORS: ^
686 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
687 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32]!
688 @ CHECK-ERRORS: ^
689 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x02]
690 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x02]
691 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x7d,0x02]
692
693 vld1.16 {d0, d1, d2, d3}, [r4], r6
694 vld1.16 {d0, d1, d2, d3}, [r4:16], r6
695 vld1.16 {d0, d1, d2, d3}, [r4:32], r6
696 vld1.16 {d0, d1, d2, d3}, [r4:64], r6
697 vld1.16 {d0, d1, d2, d3}, [r4:128], r6
698 vld1.16 {d0, d1, d2, d3}, [r4:256], r6
699
700 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x02]
701 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
702 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16], r6
703 @ CHECK-ERRORS: ^
704 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
705 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32], r6
706 @ CHECK-ERRORS: ^
707 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x02]
708 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x02]
709 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x76,0x02]
710
711 vld1.16 {d0[2]}, [r4]
712 vld1.16 {d0[2]}, [r4:16]
713 vld1.16 {d0[2]}, [r4:32]
714 vld1.16 {d0[2]}, [r4:64]
715 vld1.16 {d0[2]}, [r4:128]
716 vld1.16 {d0[2]}, [r4:256]
717
718 @ CHECK: vld1.16 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x04]
719 @ CHECK: vld1.16 {d0[2]}, [r4:16] @ encoding: [0xa4,0xf9,0x9f,0x04]
720 @ CHECK-ERRORS: error: alignment must be 16 or omitted
721 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32]
722 @ CHECK-ERRORS: ^
723 @ CHECK-ERRORS: error: alignment must be 16 or omitted
724 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64]
725 @ CHECK-ERRORS: ^
726 @ CHECK-ERRORS: error: alignment must be 16 or omitted
727 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128]
728 @ CHECK-ERRORS: ^
729 @ CHECK-ERRORS: error: alignment must be 16 or omitted
730 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256]
731 @ CHECK-ERRORS: ^
732
733 vld1.16 {d0[2]}, [r4]!
734 vld1.16 {d0[2]}, [r4:16]!
735 vld1.16 {d0[2]}, [r4:32]!
736 vld1.16 {d0[2]}, [r4:64]!
737 vld1.16 {d0[2]}, [r4:128]!
738 vld1.16 {d0[2]}, [r4:256]!
739
740 @ CHECK: vld1.16 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x04]
741 @ CHECK: vld1.16 {d0[2]}, [r4:16]! @ encoding: [0xa4,0xf9,0x9d,0x04]
742 @ CHECK-ERRORS: error: alignment must be 16 or omitted
743 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32]!
744 @ CHECK-ERRORS: ^
745 @ CHECK-ERRORS: error: alignment must be 16 or omitted
746 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64]!
747 @ CHECK-ERRORS: ^
748 @ CHECK-ERRORS: error: alignment must be 16 or omitted
749 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128]!
750 @ CHECK-ERRORS: ^
751 @ CHECK-ERRORS: error: alignment must be 16 or omitted
752 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256]!
753 @ CHECK-ERRORS: ^
754
755 vld1.16 {d0[2]}, [r4], r6
756 vld1.16 {d0[2]}, [r4:16], r6
757 vld1.16 {d0[2]}, [r4:32], r6
758 vld1.16 {d0[2]}, [r4:64], r6
759 vld1.16 {d0[2]}, [r4:128], r6
760 vld1.16 {d0[2]}, [r4:256], r6
761
762 @ CHECK: vld1.16 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x04]
763 @ CHECK: vld1.16 {d0[2]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x96,0x04]
764 @ CHECK-ERRORS: error: alignment must be 16 or omitted
765 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32], r6
766 @ CHECK-ERRORS: ^
767 @ CHECK-ERRORS: error: alignment must be 16 or omitted
768 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64], r6
769 @ CHECK-ERRORS: ^
770 @ CHECK-ERRORS: error: alignment must be 16 or omitted
771 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128], r6
772 @ CHECK-ERRORS: ^
773 @ CHECK-ERRORS: error: alignment must be 16 or omitted
774 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256], r6
775 @ CHECK-ERRORS: ^
776
777 vld1.16 {d0[]}, [r4]
778 vld1.16 {d0[]}, [r4:16]
779 vld1.16 {d0[]}, [r4:32]
780 vld1.16 {d0[]}, [r4:64]
781 vld1.16 {d0[]}, [r4:128]
782 vld1.16 {d0[]}, [r4:256]
783
784 @ CHECK: vld1.16 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0c]
785 @ CHECK: vld1.16 {d0[]}, [r4:16] @ encoding: [0xa4,0xf9,0x5f,0x0c]
786 @ CHECK-ERRORS: error: alignment must be 16 or omitted
787 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32]
788 @ CHECK-ERRORS: ^
789 @ CHECK-ERRORS: error: alignment must be 16 or omitted
790 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64]
791 @ CHECK-ERRORS: ^
792 @ CHECK-ERRORS: error: alignment must be 16 or omitted
793 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128]
794 @ CHECK-ERRORS: ^
795 @ CHECK-ERRORS: error: alignment must be 16 or omitted
796 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256]
797 @ CHECK-ERRORS: ^
798
799 vld1.16 {d0[]}, [r4]!
800 vld1.16 {d0[]}, [r4:16]!
801 vld1.16 {d0[]}, [r4:32]!
802 vld1.16 {d0[]}, [r4:64]!
803 vld1.16 {d0[]}, [r4:128]!
804 vld1.16 {d0[]}, [r4:256]!
805
806 @ CHECK: vld1.16 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0c]
807 @ CHECK: vld1.16 {d0[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x5d,0x0c]
808 @ CHECK-ERRORS: error: alignment must be 16 or omitted
809 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32]!
810 @ CHECK-ERRORS: ^
811 @