llvm.org GIT mirror llvm / e7e7d0d
Skeleton of post-RA scheduler; doesn't do anything yet. Change name of -sched option and DEBUG_TYPE to pre-RA-sched; adjust testcases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8 Dale Johannesen 12 years ago
11 changed file(s) with 106 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
8888 ///
8989 FunctionPass *createPrologEpilogCodeInserter();
9090
91 /// createPostRAScheduler - under development.
92 FunctionPass *createPostRAScheduler();
93
9194 /// BranchFolding Pass - This pass performs machine code CFG based
9295 /// optimizations to delete branches to branches, eliminate branches to
9396 /// successor blocks (creating fall throughs), and eliminating branches over
7777 // Insert prolog/epilog code. Eliminate abstract frame index references...
7878 PM.add(createPrologEpilogCodeInserter());
7979
80 // Second pass scheduler.
81 PM.add(createPostRAScheduler());
82
8083 // Branch folding must be run after regalloc and prolog/epilog insertion.
8184 if (!Fast)
8285 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
180183 if (PrintMachineCode) // Print the register-allocated code
181184 PM.add(createMachineFunctionPrinterPass(cerr));
182185
186 // Second pass scheduler.
187 PM.add(createPostRAScheduler());
188
183189 // Branch folding must be run after regalloc and prolog/epilog insertion.
184190 if (!Fast)
185191 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
0 //===----- SchedulePostRAList.cpp - list scheduler ----===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by Dale Johannesen and is distributed under the
5 // University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements a top-down list scheduler, using standard algorithms.
10 // The basic approach uses a priority queue of available nodes to schedule.
11 // One at a time, nodes are taken from the priority queue (thus in priority
12 // order), checked for legality to schedule, and emitted if legal.
13 //
14 // Nodes may not be legal to schedule either due to structural hazards (e.g.
15 // pipeline or resource constraints) or because an input to the instruction has
16 // not completed execution.
17 //
18 //===----------------------------------------------------------------------===//
19
20 #define DEBUG_TYPE "post-RA-sched"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/Support/Debug.h"
24 //#include "llvm/ADT/Statistic.h"
25 //#include
26 //#include
27 #include "llvm/Support/CommandLine.h"
28 using namespace llvm;
29
30 namespace {
31 bool NoPostRAScheduling;
32
33 // When this works it will be on by default.
34 cl::opt
35 DisablePostRAScheduler("disable-post-RA-scheduler",
36 cl::desc("Disable scheduling after register allocation"),
37 cl::location(NoPostRAScheduling),
38 cl::init(true));
39
40 class VISIBILITY_HIDDEN SchedulePostRATDList : public MachineFunctionPass {
41 public:
42 static char ID;
43 SchedulePostRATDList() : MachineFunctionPass((intptr_t)&ID) {}
44 private:
45 MachineFunction *MF;
46 const TargetMachine *TM;
47 public:
48 const char *getPassName() const {
49 return "Post RA top-down list latency scheduler (STUB)";
50 }
51
52 bool runOnMachineFunction(MachineFunction &Fn);
53 };
54 char SchedulePostRATDList::ID = 0;
55 }
56
57 bool SchedulePostRATDList::runOnMachineFunction(MachineFunction &Fn) {
58 if (NoPostRAScheduling)
59 return true;
60
61 DOUT << "SchedulePostRATDList\n";
62 MF = &Fn;
63 TM = &MF->getTarget();
64
65 // Loop over all of the basic blocks
66 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
67 MBB != MBBe; ++MBB)
68 ;
69
70 return true;
71 }
72
73
74 //===----------------------------------------------------------------------===//
75 // Public Constructor Functions
76 //===----------------------------------------------------------------------===//
77
78 FunctionPass *llvm::createPostRAScheduler() {
79 return new SchedulePostRATDList();
80 }
1212 //
1313 //===----------------------------------------------------------------------===//
1414
15 #define DEBUG_TYPE "sched"
15 #define DEBUG_TYPE "pre-RA-sched"
1616 #include "llvm/Type.h"
1717 #include "llvm/CodeGen/ScheduleDAG.h"
1818 #include "llvm/CodeGen/MachineConstantPool.h"
1717 //
1818 //===----------------------------------------------------------------------===//
1919
20 #define DEBUG_TYPE "sched"
20 #define DEBUG_TYPE "pre-RA-sched"
2121 #include "llvm/CodeGen/ScheduleDAG.h"
2222 #include "llvm/CodeGen/SchedulerRegistry.h"
2323 #include "llvm/CodeGen/SelectionDAGISel.h"
1414 //
1515 //===----------------------------------------------------------------------===//
1616
17 #define DEBUG_TYPE "sched"
17 #define DEBUG_TYPE "pre-RA-sched"
1818 #include "llvm/CodeGen/ScheduleDAG.h"
1919 #include "llvm/CodeGen/SchedulerRegistry.h"
2020 #include "llvm/CodeGen/SSARegMap.h"
1212 //
1313 //===----------------------------------------------------------------------===//
1414
15 #define DEBUG_TYPE "sched"
15 #define DEBUG_TYPE "pre-RA-sched"
1616 #include "llvm/CodeGen/MachineFunction.h"
1717 #include "llvm/CodeGen/ScheduleDAG.h"
1818 #include "llvm/CodeGen/SchedulerRegistry.h"
7272 namespace {
7373 cl::opt
7474 RegisterPassParser >
75 ISHeuristic("sched",
75 ISHeuristic("pre-RA-sched",
7676 cl::init(&createDefaultScheduler),
77 cl::desc("Instruction schedulers available:"));
77 cl::desc("Instruction schedulers available (before register allocation):"));
7878
7979 static RegisterScheduler
8080 defaultListDAGScheduler("default", " Best scheduler for the target",
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #define DEBUG_TYPE "sched"
13 #define DEBUG_TYPE "pre-RA-sched"
1414 #include "PPCHazardRecognizers.h"
1515 #include "PPC.h"
1616 #include "PPCInstrInfo.h"
None ; RUN: llvm-upgrade %s | llvm-as | llc -sched=none
1 ; RUN: llvm-upgrade %s | llvm-as | llc -sched=default
2 ; RUN: llvm-upgrade %s | llvm-as | llc -sched=simple
3 ; RUN: llvm-upgrade %s | llvm-as | llc -sched=simple-noitin
4 ; RUN: llvm-upgrade %s | llvm-as | llc -sched=list-td
5 ; RUN: llvm-upgrade %s | llvm-as | llc -sched=list-tdrr
6 ; RUN: llvm-upgrade %s | llvm-as | llc -sched=list-burr
0 ; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=none
1 ; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=default
2 ; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=simple
3 ; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=simple-noitin
4 ; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=list-td
5 ; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=list-tdrr
6 ; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=list-burr
77 ; PR859
88
99 implementation
None ; RUN: llvm-as < %s | llc -march=x86-64 -sched=none | grep leaq
1 ; RUN: llvm-as < %s | llc -march=x86-64 -sched=none | not grep {,%rsp)}
0 ; RUN: llvm-as < %s | llc -march=x86-64 -pre-RA-sched=none | grep leaq
1 ; RUN: llvm-as < %s | llc -march=x86-64 -pre-RA-sched=none | not grep {,%rsp)}
22 ; PR1103
33
44 target datalayout = "e-p:64:64"