llvm.org GIT mirror llvm / e7c1416
Now that register allocation properly considers reserved regs, simplify the ARM register class allocation order functions to take advantage of that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 10 years ago
5 changed file(s) with 29 addition(s) and 165 deletion(s). Raw diff Collapse all Expand all
219219 iterator allocation_order_end(const MachineFunction &MF) const;
220220 }];
221221 let MethodBodies = [{
222 // FP is R11, R9 is available.
223 static const unsigned ARM_GPR_AO_1[] = {
222 static const unsigned ARM_GPR_AO[] = {
224223 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
225224 ARM::R12,ARM::LR,
226225 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
227 ARM::R8, ARM::R9, ARM::R10,
228 ARM::R11 };
229 // FP is R11, R9 is not available.
230 static const unsigned ARM_GPR_AO_2[] = {
231 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
232 ARM::R12,ARM::LR,
233 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
234 ARM::R8, ARM::R10,
235 ARM::R11 };
236 // FP is R7, R9 is available as non-callee-saved register.
237 // This is used by Darwin.
238 static const unsigned ARM_GPR_AO_3[] = {
239 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
240 ARM::R9, ARM::R12,ARM::LR,
241 ARM::R4, ARM::R5, ARM::R6,
242 ARM::R8, ARM::R10,ARM::R11,ARM::R7 };
243 // FP is R7, R9 is not available.
244 static const unsigned ARM_GPR_AO_4[] = {
245 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
246 ARM::R12,ARM::LR,
247 ARM::R4, ARM::R5, ARM::R6,
248 ARM::R8, ARM::R10,ARM::R11,
249 ARM::R7 };
250 // FP is R7, R9 is available as callee-saved register.
251 // This is used by non-Darwin platform in Thumb mode.
252 static const unsigned ARM_GPR_AO_5[] = {
253 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
254 ARM::R12,ARM::LR,
255 ARM::R4, ARM::R5, ARM::R6,
256 ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
226 ARM::R8, ARM::R9, ARM::R10, ARM::R11 };
257227
258228 // For Thumb1 mode, we don't want to allocate hi regs at all, as we
259229 // don't know how to spill them. If we make our prologue/epilogue code
269239 const ARMSubtarget &Subtarget = TM.getSubtarget();
270240 if (Subtarget.isThumb1Only())
271241 return THUMB_GPR_AO;
272 if (Subtarget.isTargetDarwin()) {
273 if (Subtarget.isR9Reserved())
274 return ARM_GPR_AO_4;
275 else
276 return ARM_GPR_AO_3;
277 } else {
278 if (Subtarget.isR9Reserved())
279 return ARM_GPR_AO_2;
280 else if (Subtarget.isThumb())
281 return ARM_GPR_AO_5;
282 else
283 return ARM_GPR_AO_1;
284 }
242 return ARM_GPR_AO;
285243 }
286244
287245 GPRClass::iterator
288246 GPRClass::allocation_order_end(const MachineFunction &MF) const {
289247 const TargetMachine &TM = MF.getTarget();
290 const TargetRegisterInfo *RI = TM.getRegisterInfo();
291 const ARMSubtarget &Subtarget = TM.getSubtarget();
292 GPRClass::iterator I;
293
294 if (Subtarget.isThumb1Only()) {
295 I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
296 return RI->hasFP(MF) ? I-1 : I;
297 }
298
299 if (Subtarget.isTargetDarwin()) {
300 if (Subtarget.isR9Reserved())
301 I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
302 else
303 I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
304 } else {
305 if (Subtarget.isR9Reserved())
306 I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
307 else if (Subtarget.isThumb())
308 I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
309 else
310 I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
311 }
312
313 return RI->hasFP(MF) ? I-1 : I;
248 const ARMSubtarget &Subtarget = TM.getSubtarget();
249 if (Subtarget.isThumb1Only())
250 return THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
251 return ARM_GPR_AO + (sizeof(ARM_GPR_AO)/sizeof(unsigned));
314252 }
315253 }];
316254 }
326264 iterator allocation_order_end(const MachineFunction &MF) const;
327265 }];
328266 let MethodBodies = [{
329 // FP is R11, R9 is available.
330 static const unsigned ARM_rGPRAO_1[] = {
267 static const unsigned ARM_rGPR_AO[] = {
331268 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
332269 ARM::R12,ARM::LR,
333270 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
334271 ARM::R8, ARM::R9, ARM::R10,
335272 ARM::R11 };
336 // FP is R11, R9 is not available.
337 static const unsigned ARM_rGPRAO_2[] = {
338 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
339 ARM::R12,ARM::LR,
340 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
341 ARM::R8, ARM::R10,
342 ARM::R11 };
343 // FP is R7, R9 is available as non-callee-saved register.
344 // This is used by Darwin.
345 static const unsigned ARM_rGPRAO_3[] = {
346 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
347 ARM::R9, ARM::R12,ARM::LR,
348 ARM::R4, ARM::R5, ARM::R6,
349 ARM::R8, ARM::R10,ARM::R11,ARM::R7 };
350 // FP is R7, R9 is not available.
351 static const unsigned ARM_rGPRAO_4[] = {
352 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
353 ARM::R12,ARM::LR,
354 ARM::R4, ARM::R5, ARM::R6,
355 ARM::R8, ARM::R10,ARM::R11,
356 ARM::R7 };
357 // FP is R7, R9 is available as callee-saved register.
358 // This is used by non-Darwin platform in Thumb mode.
359 static const unsigned ARM_rGPRAO_5[] = {
360 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
361 ARM::R12,ARM::LR,
362 ARM::R4, ARM::R5, ARM::R6,
363 ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
364273
365274 // For Thumb1 mode, we don't want to allocate hi regs at all, as we
366275 // don't know how to spill them. If we make our prologue/epilogue code
367276 // smarter at some point, we can go back to using the above allocation
368277 // orders for the Thumb1 instructions that know how to use hi regs.
369 static const unsigned THUMB_rGPRAO[] = {
278 static const unsigned THUMB_rGPR_AO[] = {
370279 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
371280 ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
372281
375284 const TargetMachine &TM = MF.getTarget();
376285 const ARMSubtarget &Subtarget = TM.getSubtarget();
377286 if (Subtarget.isThumb1Only())
378 return THUMB_rGPRAO;
379 if (Subtarget.isTargetDarwin()) {
380 if (Subtarget.isR9Reserved())
381 return ARM_rGPRAO_4;
382 else
383 return ARM_rGPRAO_3;
384 } else {
385 if (Subtarget.isR9Reserved())
386 return ARM_rGPRAO_2;
387 else if (Subtarget.isThumb())
388 return ARM_rGPRAO_5;
389 else
390 return ARM_rGPRAO_1;
391 }
287 return THUMB_rGPR_AO;
288 return ARM_rGPR_AO;
392289 }
393290
394291 rGPRClass::iterator
395292 rGPRClass::allocation_order_end(const MachineFunction &MF) const {
396293 const TargetMachine &TM = MF.getTarget();
397 const TargetRegisterInfo *RI = TM.getRegisterInfo();
398 const ARMSubtarget &Subtarget = TM.getSubtarget();
399 GPRClass::iterator I;
400
401 if (Subtarget.isThumb1Only()) {
402 I = THUMB_rGPRAO + (sizeof(THUMB_rGPRAO)/sizeof(unsigned));
403 return RI->hasFP(MF) ? I-1 : I;
404 }
405
406 if (Subtarget.isTargetDarwin()) {
407 if (Subtarget.isR9Reserved())
408 I = ARM_rGPRAO_4 + (sizeof(ARM_rGPRAO_4)/sizeof(unsigned));
409 else
410 I = ARM_rGPRAO_3 + (sizeof(ARM_rGPRAO_3)/sizeof(unsigned));
411 } else {
412 if (Subtarget.isR9Reserved())
413 I = ARM_rGPRAO_2 + (sizeof(ARM_rGPRAO_2)/sizeof(unsigned));
414 else if (Subtarget.isThumb())
415 I = ARM_rGPRAO_5 + (sizeof(ARM_rGPRAO_5)/sizeof(unsigned));
416 else
417 I = ARM_rGPRAO_1 + (sizeof(ARM_rGPRAO_1)/sizeof(unsigned));
418 }
419
420 return RI->hasFP(MF) ? I-1 : I;
294 const ARMSubtarget &Subtarget = TM.getSubtarget();
295
296 if (Subtarget.isThumb1Only())
297 return THUMB_rGPR_AO + (sizeof(THUMB_rGPR_AO)/sizeof(unsigned));
298 return ARM_rGPR_AO + (sizeof(ARM_rGPR_AO)/sizeof(unsigned));
421299 }
422300 }];
423301 }
458336 const ARMSubtarget &Subtarget = TM.getSubtarget();
459337 if (Subtarget.isThumb1Only())
460338 return THUMB_GPR_AO_TC;
461 if (Subtarget.isTargetDarwin()) {
462 if (Subtarget.isR9Reserved())
463 return ARM_GPR_NOR9_TC;
464 else
465 return ARM_GPR_R9_TC;
466 } else
467 // R9 is either callee-saved or reserved; can't use it.
468 return ARM_GPR_NOR9_TC;
339 return Subtarget.isTargetDarwin() ? ARM_GPR_R9_TC : ARM_GPR_NOR9_TC;
469340 }
470341
471342 tcGPRClass::iterator
472343 tcGPRClass::allocation_order_end(const MachineFunction &MF) const {
473344 const TargetMachine &TM = MF.getTarget();
474345 const ARMSubtarget &Subtarget = TM.getSubtarget();
475 GPRClass::iterator I;
476346
477347 if (Subtarget.isThumb1Only())
478348 return THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned));
479349
480 if (Subtarget.isTargetDarwin()) {
481 if (Subtarget.isR9Reserved())
482 I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned));
483 else
484 I = ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned));
485 } else
486 // R9 is either callee-saved or reserved; can't use it.
487 I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned));
488 return I;
350 return Subtarget.isTargetDarwin() ?
351 ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned)) :
352 ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned));
489353 }
490354 }];
491355 }
627627
628628 ; CHECK: @ %bb24
629629 ; CHECK-NEXT: @ in Loop: Header=BB1_1 Depth=1
630 ; CHECK-NEXT: sub{{.*}} [[REGISTER:r[0-9]+]], #1
630 ; CHECK-NEXT: sub{{.*}} [[REGISTER:(r[0-9]+)|(lr)]], #1
631631 ; CHECK-NEXT: bne.w
632632
633633 %92 = icmp eq i32 %tmp81, %indvar78 ; [#uses=1]
1010 define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string,std::allocator >"* %this, %"struct.std::basic_string,std::allocator >"* %__str) {
1111 ; CHECK: _ZNKSs7compareERKSs:
1212 ; CHECK: it eq
13 ; CHECK-NEXT: subeq.w r0, r6, r8
14 ; CHECK-NEXT: ldmia.w sp!, {r4, r5, r6, r8, r9, pc}
13 ; CHECK-NEXT: subeq r0, r6, r7
14 ; CHECK-NEXT: ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
1515 entry:
1616 %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string,std::allocator >"* %this) ; [#uses=3]
1717 %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string,std::allocator >"* %__str) ; [#uses=3]
2121
2222 define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind {
2323 entry:
24 ; CHECK: ldr.w r9, [r7, #28]
24 ; CHECK: ldr.w {{(r[0-9])|(lr)}}, [r7, #28]
2525 %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
2626 %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
2727 br label %bb20
4545
4646 bb420: ; preds = %bb20, %bb20
4747 ; CHECK: bb420
48 ; CHECK: str r{{[0-7]}}, [sp]
49 ; CHECK: str r{{[0-7]}}, [sp, #4]
50 ; CHECK: str r{{[0-7]}}, [sp, #8]
48 ; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp]
49 ; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #4]
50 ; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #8]
5151 ; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #24]
5252 store %union.rec* null, %union.rec** @zz_hold, align 4
5353 store %union.rec* null, %union.rec** @zz_res, align 4
2020 bb: ; preds = %bb, %entry
2121 ; CHECK: LBB0_1:
2222 ; CHECK: cmp r2, #0
23 ; CHECK: sub.w r9, r2, #1
24 ; CHECK: mov r2, r9
23 ; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], r2, #1
24 ; CHECK: mov r2, [[REGISTER]]
2525
2626 %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; [#uses=1]
2727 %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; [#uses=2]