llvm.org GIT mirror llvm / e7bd519
Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all registers. Previously, the register we being marked as implicitly defined, but not killed. In some cases this would cause the register scavenger to spill a dead register. Also, use an empty register mask to simplify the logic and to reduce the memory footprint. rdar://12592448 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167499 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 7 years ago
7 changed file(s) with 23 addition(s) and 28 deletion(s). Raw diff Collapse all Expand all
8181 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
8282 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
8383 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
84 }
85
86 const uint32_t*
87 ARMBaseRegisterInfo::getNoPreservedMask() const {
88 return CSR_NoRegs_RegMask;
8489 }
8590
8691 BitVector ARMBaseRegisterInfo::
9595 /// Code Generation virtual methods...
9696 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
9797 const uint32_t *getCallPreservedMask(CallingConv::ID) const;
98 const uint32_t *getNoPreservedMask() const;
9899
99100 BitVector getReservedRegs(const MachineFunction &MF) const;
100101
189189 // Callee-saved register lists.
190190 //===----------------------------------------------------------------------===//
191191
192 def CSR_NoRegs : CalleeSavedRegs<(add)>;
193
192194 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
193195 (sequence "D%u", 15, 8))>;
194196
776776 MI.eraseFromParent();
777777 return true;
778778 }
779 case ARM::Int_eh_sjlj_dispatchsetup:
780 case ARM::Int_eh_sjlj_dispatchsetup_nofp:
781 case ARM::tInt_eh_sjlj_dispatchsetup: {
779 case ARM::Int_eh_sjlj_dispatchsetup: {
782780 MachineFunction &MF = *MI.getParent()->getParent();
783781 const ARMBaseInstrInfo *AII =
784782 static_cast(TII);
60766076 MachineMemOperand::MOLoad |
60776077 MachineMemOperand::MOVolatile, 4, 4);
60786078
6079 if (AFI->isThumb1OnlyFunction())
6080 BuildMI(DispatchBB, dl, TII->get(ARM::tInt_eh_sjlj_dispatchsetup));
6081 else if (!Subtarget->hasVFP2())
6082 BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup_nofp));
6083 else
6084 BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6079 MachineInstrBuilder MIB;
6080 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6081
6082 const ARMBaseInstrInfo *AII = static_cast(TII);
6083 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6084
6085 // Add a register mask with no preserved registers. This results in all
6086 // registers being marked as clobbered.
6087 MIB.addRegMask(RI.getNoPreservedMask());
60856088
60866089 unsigned NumLPads = LPadList.size();
60876090 if (Subtarget->isThumb2()) {
63006303 }
63016304
63026305 // N.B. the order the invoke BBs are processed in doesn't matter here.
6303 const ARMBaseInstrInfo *AII = static_cast(TII);
6304 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
63056306 const uint16_t *SavedRegs = RI.getCalleeSavedRegs(MF);
63066307 SmallVector MBBLPads;
63076308 for (SmallPtrSet::iterator
47424742 Requires<[IsARM, IsIOS]>;
47434743 }
47444744
4745 // eh.sjlj.dispatchsetup pseudo-instructions.
4746 // These pseudos are used for both ARM and Thumb2. Any differences are
4747 // handled when the pseudo is expanded (which happens before any passes
4748 // that need the instruction size).
4749 let Defs =
4750 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4751 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4752 isBarrier = 1 in
4745 // eh.sjlj.dispatchsetup pseudo-instruction.
4746 // This pseudo is used for both ARM and Thumb. Any differences are handled when
4747 // the pseudo is expanded (which happens before any passes that need the
4748 // instruction size).
4749 let isBarrier = 1 in
47534750 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4754
4755 let Defs =
4756 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4757 isBarrier = 1 in
4758 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
47594751
47604752
47614753 //===----------------------------------------------------------------------===//
12451245 Pseudo, NoItinerary, "", "",
12461246 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
12471247 Requires<[IsThumb, IsIOS]>;
1248
1249 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1250 isBarrier = 1 in
1251 def tInt_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
12521248
12531249 //===----------------------------------------------------------------------===//
12541250 // Non-Instruction Patterns