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R600: Add IsExport bit to TableGen instruction definitions Tested-by: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188516 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
6 changed file(s) with 16 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
372372 case AMDGPU::CF_ALU:
373373 I = MI;
374374 AluClauses.push_back(MakeALUClause(MBB, I));
375 case AMDGPU::EG_ExportBuf:
376 case AMDGPU::EG_ExportSwz:
377 case AMDGPU::R600_ExportBuf:
378 case AMDGPU::R600_ExportSwz:
379 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
380 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
381 case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
382 case AMDGPU::RAT_STORE_DWORD32:
383 case AMDGPU::RAT_STORE_DWORD64:
384375 DEBUG(dbgs() << CfCount << ":"; MI->dump(););
385376 CfCount++;
386377 break;
490481 EmitALUClause(I, AluClauses[i], CfCount);
491482 }
492483 default:
484 if (TII->isExport(MI->getOpcode())) {
485 DEBUG(dbgs() << CfCount << ":"; MI->dump(););
486 CfCount++;
487 }
493488 break;
494489 }
495490 }
4343 TEX_INST = (1 << 13),
4444 ALU_INST = (1 << 14),
4545 LDS_1A = (1 << 15),
46 LDS_1A1D = (1 << 16)
46 LDS_1A1D = (1 << 16),
47 IS_EXPORT = (1 << 17)
4748 };
4849 }
4950
2828 bit VTXInst = 0;
2929 bit TEXInst = 0;
3030 bit ALUInst = 0;
31 bit IsExport = 0;
3132
3233 let Namespace = "AMDGPU";
3334 let OutOperandList = outs;
5253 let TSFlags{14} = ALUInst;
5354 let TSFlags{15} = LDS_1A;
5455 let TSFlags{16} = LDS_1A1D;
56 let TSFlags{17} = IsExport;
5557 }
5658
5759 //===----------------------------------------------------------------------===//
157157
158158 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
159159 return isTransOnly(MI->getOpcode());
160 }
161
162 bool R600InstrInfo::isExport(unsigned Opcode) const {
163 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
160164 }
161165
162166 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
6767
6868 bool isTransOnly(unsigned Opcode) const;
6969 bool isTransOnly(const MachineInstr *MI) const;
70 bool isExport(unsigned Opcode) const;
7071
7172 bool usesVertexCache(unsigned Opcode) const;
7273 bool usesVertexCache(const MachineInstr *MI) const;
277277
278278 let Inst{31-0} = Word0;
279279 let Inst{63-32} = Word1;
280 let IsExport = 1;
280281
281282 }
282283
550551 let elem_size = 3;
551552 let Inst{31-0} = Word0;
552553 let Inst{63-32} = Word1;
554 let IsExport = 1;
553555 }
554556
555557 } // End usesCustomInserter = 1
563565 let elem_size = 0;
564566 let Inst{31-0} = Word0;
565567 let Inst{63-32} = Word1;
568 let IsExport = 1;
566569 }
567570
568571 //===----------------------------------------------------------------------===//