llvm.org GIT mirror llvm / e785e53
SparcV8 skeleton git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11828 91177308-0d34-0410-b5e6-96231b3b80d8 Brian Gaeke 15 years ago
28 changed file(s) with 1472 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file was developed by the LLVM research group and is distributed under
5 # the University of Illinois Open Source License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8 LEVEL = ../../..
9 LIBRARYNAME = sparcv8
10 include $(LEVEL)/Makefile.common
11
12 # Make sure that tblgen is run, first thing.
13 $(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
14 SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
15 SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
16
17 SparcV8GenRegisterNames.inc:: $(SourceDir)/SparcV8.td \
18 $(SourceDir)/SparcV8Reg.td \
19 $(SourceDir)/../Target.td $(TBLGEN)
20 @echo "Building SparcV8.td register names with tblgen"
21 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
22
23 SparcV8GenRegisterInfo.h.inc:: $(SourceDir)/SparcV8.td \
24 $(SourceDir)/SparcV8Reg.td \
25 $(SourceDir)/../Target.td $(TBLGEN)
26 @echo "Building SparcV8.td register information header with tblgen"
27 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
28
29 SparcV8GenRegisterInfo.inc:: $(SourceDir)/SparcV8.td \
30 $(SourceDir)/SparcV8Reg.td \
31 $(SourceDir)/../Target.td $(TBLGEN)
32 @echo "Building SparcV8.td register information implementation with tblgen"
33 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
34
35 SparcV8GenInstrNames.inc:: $(SourceDir)/SparcV8.td \
36 $(SourceDir)/SparcV8Instrs.td \
37 $(SourceDir)/../Target.td $(TBLGEN)
38 @echo "Building SparcV8.td instruction names with tblgen"
39 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
40
41 SparcV8GenInstrInfo.inc:: $(SourceDir)/SparcV8.td \
42 $(SourceDir)/SparcV8Instrs.td \
43 $(SourceDir)/../Target.td $(TBLGEN)
44 @echo "Building SparcV8.td instruction information with tblgen"
45 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
46
47 SparcV8GenInstrSelector.inc:: $(SourceDir)/SparcV8.td \
48 $(SourceDir)/SparcV8Instrs.td \
49 $(SourceDir)/../Target.td $(TBLGEN)
50 @echo "Building SparcV8.td instruction selector with tblgen"
51 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
52
53 clean::
54 $(VERB) rm -f *.inc
0
1 SparcV8 backend skeleton
2 ------------------------
3
4 This directory will house a 32-bit SPARC V8 backend employing a expander-based
5 instruction selector. Watch this space for more news coming soon!
6
7 $Date$
8
0 //===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the entry points for global functions defined in the LLVM
10 // SparcV8 back-end.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef TARGET_SPARCV8_H
15 #define TARGET_SPARCV8_H
16
17 #include
18
19 namespace llvm {
20
21 class FunctionPass;
22 class TargetMachine;
23
24 // Here is where you would define factory methods for sparcv8-specific
25 // passes. For example:
26 // FunctionPass *createSparcV8SimpleInstructionSelector (TargetMachine &TM);
27 // FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
28 // TargetMachine &TM);
29
30 } // end namespace llvm;
31
32 // Defines symbolic names for SparcV8 registers. This defines a mapping from
33 // register name to register number.
34 //
35 #include "SparcV8GenRegisterNames.inc"
36
37 // Defines symbolic names for the SparcV8 instructions.
38 //
39 #include "SparcV8GenInstrNames.inc"
40
41 #endif
0 //===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 // Get the target-independent interfaces which we are implementing...
13 //
14 include "../Target.td"
15
16 //===----------------------------------------------------------------------===//
17 // Register File Description
18 //===----------------------------------------------------------------------===//
19
20 include "SparcV8Reg.td"
21 include "SparcV8Instrs.td"
22
23 def SparcV8InstrInfo : InstrInfo {
24 let PHIInst = PHI;
25 }
26
27 def SparcV8 : Target {
28 // Pointers are 32-bits in size.
29 let PointerType = i32;
30
31 // According to the Mach-O Runtime ABI, these regs are nonvolatile across
32 // calls:
33 let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
34 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
35 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
36 F30, F31, CR2, CR3, CR4];
37
38 // Pull in Instruction Info:
39 let InstructionSet = SparcV8InstrInfo;
40 }
0 //===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SparcV8 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SparcV8InstrInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "SparcV8GenInstrInfo.inc"
16
17 namespace llvm {
18
19 SparcV8InstrInfo::SparcV8InstrInfo()
20 : TargetInstrInfo(SparcV8Insts,
21 sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0]), 0) {
22 }
23
24 // createNOPinstr - returns the target's implementation of NOP, which is
25 // usually a pseudo-instruction, implemented by a degenerate version of
26 // another instruction.
27 //
28 MachineInstr* SparcV8InstrInfo::createNOPinstr() const {
29 return 0;
30 }
31
32 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
33 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
34 /// more than one way to `do nothing' but only one canonical way to slack off.
35 //
36 bool SparcV8InstrInfo::isNOPinstr(const MachineInstr &MI) const {
37 return false;
38 }
39
40 } // end namespace llvm
41
0 //===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SparcV8 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SPARCV8INSTRUCTIONINFO_H
14 #define SPARCV8INSTRUCTIONINFO_H
15
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "SparcV8RegisterInfo.h"
18
19 namespace llvm {
20
21 class SparcV8InstrInfo : public TargetInstrInfo {
22 const SparcV8RegisterInfo RI;
23 public:
24 SparcV8InstrInfo();
25
26 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
27 /// such, whenever a client has an instance of instruction info, it should
28 /// always be able to get register info as well (through this method).
29 ///
30 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
31
32 /// createNOPinstr - returns the target's implementation of NOP, which is
33 /// usually a pseudo-instruction, implemented by a degenerate version of
34 /// another instruction.
35 ///
36 MachineInstr* createNOPinstr() const;
37
38 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
39 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
40 /// more than one way to `do nothing' but only one canonical way to slack off.
41 ///
42 bool isNOPinstr(const MachineInstr &MI) const;
43 };
44
45 }
46
47 #endif
0 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SparcV8 implementation of the MRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SparcV8.h"
14 #include "SparcV8RegisterInfo.h"
15 #include "llvm/Type.h"
16 using namespace llvm;
17
18 SparcV8RegisterInfo::SparcV8RegisterInfo()
19 : SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN,
20 SparcV8::ADJCALLSTACKUP) {}
21
22 int SparcV8RegisterInfo::storeRegToStackSlot(
23 MachineBasicBlock &MBB,
24 MachineBasicBlock::iterator MBBI,
25 unsigned SrcReg, int FrameIdx,
26 const TargetRegisterClass *RC) const
27 {
28 abort();
29 return -1;
30 }
31
32 int SparcV8RegisterInfo::loadRegFromStackSlot(
33 MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MBBI,
35 unsigned DestReg, int FrameIdx,
36 const TargetRegisterClass *RC) const
37 {
38 abort();
39 return -1;
40 }
41
42 int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator MBBI,
44 unsigned DestReg, unsigned SrcReg,
45 const TargetRegisterClass *RC) const {
46 abort();
47 return -1;
48 }
49
50 void SparcV8RegisterInfo::
51 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator I) const {
53 abort();
54 }
55
56 void
57 SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
58 MachineBasicBlock::iterator II) const {
59 abort();
60 }
61
62 void SparcV8RegisterInfo::processFunctionBeforeFrameFinalized(
63 MachineFunction &MF) const {
64 abort();
65 }
66
67 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
68 abort();
69 }
70
71 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
72 MachineBasicBlock &MBB) const {
73 abort();
74 }
75
76
77 #include "SparcV8GenRegisterInfo.inc"
78
79 const TargetRegisterClass*
80 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
81 switch (Ty->getPrimitiveID()) {
82 case Type::LongTyID:
83 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
84 default: assert(0 && "Invalid type to getClass!");
85 case Type::BoolTyID:
86 case Type::SByteTyID:
87 case Type::UByteTyID:
88 case Type::ShortTyID:
89 case Type::UShortTyID:
90 case Type::IntTyID:
91 case Type::UIntTyID:
92 case Type::PointerTyID: return &GPRCInstance;
93
94 case Type::FloatTyID:
95 case Type::DoubleTyID: return &FPRCInstance;
96 }
97 }
98
0 //===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SparcV8 implementation of the MRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SPARCV8REGISTERINFO_H
14 #define SPARCV8REGISTERINFO_H
15
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "SparcV8GenRegisterInfo.h.inc"
18
19 namespace llvm {
20
21 class Type;
22
23 struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
24 SparcV8RegisterInfo();
25 const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
26
27 /// Code Generation virtual methods...
28 int storeRegToStackSlot(MachineBasicBlock &MBB,
29 MachineBasicBlock::iterator MBBI,
30 unsigned SrcReg, int FrameIndex,
31 const TargetRegisterClass *RC) const;
32
33 int loadRegFromStackSlot(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MBBI,
35 unsigned DestReg, int FrameIndex,
36 const TargetRegisterClass *RC) const;
37
38 int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
39 unsigned DestReg, unsigned SrcReg,
40 const TargetRegisterClass *RC) const;
41
42 void eliminateCallFramePseudoInstr(MachineFunction &MF,
43 MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator I) const;
45
46 void eliminateFrameIndex(MachineFunction &MF,
47 MachineBasicBlock::iterator II) const;
48
49 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
50
51 void emitPrologue(MachineFunction &MF) const;
52 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
53 };
54
55 } // end namespace llvm
56
57 #endif
0 //===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "SparcV8TargetMachine.h"
13 #include "SparcV8.h"
14 #include "llvm/Module.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Target/TargetMachineImpls.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/Passes.h"
19
20 namespace llvm {
21
22 // allocateSparcV8TargetMachine - Allocate and return a subclass of
23 // TargetMachine that implements the SparcV8 backend.
24 //
25 TargetMachine *allocateSparcV8TargetMachine(const Module &M,
26 IntrinsicLowering *IL) {
27 return new SparcV8TargetMachine(M, IL);
28 }
29
30 /// SparcV8TargetMachine ctor - Create an ILP32 architecture model
31 ///
32 SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
33 IntrinsicLowering *IL)
34 : TargetMachine("SparcV8", IL, true, 4, 4, 4, 4, 4),
35 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 4), JITInfo(*this) {
36 }
37
38 /// addPassesToEmitAssembly - Add passes to the specified pass manager
39 /// to implement a static compiler for this target.
40 ///
41 bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
42 std::ostream &Out) {
43 //
44 PM.add(createRegisterAllocator());
45 PM.add(createPrologEpilogCodeInserter());
46 //
47 PM.add(createMachineCodeDeleter());
48 return true; // change to `return false' when this actually works.
49 }
50
51 /// addPassesToJITCompile - Add passes to the specified pass manager to
52 /// implement a fast dynamic compiler for this target.
53 ///
54 void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
55 //
56 PM.add(createRegisterAllocator());
57 PM.add(createPrologEpilogCodeInserter());
58 }
59
60 } // end namespace llvm
0 //===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the SparcV8 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SPARCV8TARGETMACHINE_H
14 #define SPARCV8TARGETMACHINE_H
15
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/TargetFrameInfo.h"
18 #include "llvm/PassManager.h"
19 #include "SparcV8InstrInfo.h"
20 #include "SparcV8JITInfo.h"
21
22 namespace llvm {
23
24 class IntrinsicLowering;
25
26 class SparcV8TargetMachine : public TargetMachine {
27 SparcV8InstrInfo InstrInfo;
28 TargetFrameInfo FrameInfo;
29 SparcV8JITInfo JITInfo;
30 public:
31 SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL);
32
33 virtual const SparcV8InstrInfo &getInstrInfo() const { return InstrInfo; }
34 virtual const TargetFrameInfo &getFrameInfo() const { return FrameInfo; }
35 virtual const MRegisterInfo *getRegisterInfo() const {
36 return &InstrInfo.getRegisterInfo();
37 }
38 virtual TargetJITInfo *getJITInfo() {
39 return &JITInfo;
40 }
41
42 virtual const TargetSchedInfo &getSchedInfo() const { abort(); }
43 virtual const TargetRegInfo &getRegInfo() const { abort(); }
44 virtual const TargetCacheInfo &getCacheInfo() const { abort(); }
45
46 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
47 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
48 /// actually outputting the machine code and resolving things like the address
49 /// of functions. This method should returns true if machine code emission is
50 /// not supported.
51 ///
52 virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
53 MachineCodeEmitter &MCE);
54
55 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
56 };
57
58 } // end namespace llvm
59
60 #endif
0 //===-- SparcV8CodeEmitter.cpp - JIT Code Emitter for SparcV8 -----*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "SparcV8TargetMachine.h"
13
14 namespace llvm {
15
16 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
17 /// machine code emitted. This uses a MachineCodeEmitter object to handle
18 /// actually outputting the machine code and resolving things like the address
19 /// of functions. This method should returns true if machine code emission is
20 /// not supported.
21 ///
22 bool SparcV8TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
23 MachineCodeEmitter &MCE) {
24 return true;
25 // It should go something like this:
26 // PM.add(new Emitter(MCE)); // Machine code emitter pass for SparcV8
27 // Delete machine code for this function after emitting it:
28 // PM.add(createMachineCodeDeleter());
29 }
30
31 void *SparcV8JITInfo::getJITStubForFunction(Function *F,
32 MachineCodeEmitter &MCE) {
33 assert (0 && "SparcV8JITInfo::getJITStubForFunction not implemented");
34 return 0;
35 }
36
37 void SparcV8JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
38 assert (0 && "SparcV8JITInfo::replaceMachineCodeForFunction not implemented");
39 }
40
41 } // end llvm namespace
42
0 //===- SparcV8InstrInfo.td - Describe the SparcV8 Instruction Set -*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 class Format val> {
13 bits<4> Value = val;
14 }
15
16 // All of the SparcV8 instruction formats, plus a pseudo-instruction format:
17 def Pseudo : Format<0>;
18 def IForm : Format<1>;
19 def BForm : Format<2>;
20 def SCForm : Format<3>;
21 def DForm : Format<4>;
22 def XForm : Format<5>;
23 def XLForm : Format<6>;
24 def XFXForm : Format<7>;
25 def XFLForm : Format<8>;
26 def XOForm : Format<9>;
27 def AForm : Format<10>;
28 def MForm : Format<11>;
29
30 class PPCInst opcd, Format f> : Instruction {
31 let Namespace = "SparcV8";
32
33 let Name = nm;
34 bits<6> Opcode = opcd;
35 Format Form = f;
36 bits<4> FormBits = Form.Value;
37 }
38
39 // Pseudo-instructions:
40 def PHI : PPCInst<"PHI", 0, Pseudo>; // PHI node...
41 def NOP : PPCInst<"NOP", 0, Pseudo>; // No-op
42 def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>;
43 def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>;
44
45
0 //===- SparcV8JITInfo.h - SparcV8 impl. of the JIT interface ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SparcV8 implementation of the TargetJITInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SPARCV8JITINFO_H
14 #define SPARCV8JITINFO_H
15
16 #include "llvm/Target/TargetJITInfo.h"
17
18 namespace llvm {
19 class TargetMachine;
20 class IntrinsicLowering;
21
22 class SparcV8JITInfo : public TargetJITInfo {
23 TargetMachine &TM;
24 public:
25 SparcV8JITInfo(TargetMachine &tm) : TM(tm) {}
26
27 /// addPassesToJITCompile - Add passes to the specified pass manager to
28 /// implement a fast dynamic compiler for this target. Return true if this
29 /// is not supported for this target.
30 ///
31 virtual void addPassesToJITCompile(FunctionPassManager &PM);
32
33 /// replaceMachineCodeForFunction - Make it so that calling the function
34 /// whose machine code is at OLD turns into a call to NEW, perhaps by
35 /// overwriting OLD with a branch to NEW. This is used for self-modifying
36 /// code.
37 ///
38 virtual void replaceMachineCodeForFunction(void *Old, void *New);
39
40 /// getJITStubForFunction - Create or return a stub for the specified
41 /// function. This stub acts just like the specified function, except that
42 /// it allows the "address" of the function to be taken without having to
43 /// generate code for it.
44 virtual void *getJITStubForFunction(Function *F, MachineCodeEmitter &MCE);
45 };
46 }
47
48 #endif
0 //===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 class PPCReg : Register {
13 let Namespace = "SparcV8";
14 }
15
16 // We identify all our registers with a 5-bit ID, for consistency's sake.
17
18 // GPR - One of the 32 32-bit general-purpose registers
19 class GPR num> : PPCReg {
20 field bits<5> Num = num;
21 }
22
23 // SPR - One of the 32-bit special-purpose registers
24 class SPR num> : PPCReg {
25 field bits<5> Num = num;
26 }
27
28 // FPR - One of the 32 64-bit floating-point registers
29 class FPR num> : PPCReg {
30 field bits<5> Num = num;
31 }
32
33 // CR - One of the 8 4-bit condition registers
34 class CR num> : PPCReg {
35 field bits<5> Num = num;
36 }
37
38 // General-purpose registers
39 def R0 : GPR< 0>; def R1 : GPR< 1>; def R2 : GPR< 2>; def R3 : GPR< 3>;
40 def R4 : GPR< 4>; def R5 : GPR< 5>; def R6 : GPR< 6>; def R7 : GPR< 7>;
41 def R8 : GPR< 8>; def R9 : GPR< 9>; def R10 : GPR<10>; def R11 : GPR<11>;
42 def R12 : GPR<12>; def R13 : GPR<13>; def R14 : GPR<14>; def R15 : GPR<15>;
43 def R16 : GPR<16>; def R17 : GPR<17>; def R18 : GPR<18>; def R19 : GPR<19>;
44 def R20 : GPR<20>; def R21 : GPR<21>; def R22 : GPR<22>; def R23 : GPR<23>;
45 def R24 : GPR<24>; def R25 : GPR<25>; def R26 : GPR<26>; def R27 : GPR<27>;
46 def R28 : GPR<28>; def R29 : GPR<29>; def R30 : GPR<30>; def R31 : GPR<31>;
47
48 // Floating-point registers
49 def F0 : FPR< 0>; def F1 : FPR< 1>; def F2 : FPR< 2>; def F3 : FPR< 3>;
50 def F4 : FPR< 4>; def F5 : FPR< 5>; def F6 : FPR< 6>; def F7 : FPR< 7>;
51 def F8 : FPR< 8>; def F9 : FPR< 9>; def F10 : FPR<10>; def F11 : FPR<11>;
52 def F12 : FPR<12>; def F13 : FPR<13>; def F14 : FPR<14>; def F15 : FPR<15>;
53 def F16 : FPR<16>; def F17 : FPR<17>; def F18 : FPR<18>; def F19 : FPR<19>;
54 def F20 : FPR<20>; def F21 : FPR<21>; def F22 : FPR<22>; def F23 : FPR<23>;
55 def F24 : FPR<24>; def F25 : FPR<25>; def F26 : FPR<26>; def F27 : FPR<27>;
56 def F28 : FPR<28>; def F29 : FPR<29>; def F30 : FPR<30>; def F31 : FPR<31>;
57
58 // Condition registers
59 def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>;
60 def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>;
61
62 // Floating-point status and control register
63 def FPSCR : SPR<0>;
64 // fiXed-point Exception Register? :-)
65 def XER : SPR<1>;
66 // Link register
67 def LR : SPR<2>;
68 // Count register
69 def CTR : SPR<3>;
70 // These are the "time base" registers which are read-only in user mode.
71 def TBL : SPR<4>;
72 def TBU : SPR<5>;
73
74 /// Register classes: one for floats and another for non-floats.
75 def GPRC : RegisterClass
76 R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
77 R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
78 def FPRC : RegisterClass
79 F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
80 F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
81
0 ##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file was developed by the LLVM research group and is distributed under
5 # the University of Illinois Open Source License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8 LEVEL = ../../..
9 LIBRARYNAME = sparcv8
10 include $(LEVEL)/Makefile.common
11
12 # Make sure that tblgen is run, first thing.
13 $(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
14 SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
15 SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
16
17 SparcV8GenRegisterNames.inc:: $(SourceDir)/SparcV8.td \
18 $(SourceDir)/SparcV8Reg.td \
19 $(SourceDir)/../Target.td $(TBLGEN)
20 @echo "Building SparcV8.td register names with tblgen"
21 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
22
23 SparcV8GenRegisterInfo.h.inc:: $(SourceDir)/SparcV8.td \
24 $(SourceDir)/SparcV8Reg.td \
25 $(SourceDir)/../Target.td $(TBLGEN)
26 @echo "Building SparcV8.td register information header with tblgen"
27 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
28
29 SparcV8GenRegisterInfo.inc:: $(SourceDir)/SparcV8.td \
30 $(SourceDir)/SparcV8Reg.td \
31 $(SourceDir)/../Target.td $(TBLGEN)
32 @echo "Building SparcV8.td register information implementation with tblgen"
33 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
34
35 SparcV8GenInstrNames.inc:: $(SourceDir)/SparcV8.td \
36 $(SourceDir)/SparcV8Instrs.td \
37 $(SourceDir)/../Target.td $(TBLGEN)
38 @echo "Building SparcV8.td instruction names with tblgen"
39 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
40
41 SparcV8GenInstrInfo.inc:: $(SourceDir)/SparcV8.td \
42 $(SourceDir)/SparcV8Instrs.td \
43 $(SourceDir)/../Target.td $(TBLGEN)
44 @echo "Building SparcV8.td instruction information with tblgen"
45 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
46
47 SparcV8GenInstrSelector.inc:: $(SourceDir)/SparcV8.td \
48 $(SourceDir)/SparcV8Instrs.td \
49 $(SourceDir)/../Target.td $(TBLGEN)
50 @echo "Building SparcV8.td instruction selector with tblgen"
51 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
52
53 clean::
54 $(VERB) rm -f *.inc
0
1 SparcV8 backend skeleton
2 ------------------------
3
4 This directory will house a 32-bit SPARC V8 backend employing a expander-based
5 instruction selector. Watch this space for more news coming soon!
6
7 $Date$
8
0 //===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the entry points for global functions defined in the LLVM
10 // SparcV8 back-end.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef TARGET_SPARCV8_H
15 #define TARGET_SPARCV8_H
16
17 #include
18
19 namespace llvm {
20
21 class FunctionPass;
22 class TargetMachine;
23
24 // Here is where you would define factory methods for sparcv8-specific
25 // passes. For example:
26 // FunctionPass *createSparcV8SimpleInstructionSelector (TargetMachine &TM);
27 // FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
28 // TargetMachine &TM);
29
30 } // end namespace llvm;
31
32 // Defines symbolic names for SparcV8 registers. This defines a mapping from
33 // register name to register number.
34 //
35 #include "SparcV8GenRegisterNames.inc"
36
37 // Defines symbolic names for the SparcV8 instructions.
38 //
39 #include "SparcV8GenInstrNames.inc"
40
41 #endif
0 //===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 // Get the target-independent interfaces which we are implementing...
13 //
14 include "../Target.td"
15
16 //===----------------------------------------------------------------------===//
17 // Register File Description
18 //===----------------------------------------------------------------------===//
19
20 include "SparcV8Reg.td"
21 include "SparcV8Instrs.td"
22
23 def SparcV8InstrInfo : InstrInfo {
24 let PHIInst = PHI;
25 }
26
27 def SparcV8 : Target {
28 // Pointers are 32-bits in size.
29 let PointerType = i32;
30
31 // According to the Mach-O Runtime ABI, these regs are nonvolatile across
32 // calls:
33 let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
34 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
35 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
36 F30, F31, CR2, CR3, CR4];
37
38 // Pull in Instruction Info:
39 let InstructionSet = SparcV8InstrInfo;
40 }
0 //===-- SparcV8CodeEmitter.cpp - JIT Code Emitter for SparcV8 -----*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "SparcV8TargetMachine.h"
13
14 namespace llvm {
15
16 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
17 /// machine code emitted. This uses a MachineCodeEmitter object to handle
18 /// actually outputting the machine code and resolving things like the address
19 /// of functions. This method should returns true if machine code emission is
20 /// not supported.
21 ///
22 bool SparcV8TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
23 MachineCodeEmitter &MCE) {
24 return true;
25 // It should go something like this:
26 // PM.add(new Emitter(MCE)); // Machine code emitter pass for SparcV8
27 // Delete machine code for this function after emitting it:
28 // PM.add(createMachineCodeDeleter());
29 }
30
31 void *SparcV8JITInfo::getJITStubForFunction(Function *F,
32 MachineCodeEmitter &MCE) {
33 assert (0 && "SparcV8JITInfo::getJITStubForFunction not implemented");
34 return 0;
35 }
36
37 void SparcV8JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
38 assert (0 && "SparcV8JITInfo::replaceMachineCodeForFunction not implemented");
39 }
40
41 } // end llvm namespace
42
0 //===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SparcV8 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SparcV8InstrInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "SparcV8GenInstrInfo.inc"
16
17 namespace llvm {
18
19 SparcV8InstrInfo::SparcV8InstrInfo()
20 : TargetInstrInfo(SparcV8Insts,
21 sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0]), 0) {
22 }
23
24 // createNOPinstr - returns the target's implementation of NOP, which is
25 // usually a pseudo-instruction, implemented by a degenerate version of
26 // another instruction.
27 //
28 MachineInstr* SparcV8InstrInfo::createNOPinstr() const {
29 return 0;
30 }
31
32 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
33 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
34 /// more than one way to `do nothing' but only one canonical way to slack off.
35 //
36 bool SparcV8InstrInfo::isNOPinstr(const MachineInstr &MI) const {
37 return false;
38 }
39
40 } // end namespace llvm
41
0 //===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SparcV8 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SPARCV8INSTRUCTIONINFO_H
14 #define SPARCV8INSTRUCTIONINFO_H
15
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "SparcV8RegisterInfo.h"
18
19 namespace llvm {
20
21 class SparcV8InstrInfo : public TargetInstrInfo {
22 const SparcV8RegisterInfo RI;
23 public:
24 SparcV8InstrInfo();
25
26 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
27 /// such, whenever a client has an instance of instruction info, it should
28 /// always be able to get register info as well (through this method).
29 ///
30 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
31
32 /// createNOPinstr - returns the target's implementation of NOP, which is
33 /// usually a pseudo-instruction, implemented by a degenerate version of
34 /// another instruction.
35 ///
36 MachineInstr* createNOPinstr() const;
37
38 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
39 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
40 /// more than one way to `do nothing' but only one canonical way to slack off.
41 ///
42 bool isNOPinstr(const MachineInstr &MI) const;
43 };
44
45 }
46
47 #endif
0 //===- SparcV8InstrInfo.td - Describe the SparcV8 Instruction Set -*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 class Format val> {
13 bits<4> Value = val;
14 }
15
16 // All of the SparcV8 instruction formats, plus a pseudo-instruction format:
17 def Pseudo : Format<0>;
18 def IForm : Format<1>;
19 def BForm : Format<2>;
20 def SCForm : Format<3>;
21 def DForm : Format<4>;
22 def XForm : Format<5>;
23 def XLForm : Format<6>;
24 def XFXForm : Format<7>;
25 def XFLForm : Format<8>;
26 def XOForm : Format<9>;
27 def AForm : Format<10>;
28 def MForm : Format<11>;
29
30 class PPCInst opcd, Format f> : Instruction {
31 let Namespace = "SparcV8";
32
33 let Name = nm;
34 bits<6> Opcode = opcd;
35 Format Form = f;
36 bits<4> FormBits = Form.Value;
37 }
38
39 // Pseudo-instructions:
40 def PHI : PPCInst<"PHI", 0, Pseudo>; // PHI node...
41 def NOP : PPCInst<"NOP", 0, Pseudo>; // No-op
42 def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>;
43 def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>;
44
45
0 //===- SparcV8JITInfo.h - SparcV8 impl. of the JIT interface ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SparcV8 implementation of the TargetJITInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SPARCV8JITINFO_H
14 #define SPARCV8JITINFO_H
15
16 #include "llvm/Target/TargetJITInfo.h"
17
18 namespace llvm {
19 class TargetMachine;
20 class IntrinsicLowering;
21
22 class SparcV8JITInfo : public TargetJITInfo {
23 TargetMachine &TM;
24 public:
25 SparcV8JITInfo(TargetMachine &tm) : TM(tm) {}
26
27 /// addPassesToJITCompile - Add passes to the specified pass manager to
28 /// implement a fast dynamic compiler for this target. Return true if this
29 /// is not supported for this target.
30 ///
31 virtual void addPassesToJITCompile(FunctionPassManager &PM);
32
33 /// replaceMachineCodeForFunction - Make it so that calling the function
34 /// whose machine code is at OLD turns into a call to NEW, perhaps by
35 /// overwriting OLD with a branch to NEW. This is used for self-modifying
36 /// code.
37 ///
38 virtual void replaceMachineCodeForFunction(void *Old, void *New);
39
40 /// getJITStubForFunction - Create or return a stub for the specified
41 /// function. This stub acts just like the specified function, except that
42 /// it allows the "address" of the function to be taken without having to
43 /// generate code for it.
44 virtual void *getJITStubForFunction(Function *F, MachineCodeEmitter &MCE);
45 };
46 }
47
48 #endif
0 //===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 class PPCReg : Register {
13 let Namespace = "SparcV8";
14 }
15
16 // We identify all our registers with a 5-bit ID, for consistency's sake.
17
18 // GPR - One of the 32 32-bit general-purpose registers
19 class GPR num> : PPCReg {
20 field bits<5> Num = num;
21 }
22
23 // SPR - One of the 32-bit special-purpose registers
24 class SPR num> : PPCReg {
25 field bits<5> Num = num;
26 }
27
28 // FPR - One of the 32 64-bit floating-point registers
29 class FPR num> : PPCReg {
30 field bits<5> Num = num;
31 }
32
33 // CR - One of the 8 4-bit condition registers
34 class CR num> : PPCReg {
35 field bits<5> Num = num;
36 }
37
38 // General-purpose registers
39 def R0 : GPR< 0>; def R1 : GPR< 1>; def R2 : GPR< 2>; def R3 : GPR< 3>;
40 def R4 : GPR< 4>; def R5 : GPR< 5>; def R6 : GPR< 6>; def R7 : GPR< 7>;
41 def R8 : GPR< 8>; def R9 : GPR< 9>; def R10 : GPR<10>; def R11 : GPR<11>;
42 def R12 : GPR<12>; def R13 : GPR<13>; def R14 : GPR<14>; def R15 : GPR<15>;
43 def R16 : GPR<16>; def R17 : GPR<17>; def R18 : GPR<18>; def R19 : GPR<19>;
44 def R20 : GPR<20>; def R21 : GPR<21>; def R22 : GPR<22>; def R23 : GPR<23>;
45 def R24 : GPR<24>; def R25 : GPR<25>; def R26 : GPR<26>; def R27 : GPR<27>;
46 def R28 : GPR<28>; def R29 : GPR<29>; def R30 : GPR<30>; def R31 : GPR<31>;
47
48 // Floating-point registers
49 def F0 : FPR< 0>; def F1 : FPR< 1>; def F2 : FPR< 2>; def F3 : FPR< 3>;
50 def F4 : FPR< 4>; def F5 : FPR< 5>; def F6 : FPR< 6>; def F7 : FPR< 7>;
51 def F8 : FPR< 8>; def F9 : FPR< 9>; def F10 : FPR<10>; def F11 : FPR<11>;
52 def F12 : FPR<12>; def F13 : FPR<13>; def F14 : FPR<14>; def F15 : FPR<15>;
53 def F16 : FPR<16>; def F17 : FPR<17>; def F18 : FPR<18>; def F19 : FPR<19>;
54 def F20 : FPR<20>; def F21 : FPR<21>; def F22 : FPR<22>; def F23 : FPR<23>;
55 def F24 : FPR<24>; def F25 : FPR<25>; def F26 : FPR<26>; def F27 : FPR<27>;
56 def F28 : FPR<28>; def F29 : FPR<29>; def F30 : FPR<30>; def F31 : FPR<31>;
57
58 // Condition registers
59 def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>;
60 def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>;
61
62 // Floating-point status and control register
63 def FPSCR : SPR<0>;
64 // fiXed-point Exception Register? :-)
65 def XER : SPR<1>;
66 // Link register
67 def LR : SPR<2>;
68 // Count register
69 def CTR : SPR<3>;
70 // These are the "time base" registers which are read-only in user mode.
71 def TBL : SPR<4>;
72 def TBU : SPR<5>;
73
74 /// Register classes: one for floats and another for non-floats.
75 def GPRC : RegisterClass
76 R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
77 R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
78 def FPRC : RegisterClass
79 F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
80 F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
81
0 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SparcV8 implementation of the MRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SparcV8.h"
14 #include "SparcV8RegisterInfo.h"
15 #include "llvm/Type.h"
16 using namespace llvm;
17
18 SparcV8RegisterInfo::SparcV8RegisterInfo()
19 : SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN,
20 SparcV8::ADJCALLSTACKUP) {}
21
22 int SparcV8RegisterInfo::storeRegToStackSlot(
23 MachineBasicBlock &MBB,
24 MachineBasicBlock::iterator MBBI,
25 unsigned SrcReg, int FrameIdx,
26 const TargetRegisterClass *RC) const
27 {
28 abort();
29 return -1;
30 }
31
32 int SparcV8RegisterInfo::loadRegFromStackSlot(
33 MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MBBI,
35 unsigned DestReg, int FrameIdx,
36 const TargetRegisterClass *RC) const
37 {
38 abort();
39 return -1;
40 }
41
42 int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator MBBI,
44 unsigned DestReg, unsigned SrcReg,
45 const TargetRegisterClass *RC) const {
46 abort();
47 return -1;
48 }
49
50 void SparcV8RegisterInfo::
51 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator I) const {
53 abort();
54 }
55
56 void
57 SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
58 MachineBasicBlock::iterator II) const {
59 abort();
60 }
61
62 void SparcV8RegisterInfo::processFunctionBeforeFrameFinalized(
63 MachineFunction &MF) const {
64 abort();
65 }
66
67 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
68 abort();
69 }
70
71 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
72 MachineBasicBlock &MBB) const {
73 abort();
74 }
75
76
77 #include "SparcV8GenRegisterInfo.inc"
78
79 const TargetRegisterClass*
80 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
81 switch (Ty->getPrimitiveID()) {
82 case Type::LongTyID:
83 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
84 default: assert(0 && "Invalid type to getClass!");
85 case Type::BoolTyID:
86 case Type::SByteTyID:
87 case Type::UByteTyID:
88 case Type::ShortTyID:
89 case Type::UShortTyID:
90 case Type::IntTyID:
91 case Type::UIntTyID:
92 case Type::PointerTyID: return &GPRCInstance;
93
94 case Type::FloatTyID:
95 case Type::DoubleTyID: return &FPRCInstance;
96 }
97 }
98
0 //===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SparcV8 implementation of the MRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SPARCV8REGISTERINFO_H
14 #define SPARCV8REGISTERINFO_H
15
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "SparcV8GenRegisterInfo.h.inc"
18
19 namespace llvm {
20
21 class Type;
22
23 struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
24 SparcV8RegisterInfo();
25 const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
26
27 /// Code Generation virtual methods...
28 int storeRegToStackSlot(MachineBasicBlock &MBB,
29 MachineBasicBlock::iterator MBBI,
30 unsigned SrcReg, int FrameIndex,
31 const TargetRegisterClass *RC) const;
32
33 int loadRegFromStackSlot(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MBBI,
35 unsigned DestReg, int FrameIndex,
36 const TargetRegisterClass *RC) const;
37
38 int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
39 unsigned DestReg, unsigned SrcReg,
40 const TargetRegisterClass *RC) const;
41
42 void eliminateCallFramePseudoInstr(MachineFunction &MF,
43 MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator I) const;
45
46 void eliminateFrameIndex(MachineFunction &MF,
47 MachineBasicBlock::iterator II) const;
48
49 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
50
51 void emitPrologue(MachineFunction &MF) const;
52 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
53 };
54
55 } // end namespace llvm
56
57 #endif
0 //===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "SparcV8TargetMachine.h"
13 #include "SparcV8.h"
14 #include "llvm/Module.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Target/TargetMachineImpls.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/Passes.h"
19
20 namespace llvm {
21
22 // allocateSparcV8TargetMachine - Allocate and return a subclass of
23 // TargetMachine that implements the SparcV8 backend.
24 //
25 TargetMachine *allocateSparcV8TargetMachine(const Module &M,
26 IntrinsicLowering *IL) {
27 return new SparcV8TargetMachine(M, IL);
28 }
29
30 /// SparcV8TargetMachine ctor - Create an ILP32 architecture model
31 ///
32 SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
33 IntrinsicLowering *IL)
34 : TargetMachine("SparcV8", IL, true, 4, 4, 4, 4, 4),
35 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 4), JITInfo(*this) {
36 }
37
38 /// addPassesToEmitAssembly - Add passes to the specified pass manager
39 /// to implement a static compiler for this target.
40 ///
41 bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
42 std::ostream &Out) {
43 //
44 PM.add(createRegisterAllocator());
45 PM.add(createPrologEpilogCodeInserter());
46 //
47 PM.add(createMachineCodeDeleter());
48 return true; // change to `return false' when this actually works.
49 }
50
51 /// addPassesToJITCompile - Add passes to the specified pass manager to
52 /// implement a fast dynamic compiler for this target.
53 ///
54 void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
55 //
56 PM.add(createRegisterAllocator());
57 PM.add(createPrologEpilogCodeInserter());
58 }
59
60 } // end namespace llvm
0 //===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the SparcV8 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SPARCV8TARGETMACHINE_H
14 #define SPARCV8TARGETMACHINE_H
15
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/TargetFrameInfo.h"
18 #include "llvm/PassManager.h"
19 #include "SparcV8InstrInfo.h"
20 #include "SparcV8JITInfo.h"
21
22 namespace llvm {
23
24 class IntrinsicLowering;
25
26 class SparcV8TargetMachine : public TargetMachine {
27 SparcV8InstrInfo InstrInfo;
28 TargetFrameInfo FrameInfo;
29 SparcV8JITInfo JITInfo;
30 public:
31 SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL);
32
33 virtual const SparcV8InstrInfo &getInstrInfo() const { return InstrInfo; }
34 virtual const TargetFrameInfo &getFrameInfo() const { return FrameInfo; }
35 virtual const MRegisterInfo *getRegisterInfo() const {
36 return &InstrInfo.getRegisterInfo();
37 }
38 virtual TargetJITInfo *getJITInfo() {
39 return &JITInfo;
40 }
41
42 virtual const TargetSchedInfo &getSchedInfo() const { abort(); }
43 virtual const TargetRegInfo &getRegInfo() const { abort(); }
44 virtual const TargetCacheInfo &getCacheInfo() const { abort(); }
45
46 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
47 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
48 /// actually outputting the machine code and resolving things like the address
49 /// of functions. This method should returns true if machine code emission is
50 /// not supported.
51 ///
52 virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
53 MachineCodeEmitter &MCE);
54
55 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
56 };
57
58 } // end namespace llvm
59
60 #endif