llvm.org GIT mirror llvm / e737018
DAGCombiner: Merge store/loads when we have extload/truncstores This is helps on architectures where i8,i16 are not legal but we have byte, and short loads/stores. Allowing us to merge copies like the one below on ARM. copy(char *a, char *b, int n) { do { int t0 = a[0]; int t1 = a[1]; b[0] = t0; b[1] = t1; radar://13536387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178546 91177308-0d34-0410-b5e6-96231b3b80d8 Arnold Schwaighofer 7 years ago
2 changed file(s) with 117 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
79797979 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
79807980 if (TLI.isTypeLegal(StoreTy))
79817981 LastLegalType = i+1;
7982 // Or check whether a truncstore is legal.
7983 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
7984 TargetLowering::TypePromoteInteger) {
7985 EVT LegalizedStoredValueTy =
7986 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
7987 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy))
7988 LastLegalType = i+1;
7989 }
79827990
79837991 // Find a legal type for the vector store.
79847992 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
81628170 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
81638171 if (TLI.isTypeLegal(StoreTy))
81648172 LastLegalIntegerType = i + 1;
8173 // Or check whether a truncstore and extload is legal.
8174 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
8175 TargetLowering::TypePromoteInteger) {
8176 EVT LegalizedStoredValueTy =
8177 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy);
8178 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
8179 TLI.isLoadExtLegal(ISD::ZEXTLOAD, StoreTy) &&
8180 TLI.isLoadExtLegal(ISD::SEXTLOAD, StoreTy) &&
8181 TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy))
8182 LastLegalIntegerType = i+1;
8183 }
81658184 }
81668185
81678186 // Only use vector types if the vector type is larger than the integer type.
0 ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
1
2 ; Make sure that we merge the consecutive load/store sequence below and use a
3 ; word (16 bit) instead of a byte copy.
4 ; CHECK: MergeLoadStoreBaseIndexOffset
5 ; CHECK: ldrh [[REG:r[0-9]+]], [{{.*}}]
6 ; CHECK: strh [[REG]], [r1], #2
7 define void @MergeLoadStoreBaseIndexOffset(i32* %a, i8* %b, i8* %c, i32 %n) {
8 br label %1
9
10 ;
11 %.09 = phi i32 [ %n, %0 ], [ %11, %1 ]
12 %.08 = phi i8* [ %b, %0 ], [ %10, %1 ]
13 %.0 = phi i32* [ %a, %0 ], [ %2, %1 ]
14 %2 = getelementptr inbounds i32* %.0, i32 1
15 %3 = load i32* %.0, align 1
16 %4 = getelementptr inbounds i8* %c, i32 %3
17 %5 = load i8* %4, align 1
18 %6 = add i32 %3, 1
19 %7 = getelementptr inbounds i8* %c, i32 %6
20 %8 = load i8* %7, align 1
21 store i8 %5, i8* %.08, align 1
22 %9 = getelementptr inbounds i8* %.08, i32 1
23 store i8 %8, i8* %9, align 1
24 %10 = getelementptr inbounds i8* %.08, i32 2
25 %11 = add nsw i32 %.09, -1
26 %12 = icmp eq i32 %11, 0
27 br i1 %12, label %13, label %1
28
29 ;
30 ret void
31 }
32
33 ; Make sure that we merge the consecutive load/store sequence below and use a
34 ; word (16 bit) instead of a byte copy even if there are intermediate sign
35 ; extensions.
36 ; CHECK: MergeLoadStoreBaseIndexOffsetSext
37 ; CHECK: ldrh [[REG:r[0-9]+]], [{{.*}}]
38 ; CHECK: strh [[REG]], [r1], #2
39 define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) {
40 br label %1
41
42 ;
43 %.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
44 %.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
45 %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
46 %2 = getelementptr inbounds i8* %.0, i32 1
47 %3 = load i8* %.0, align 1
48 %4 = sext i8 %3 to i32
49 %5 = getelementptr inbounds i8* %c, i32 %4
50 %6 = load i8* %5, align 1
51 %7 = add i32 %4, 1
52 %8 = getelementptr inbounds i8* %c, i32 %7
53 %9 = load i8* %8, align 1
54 store i8 %6, i8* %.08, align 1
55 %10 = getelementptr inbounds i8* %.08, i32 1
56 store i8 %9, i8* %10, align 1
57 %11 = getelementptr inbounds i8* %.08, i32 2
58 %12 = add nsw i32 %.09, -1
59 %13 = icmp eq i32 %12, 0
60 br i1 %13, label %14, label %1
61
62 ;
63 ret void
64 }
65
66 ; However, we can only merge ignore sign extensions when they are on all memory
67 ; computations;
68 ; CHECK: loadStoreBaseIndexOffsetSextNoSex
69 ; CHECK-NOT: ldrh [[REG:r[0-9]+]], [{{.*}}]
70 ; CHECK-NOT: strh [[REG]], [r1], #2
71 define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) {
72 br label %1
73
74 ;
75 %.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
76 %.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
77 %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
78 %2 = getelementptr inbounds i8* %.0, i32 1
79 %3 = load i8* %.0, align 1
80 %4 = sext i8 %3 to i32
81 %5 = getelementptr inbounds i8* %c, i32 %4
82 %6 = load i8* %5, align 1
83 %7 = add i8 %3, 1
84 %wrap.4 = sext i8 %7 to i32
85 %8 = getelementptr inbounds i8* %c, i32 %wrap.4
86 %9 = load i8* %8, align 1
87 store i8 %6, i8* %.08, align 1
88 %10 = getelementptr inbounds i8* %.08, i32 1
89 store i8 %9, i8* %10, align 1
90 %11 = getelementptr inbounds i8* %.08, i32 2
91 %12 = add nsw i32 %.09, -1
92 %13 = icmp eq i32 %12, 0
93 br i1 %13, label %14, label %1
94
95 ;
96 ret void
97 }