llvm.org GIT mirror llvm / e708238
ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202257 91177308-0d34-0410-b5e6-96231b3b80d8 Artyom Skrobov 6 years ago
4 changed file(s) with 139 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
531531 return false;
532532 }
533533
534 return true;
535 }
536
537 template<> bool IsCPSRDead(MachineInstr* MI) {
538 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
539 const MachineOperand &MO = MI->getOperand(i);
540 if (!MO.isReg() || MO.isUndef() || MO.isUse())
541 continue;
542 if (MO.getReg() != ARM::CPSR)
543 continue;
544 if (!MO.isDead())
545 return false;
546 }
547 // all definitions of CPSR are dead
534548 return true;
535549 }
536550
1515
1616 #include "ARM.h"
1717
18 template // could be MachineInstr or MCInst
19 bool IsCPSRDead(InstrType *Instr);
20
1821 namespace llvm {
1922
2023 template // could be MachineInstr or MCInst
2528 case ARM::tADC:
2629 case ARM::tADDi3:
2730 case ARM::tADDi8:
28 case ARM::tADDrSPi:
2931 case ARM::tADDrr:
3032 case ARM::tAND:
3133 case ARM::tASRri:
3234 case ARM::tASRrr:
3335 case ARM::tBIC:
34 case ARM::tCMNz:
35 case ARM::tCMPi8:
36 case ARM::tCMPr:
3736 case ARM::tEOR:
38 case ARM::tLDRBi:
39 case ARM::tLDRBr:
40 case ARM::tLDRHi:
41 case ARM::tLDRHr:
42 case ARM::tLDRSB:
43 case ARM::tLDRSH:
44 case ARM::tLDRi:
45 case ARM::tLDRr:
46 case ARM::tLDRspi:
4737 case ARM::tLSLri:
4838 case ARM::tLSLrr:
4939 case ARM::tLSRri:
5545 case ARM::tROR:
5646 case ARM::tRSB:
5747 case ARM::tSBC:
48 case ARM::tSUBi3:
49 case ARM::tSUBi8:
50 case ARM::tSUBrr:
51 // Outside of an IT block, these set CPSR.
52 return IsCPSRDead(Instr);
53 case ARM::tADDrSPi:
54 case ARM::tCMNz:
55 case ARM::tCMPi8:
56 case ARM::tCMPr:
57 case ARM::tLDRBi:
58 case ARM::tLDRBr:
59 case ARM::tLDRHi:
60 case ARM::tLDRHr:
61 case ARM::tLDRSB:
62 case ARM::tLDRSH:
63 case ARM::tLDRi:
64 case ARM::tLDRr:
65 case ARM::tLDRspi:
5866 case ARM::tSTRBi:
5967 case ARM::tSTRBr:
6068 case ARM::tSTRHi:
6270 case ARM::tSTRi:
6371 case ARM::tSTRr:
6472 case ARM::tSTRspi:
65 case ARM::tSUBi3:
66 case ARM::tSUBi8:
67 case ARM::tSUBrr:
6873 case ARM::tTST:
6974 return true;
7075 // there are some "conditionally deprecated" opcodes
78497849 return Match_Success;
78507850 }
78517851
7852 template<> inline bool IsCPSRDead(MCInst* Instr) {
7853 return true; // In an assembly source, no need to second-guess
7854 }
7855
78527856 static const char *getSubtargetFeatureName(unsigned Val);
78537857 bool ARMAsmParser::
78547858 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
0 ; RUN: llc < %s -mtriple=thumbv8 -show-mc-encoding | FileCheck %s
1 ; CHECK-NOT: orrsne r0, r1 @ encoding: [0x08,0x43]
2 ; Narrow tORR cannot be predicated and set CPSR at the same time!
3
4 declare void @f(i32)
5
6 define void @initCloneLookups() #1 {
7 entry:
8 br label %for.cond1.preheader
9
10 for.cond1.preheader: ; preds = %for.inc24, %entry
11 %cmp108 = phi i1 [ true, %entry ], [ %cmp, %for.inc24 ]
12 %y.0105 = phi i32 [ 1, %entry ], [ %inc25, %for.inc24 ]
13 %notlhs = icmp slt i32 %y.0105, 6
14 %notlhs69 = icmp sgt i32 %y.0105, 4
15 %sub = add nsw i32 %y.0105, -1
16 %cmp1.i = icmp sgt i32 %sub, 5
17 %cmp1.i54 = icmp sgt i32 %y.0105, 5
18 br i1 %cmp108, label %if.then.us, label %for.cond1.preheader.for.cond1.preheader.split_crit_edge
19
20 for.cond1.preheader.for.cond1.preheader.split_crit_edge: ; preds = %for.cond1.preheader
21 br i1 %notlhs, label %for.inc.us101, label %for.inc
22
23 if.then.us: ; preds = %for.cond1.preheader, %for.inc.us
24 %x.071.us = phi i32 [ %inc.us.pre-phi, %for.inc.us ], [ 1, %for.cond1.preheader ]
25 %notrhs.us = icmp sge i32 %x.071.us, %y.0105
26 %or.cond44.not.us = or i1 %notrhs.us, %notlhs
27 %notrhs70.us = icmp sle i32 %x.071.us, %y.0105
28 %tobool.us = or i1 %notrhs70.us, %notlhs69
29 %or.cond66.us = and i1 %or.cond44.not.us, %tobool.us
30 br i1 %or.cond66.us, label %getHexxagonIndex.exit52.us, label %if.then.us.for.inc.us_crit_edge
31
32 if.then.us.for.inc.us_crit_edge: ; preds = %if.then.us
33 %inc.us.pre = add nsw i32 %x.071.us, 1
34 br label %for.inc.us
35
36 getHexxagonIndex.exit52.us: ; preds = %if.then.us
37 %cmp3.i.us = icmp slt i32 %x.071.us, 5
38 %or.cond.i.us = and i1 %cmp1.i, %cmp3.i.us
39 %..i.us = sext i1 %or.cond.i.us to i32
40 tail call void @f(i32 %..i.us) #3
41 %add.us = add nsw i32 %x.071.us, 1
42 %cmp3.i55.us = icmp slt i32 %add.us, 5
43 %or.cond.i56.us = and i1 %cmp1.i54, %cmp3.i55.us
44 %..i57.us = sext i1 %or.cond.i56.us to i32
45 tail call void @f(i32 %..i57.us) #3
46 %or.cond.i48.us = and i1 %notlhs69, %cmp3.i55.us
47 %..i49.us = sext i1 %or.cond.i48.us to i32
48 tail call void @f(i32 %..i49.us) #3
49 br label %for.inc.us
50
51 for.inc.us: ; preds = %if.then.us.for.inc.us_crit_edge, %getHexxagonIndex.exit52.us
52 %inc.us.pre-phi = phi i32 [ %inc.us.pre, %if.then.us.for.inc.us_crit_edge ], [ %add.us, %getHexxagonIndex.exit52.us ]
53 %exitcond109 = icmp eq i32 %inc.us.pre-phi, 10
54 br i1 %exitcond109, label %for.inc24, label %if.then.us
55
56 for.inc.us101: ; preds = %for.cond1.preheader.for.cond1.preheader.split_crit_edge, %for.inc.us101
57 %x.071.us74 = phi i32 [ %add.us89, %for.inc.us101 ], [ 1, %for.cond1.preheader.for.cond1.preheader.split_crit_edge ]
58 %cmp3.i.us84 = icmp slt i32 %x.071.us74, 5
59 %or.cond.i.us85 = and i1 %cmp1.i, %cmp3.i.us84
60 %..i.us86 = sext i1 %or.cond.i.us85 to i32
61 tail call void @f(i32 %..i.us86) #3
62 %add.us89 = add nsw i32 %x.071.us74, 1
63 %cmp3.i55.us93 = icmp slt i32 %add.us89, 5
64 %or.cond.i56.us94 = and i1 %cmp1.i54, %cmp3.i55.us93
65 %..i57.us95 = sext i1 %or.cond.i56.us94 to i32
66 tail call void @f(i32 %..i57.us95) #3
67 %or.cond.i48.us97 = and i1 %notlhs69, %cmp3.i55.us93
68 %..i49.us98 = sext i1 %or.cond.i48.us97 to i32
69 tail call void @f(i32 %..i49.us98) #3
70 %exitcond110 = icmp eq i32 %add.us89, 10
71 br i1 %exitcond110, label %for.inc24, label %for.inc.us101
72
73 for.inc: ; preds = %for.cond1.preheader.for.cond1.preheader.split_crit_edge, %for.inc
74 %x.071 = phi i32 [ %add, %for.inc ], [ 1, %for.cond1.preheader.for.cond1.preheader.split_crit_edge ]
75 %cmp3.i = icmp slt i32 %x.071, 5
76 %or.cond.i = and i1 %cmp1.i, %cmp3.i
77 %..i = sext i1 %or.cond.i to i32
78 tail call void @f(i32 %..i) #3
79 %add = add nsw i32 %x.071, 1
80 %cmp3.i55 = icmp slt i32 %add, 5
81 %or.cond.i56 = and i1 %cmp1.i54, %cmp3.i55
82 %..i57 = sext i1 %or.cond.i56 to i32
83 tail call void @f(i32 %..i57) #3
84 %or.cond.i48 = and i1 %notlhs69, %cmp3.i55
85 %..i49 = sext i1 %or.cond.i48 to i32
86 tail call void @f(i32 %..i49) #3
87 %exitcond = icmp eq i32 %add, 10
88 br i1 %exitcond, label %for.inc24, label %for.inc
89
90 for.inc24: ; preds = %for.inc, %for.inc.us101, %for.inc.us
91 %inc25 = add nsw i32 %y.0105, 1
92 %cmp = icmp slt i32 %inc25, 10
93 %exitcond111 = icmp eq i32 %inc25, 10
94 br i1 %exitcond111, label %for.end26, label %for.cond1.preheader
95
96 for.end26: ; preds = %for.inc24
97 ret void
98 }
99