llvm.org GIT mirror llvm / e6fb6db
[MIParser] Set RegClassOrRegBank during instruction parsing MachineRegisterInfo::createGenericVirtualRegister sets RegClassOrRegBank to static_cast<RegisterBank *>(nullptr). MIParser on the other hand doesn't. When we attempt to constrain Register Class on such VReg, additional COPY is generated. This way we avoid COPY instructions showing in test that have MIR input while they are not present with llvm-ir input that was used to create given MIR for a -run-pass test. Differential Revision: https://reviews.llvm.org/D68946 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375502 91177308-0d34-0410-b5e6-96231b3b80d8 Petar Avramovic 1 year, 5 days ago
4 changed file(s) with 29 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
14361436 if (MRI.getType(Reg).isValid() && MRI.getType(Reg) != Ty)
14371437 return error("inconsistent type for generic virtual register");
14381438
1439 MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
14391440 MRI.setType(Reg, Ty);
14401441 }
14411442 }
14541455 if (MRI.getType(Reg).isValid() && MRI.getType(Reg) != Ty)
14551456 return error("inconsistent type for generic virtual register");
14561457
1458 MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
14571459 MRI.setType(Reg, Ty);
14581460 } else if (Register::isVirtualRegister(Reg)) {
14591461 // Generic virtual registers must have a type.
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
11 # RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
22
3 # Check there are COPY instructions surrounding ADDVI_W instruction.
4 # MIParser does not set RegClassOrRegBank for parsed virtual registers.
3 # Check there are no COPY instructions surrounding ADDVI_W instruction.
4 # MIParser sets RegClassOrRegBank for parsed virtual registers.
55 # Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
6 # gets selected into ADDVI_W creates additional copies.
7 # FixMe: Make sure this test has same output as setRegClassOrRegBank.ll.
6 # gets selected into ADDVI_W works as expected.
7 # Check that setRegClassOrRegBank.ll has same output.
88
99 --- |
1010
2424 ; P5600: liveins: $a0, $a1
2525 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
2626 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
27 ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
28 ; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>)
29 ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25
30 ; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]]
31 ; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
27 ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
28 ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
29 ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
3230 ; P5600: RetRA
3331 %0:_(p0) = COPY $a0
3432 %1:_(p0) = COPY $a1
150150 ; P5600: liveins: $a0, $a1
151151 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
152152 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
153 ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
154 ; P5600: [[COPY2:%[0-9]+]]:msa128b = COPY [[LOAD]](<16 x s8>)
155 ; P5600: [[ADDVI_B:%[0-9]+]]:msa128b = ADDVI_B [[COPY2]], 3
156 ; P5600: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY [[ADDVI_B]]
157 ; P5600: G_STORE [[COPY3]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c)
153 ; P5600: [[LOAD:%[0-9]+]]:msa128b(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
154 ; P5600: [[ADDVI_B:%[0-9]+]]:msa128b(<16 x s8>) = ADDVI_B [[LOAD]](<16 x s8>), 3
155 ; P5600: G_STORE [[ADDVI_B]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c)
158156 ; P5600: RetRA
159157 %0:_(p0) = COPY $a0
160158 %1:_(p0) = COPY $a1
176174 ; P5600: liveins: $a0, $a1
177175 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
178176 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
179 ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
180 ; P5600: [[COPY2:%[0-9]+]]:msa128h = COPY [[LOAD]](<8 x s16>)
181 ; P5600: [[ADDVI_H:%[0-9]+]]:msa128h = ADDVI_H [[COPY2]], 18
182 ; P5600: [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY [[ADDVI_H]]
183 ; P5600: G_STORE [[COPY3]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c)
177 ; P5600: [[LOAD:%[0-9]+]]:msa128h(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
178 ; P5600: [[ADDVI_H:%[0-9]+]]:msa128h(<8 x s16>) = ADDVI_H [[LOAD]](<8 x s16>), 18
179 ; P5600: G_STORE [[ADDVI_H]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c)
184180 ; P5600: RetRA
185181 %0:_(p0) = COPY $a0
186182 %1:_(p0) = COPY $a1
202198 ; P5600: liveins: $a0, $a1
203199 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
204200 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
205 ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
206 ; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>)
207 ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25
208 ; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]]
209 ; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
201 ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
202 ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
203 ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
210204 ; P5600: RetRA
211205 %0:_(p0) = COPY $a0
212206 %1:_(p0) = COPY $a1
228222 ; P5600: liveins: $a0, $a1
229223 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
230224 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
231 ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
232 ; P5600: [[COPY2:%[0-9]+]]:msa128d = COPY [[LOAD]](<2 x s64>)
233 ; P5600: [[ADDVI_D:%[0-9]+]]:msa128d = ADDVI_D [[COPY2]], 31
234 ; P5600: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY [[ADDVI_D]]
235 ; P5600: G_STORE [[COPY3]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
225 ; P5600: [[LOAD:%[0-9]+]]:msa128d(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
226 ; P5600: [[ADDVI_D:%[0-9]+]]:msa128d(<2 x s64>) = ADDVI_D [[LOAD]](<2 x s64>), 31
227 ; P5600: G_STORE [[ADDVI_D]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
236228 ; P5600: RetRA
237229 %0:_(p0) = COPY $a0
238230 %1:_(p0) = COPY $a1
342342
343343 ; FP32-LABEL: name: u32tof32
344344 ; FP32: liveins: $a0
345 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
345 ; FP32: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0
346346 ; FP32: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
347 ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
348 ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY1]], [[C]](s32)
347 ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY]](s32), [[C]](s32)
349348 ; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
350349 ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C1]]
351350 ; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
353352 ; FP32: RetRA implicit $f0
354353 ; FP64-LABEL: name: u32tof32
355354 ; FP64: liveins: $a0
356 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
355 ; FP64: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0
357356 ; FP64: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
358 ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
359 ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY1]], [[C]](s32)
357 ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY]](s32), [[C]](s32)
360358 ; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
361359 ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C1]]
362360 ; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
500498
501499 ; FP32-LABEL: name: u32tof64
502500 ; FP32: liveins: $a0
503 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
501 ; FP32: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0
504502 ; FP32: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
505 ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
506 ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY1]], [[C]](s32)
503 ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY]](s32), [[C]](s32)
507504 ; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
508505 ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C1]]
509506 ; FP32: $d0 = COPY [[FSUB]](s64)
510507 ; FP32: RetRA implicit $d0
511508 ; FP64-LABEL: name: u32tof64
512509 ; FP64: liveins: $a0
513 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
510 ; FP64: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0
514511 ; FP64: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
515 ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
516 ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY1]], [[C]](s32)
512 ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY]](s32), [[C]](s32)
517513 ; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
518514 ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C1]]
519515 ; FP64: $d0 = COPY [[FSUB]](s64)