llvm.org GIT mirror llvm / e6b8991
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319445 91177308-0d34-0410-b5e6-96231b3b80d8 Francis Visoiu Mistrih 2 years ago
138 changed file(s) with 4080 addition(s) and 4090 deletion(s). Raw diff Collapse all Expand all
140140
141141 DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
142142 DEBUG(for (unsigned r : CriticalPathSet.set_bits())
143 dbgs() << " " << TRI->getName(r));
143 dbgs() << " " << printReg(r, TRI));
144144 DEBUG(dbgs() << '\n');
145145 }
146146
215215 // schedule region).
216216 if (State->IsLive(Reg)) {
217217 DEBUG(if (State->GetGroup(Reg) != 0)
218 dbgs() << " " << TRI->getName(Reg) << "=g" <<
218 dbgs() << " " << printReg(Reg, TRI) << "=g" <<
219219 State->GetGroup(Reg) << "->g0(region live-out)");
220220 State->UnionGroups(Reg, 0);
221221 } else if ((DefIndices[Reg] < InsertPosIndex)
322322 RegRefs.erase(Reg);
323323 State->LeaveGroup(Reg);
324324 DEBUG(if (header) {
325 dbgs() << header << TRI->getName(Reg); header = nullptr; });
325 dbgs() << header << printReg(Reg, TRI); header = nullptr; });
326326 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
327327 // Repeat for subregisters. Note that we only do this if the superregister
328328 // was not live because otherwise, regardless whether we have an explicit
336336 RegRefs.erase(SubregReg);
337337 State->LeaveGroup(SubregReg);
338338 DEBUG(if (header) {
339 dbgs() << header << TRI->getName(Reg); header = nullptr; });
340 DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
339 dbgs() << header << printReg(Reg, TRI); header = nullptr; });
340 DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" <<
341341 State->GetGroup(SubregReg) << tag);
342342 }
343343 }
373373 unsigned Reg = MO.getReg();
374374 if (Reg == 0) continue;
375375
376 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
376 DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg));
377377
378378 // If MI's defs have a special allocation requirement, don't allow
379379 // any def registers to be changed. Also assume all registers
392392 unsigned AliasReg = *AI;
393393 if (State->IsLive(AliasReg)) {
394394 State->UnionGroups(Reg, AliasReg);
395 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
396 TRI->getName(AliasReg) << ")");
395 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
396 << printReg(AliasReg, TRI) << ")");
397397 }
398398 }
399399
468468 unsigned Reg = MO.getReg();
469469 if (Reg == 0) continue;
470470
471 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
472 State->GetGroup(Reg));
471 DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg));
473472
474473 // It wasn't previously live but now it is, this is a kill. Forget
475474 // the previous live-range information and start a new live-range
504503 if (Reg == 0) continue;
505504
506505 if (FirstReg != 0) {
507 DEBUG(dbgs() << "=" << TRI->getName(Reg));
506 DEBUG(dbgs() << "=" << printReg(Reg, TRI));
508507 State->UnionGroups(FirstReg, Reg);
509508 } else {
510 DEBUG(dbgs() << " " << TRI->getName(Reg));
509 DEBUG(dbgs() << " " << printReg(Reg, TRI));
511510 FirstReg = Reg;
512511 }
513512 }
573572
574573 // If Reg has any references, then collect possible rename regs
575574 if (RegRefs.count(Reg) > 0) {
576 DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
575 DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
577576
578577 BitVector &BV = RenameRegisterMap[Reg];
579578 assert(BV.empty());
582581 DEBUG({
583582 dbgs() << " ::";
584583 for (unsigned r : BV.set_bits())
585 dbgs() << " " << TRI->getName(r);
584 dbgs() << " " << printReg(r, TRI);
586585 dbgs() << "\n";
587586 });
588587 }
607606 if (renamecnt++ % DebugDiv != DebugMod)
608607 return false;
609608
610 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
611 " for debug ***\n";
609 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI)
610 << " for debug ***\n";
612611 }
613612 #endif
614613
645644 // Don't replace a register with itself.
646645 if (NewSuperReg == SuperReg) continue;
647646
648 DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
647 DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':');
649648 RenameMap.clear();
650649
651650 // For each referenced group register (which must be a SuperReg or
662661 NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
663662 }
664663
665 DEBUG(dbgs() << " " << TRI->getName(NewReg));
664 DEBUG(dbgs() << " " << printReg(NewReg, TRI));
666665
667666 // Check if Reg can be renamed to NewReg.
668667 if (!RenameRegisterMap[Reg].test(NewReg)) {
683682 unsigned AliasReg = *AI;
684683 if (State->IsLive(AliasReg) ||
685684 (KillIndices[Reg] > DefIndices[AliasReg])) {
686 DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
685 DEBUG(dbgs() << "(alias " << printReg(AliasReg, TRI) << " live)");
687686 found = true;
688687 break;
689688 }
792791 DEBUG(dbgs() << "Available regs:");
793792 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
794793 if (!State->IsLive(Reg))
795 DEBUG(dbgs() << " " << TRI->getName(Reg));
794 DEBUG(dbgs() << " " << printReg(Reg, TRI));
796795 }
797796 DEBUG(dbgs() << '\n');
798797 #endif
848847 (Edge->getKind() != SDep::Output)) continue;
849848
850849 unsigned AntiDepReg = Edge->getReg();
851 DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
850 DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
852851 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
853852
854853 if (!MRI.isAllocatable(AntiDepReg)) {
951950 std::map RenameMap;
952951 if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
953952 DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
954 << TRI->getName(AntiDepReg) << ":");
953 << printReg(AntiDepReg, TRI) << ":");
955954
956955 // Handle each group register...
957956 for (std::map::iterator
959958 unsigned CurrReg = S->first;
960959 unsigned NewReg = S->second;
961960
962 DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
963 TRI->getName(NewReg) << "(" <<
964 RegRefs.count(CurrReg) << " refs)");
961 DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
962 << printReg(NewReg, TRI) << "("
963 << RegRefs.count(CurrReg) << " refs)");
965964
966965 // Update the references to the old register CurrReg to
967966 // refer to the new register NewReg.
465465 DEBUG(dbgs() << "Available regs:");
466466 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
467467 if (KillIndices[Reg] == ~0u)
468 DEBUG(dbgs() << " " << TRI->getName(Reg));
468 DEBUG(dbgs() << " " << printReg(Reg, TRI));
469469 }
470470 DEBUG(dbgs() << '\n');
471471 }
645645 LastNewReg[AntiDepReg],
646646 RC, ForbidRegs)) {
647647 DEBUG(dbgs() << "Breaking anti-dependence edge on "
648 << TRI->getName(AntiDepReg)
649 << " with " << RegRefs.count(AntiDepReg) << " references"
650 << " using " << TRI->getName(NewReg) << "!\n");
648 << printReg(AntiDepReg, TRI) << " with "
649 << RegRefs.count(AntiDepReg) << " references"
650 << " using " << printReg(NewReg, TRI) << "!\n");
651651
652652 // Update the references to the old register to refer to the new
653653 // register.
393393 continue;
394394 for (int rx : regIndices(MO.getReg())) {
395395 // This instruction explicitly defines rx.
396 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
396 DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << CurInstr
397397 << '\t' << *MI);
398398
399399 if (breakDependency) {
191191 } // end namespace yaml
192192 } // end namespace llvm
193193
194 static void printRegMIR(unsigned Reg, raw_ostream &OS,
195 const TargetRegisterInfo *TRI) {
196 // TODO: Print Stack Slots.
197 if (!Reg)
198 OS << '_';
199 else if (TargetRegisterInfo::isVirtualRegister(Reg))
200 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
201 else if (Reg < TRI->getNumRegs())
202 OS << '%' << StringRef(TRI->getName(Reg)).lower();
203 else
204 llvm_unreachable("Can't print this kind of register yet");
205 }
206
207194 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
208195 const TargetRegisterInfo *TRI) {
209196 raw_string_ostream OS(Dest.Value);
210 printRegMIR(Reg, OS, TRI);
197 OS << printReg(Reg, TRI);
211198 }
212199
213200 void MIRPrinter::print(const MachineFunction &MF) {
261248 if (RegMask[I / 32] & (1u << (I % 32))) {
262249 if (IsRegInRegMaskFound)
263250 OS << ',';
264 printRegMIR(I, OS, TRI);
251 OS << printReg(I, TRI);
265252 IsRegInRegMaskFound = true;
266253 }
267254 }
647634 if (!First)
648635 OS << ", ";
649636 First = false;
650 printRegMIR(LI.PhysReg, OS, &TRI);
637 OS << printReg(LI.PhysReg, &TRI);
651638 if (!LI.LaneMask.all())
652639 OS << ":0x" << PrintLaneMask(LI.LaneMask);
653640 }
948935 OS << "early-clobber ";
949936 if (Op.isDebug())
950937 OS << "debug-use ";
951 printRegMIR(Reg, OS, TRI);
938 OS << printReg(Reg, TRI);
952939 // Print the sub register.
953940 if (Op.getSubReg() != 0)
954941 OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
10401027 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
10411028 if (IsCommaNeeded)
10421029 OS << ", ";
1043 printRegMIR(Reg, OS, TRI);
1030 OS << printReg(Reg, TRI);
10441031 IsCommaNeeded = true;
10451032 }
10461033 }
12111198 OS << "";
12121199 return;
12131200 }
1214 printRegMIR(Reg, OS, TRI);
1201 OS << printReg(Reg, TRI);
12151202 }
12161203
12171204 void MIPrinter::print(const MCCFIInstruction &CFI,
10961096 TII->getRegClass(MCID, MONum, TRI, *MF)) {
10971097 if (!DRC->contains(Reg)) {
10981098 report("Illegal physical register for instruction", MO, MONum);
1099 errs() << TRI->getName(Reg) << " is not a "
1100 << TRI->getRegClassName(DRC) << " register.\n";
1099 errs() << printReg(Reg, TRI) << " is not a "
1100 << TRI->getRegClassName(DRC) << " register.\n";
11011101 }
11021102 }
11031103 }
16881688 if (MInfo.regsKilled.count(*I)) {
16891689 report("Virtual register killed in block, but needed live out.", &MBB);
16901690 errs() << "Virtual register " << printReg(*I)
1691 << " is used after the block.\n";
1691 << " is used after the block.\n";
16921692 }
16931693 }
16941694
17211721 if (!VI.AliveBlocks.test(MBB.getNumber())) {
17221722 report("LiveVariables: Block missing from AliveBlocks", &MBB);
17231723 errs() << "Virtual register " << printReg(Reg)
1724 << " must be live through the block.\n";
1724 << " must be live through the block.\n";
17251725 }
17261726 } else {
17271727 if (VI.AliveBlocks.test(MBB.getNumber())) {
17281728 report("LiveVariables: Block should not be in AliveBlocks", &MBB);
17291729 errs() << "Virtual register " << printReg(Reg)
1730 << " is not needed live through the block.\n";
1730 << " is not needed live through the block.\n";
17311731 }
17321732 }
17331733 }
218218 Intfs.push_back(Intf);
219219 }
220220 }
221 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
222 " interferences with " << VirtReg << "\n");
221 DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI)
222 << " interferences with " << VirtReg << "\n");
223223 assert(!Intfs.empty() && "expected interference");
224224
225225 // Spill each interfering vreg allocated to PhysReg or an alias.
812812 void RegAllocFast::dumpState() {
813813 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
814814 if (PhysRegState[Reg] == regDisabled) continue;
815 dbgs() << " " << TRI->getName(Reg);
815 dbgs() << " " << printReg(Reg, TRI);
816816 switch(PhysRegState[Reg]) {
817817 case regFree:
818818 break;
140140
141141 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
142142 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
143 DEBUG(dbgs() << TRI->getName(PReg) << " ");
143 DEBUG(dbgs() << printReg(PReg, TRI) << " ");
144144
145145 DEBUG(dbgs() << " \n----------------------------------------\n");
146146
287287 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
288288 for (unsigned Reg : *RC) {
289289 if (!isRegUsed(Reg)) {
290 DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(Reg) <<
291 "\n");
290 DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
291 << "\n");
292292 return Reg;
293293 }
294294 }
560560
561561 // If we found an unused register there is no reason to spill it.
562562 if (!isRegUsed(SReg)) {
563 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
563 DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
564564 return SReg;
565565 }
566566
567567 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
568568 Scavenged.Restore = &*std::prev(UseMI);
569569
570 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
571 "\n");
570 DEBUG(dbgs() << "Scavenged register (with spill): " << printReg(SReg, TRI)
571 << "\n");
572572
573573 return SReg;
574574 }
598598 Scavenged.Restore = &*std::prev(SpillBefore);
599599 LiveUnits.removeReg(Reg);
600600 DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
601 << " until " << *SpillBefore);
601 << " until " << *SpillBefore);
602602 } else {
603603 DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n');
604604 }
9696
9797 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
9898 if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg))
99 OS << TRI->getName(PReg) << " ";
99 OS << printReg(PReg, TRI) << " ";
100100 }
101101 OS << "\n";
102102 }
14291429 SmallVector LRegs;
14301430 if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
14311431 break;
1432 DEBUG(dbgs() << " Interfering reg " <<
1433 (LRegs[0] == TRI->getNumRegs() ? "CallResource"
1434 : TRI->getName(LRegs[0]))
1435 << " SU #" << CurSU->NodeNum << '\n');
1432 DEBUG(dbgs() << " Interfering reg ";
1433 if (LRegs[0] == TRI->getNumRegs())
1434 dbgs() << "CallResource";
1435 else
1436 dbgs() << printReg(LRegs[0], TRI);
1437 dbgs() << " SU #" << CurSU->NodeNum << '\n');
14361438 std::pair LRegsPair =
14371439 LRegsMap.insert(std::make_pair(CurSU, LRegs));
14381440 if (LRegsPair.second) {
192192 case Location::Register:
193193 OS << "Register ";
194194 if (TRI)
195 OS << TRI->getName(Loc.Reg);
195 OS << printReg(Loc.Reg, TRI);
196196 else
197197 OS << Loc.Reg;
198198 break;
199199 case Location::Direct:
200200 OS << "Direct ";
201201 if (TRI)
202 OS << TRI->getName(Loc.Reg);
202 OS << printReg(Loc.Reg, TRI);
203203 else
204204 OS << Loc.Reg;
205205 if (Loc.Offset)
208208 case Location::Indirect:
209209 OS << "Indirect ";
210210 if (TRI)
211 OS << TRI->getName(Loc.Reg);
211 OS << printReg(Loc.Reg, TRI);
212212 else
213213 OS << Loc.Reg;
214214 OS << "+" << Loc.Offset;
232232 for (const auto &LO : LiveOuts) {
233233 OS << WSMP << "\t\tLO " << Idx << ": ";
234234 if (TRI)
235 OS << TRI->getName(LO.Reg);
235 OS << printReg(LO.Reg, TRI);
236236 else
237237 OS << LO.Reg;
238238 OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte "
9393 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
9494 else if (TargetRegisterInfo::isVirtualRegister(Reg))
9595 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
96 else if (TRI && Reg < TRI->getNumRegs()) {
96 else if (!TRI)
97 OS << '%' << "physreg" << Reg;
98 else if (Reg < TRI->getNumRegs()) {
9799 OS << '%';
98100 printLowerCase(TRI->getName(Reg), OS);
99101 } else
100 OS << "%physreg" << Reg;
102 llvm_unreachable("Register kind is unsupported.");
103
101104 if (SubIdx) {
102105 if (TRI)
103106 OS << ':' << TRI->getSubRegIndexName(SubIdx);
537537 DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n");
538538 return false;
539539 }
540 DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n");
540 DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n");
541541
542542 std::map Substs;
543543 for (MachineInstr &I : *G) {
610610 // unit.
611611 unsigned DestReg = MI->getOperand(0).getReg();
612612
613 DEBUG(dbgs() << "New chain started for register "
614 << TRI->getName(DestReg) << " at " << *MI);
613 DEBUG(dbgs() << "New chain started for register " << printReg(DestReg, TRI)
614 << " at " << *MI);
615615
616616 auto G = llvm::make_unique(MI, Idx, getColor(DestReg));
617617 ActiveChains[DestReg] = G.get();
631631
632632 if (ActiveChains.find(AccumReg) != ActiveChains.end()) {
633633 DEBUG(dbgs() << "Chain found for accumulator register "
634 << TRI->getName(AccumReg) << " in MI " << *MI);
634 << printReg(AccumReg, TRI) << " in MI " << *MI);
635635
636636 // For simplicity we only chain together sequences of MULs/MLAs where the
637637 // accumulator register is killed on each instruction. This means we don't
656656 }
657657
658658 DEBUG(dbgs() << "Creating new chain for dest register "
659 << TRI->getName(DestReg) << "\n");
659 << printReg(DestReg, TRI) << "\n");
660660 auto G = llvm::make_unique(MI, Idx, getColor(DestReg));
661661 ActiveChains[DestReg] = G.get();
662662 AllChains.push_back(std::move(G));
684684
685685 // If this is a KILL of a current chain, record it.
686686 if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) {
687 DEBUG(dbgs() << "Kill seen for chain " << TRI->getName(MO.getReg())
688 << "\n");
687 DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI)
688 << "\n");
689689 ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied());
690690 }
691691 ActiveChains.erase(MO.getReg());
696696 I != E;) {
697697 if (MO.clobbersPhysReg(I->first)) {
698698 DEBUG(dbgs() << "Kill (regmask) seen for chain "
699 << TRI->getName(I->first) << "\n");
699 << printReg(I->first, TRI) << "\n");
700700 I->second->setKill(MI, Idx, /*Immutable=*/true);
701701 ActiveChains.erase(I++);
702702 } else
10591059 StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui;
10601060 else
10611061 StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui;
1062 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1);
1062 DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI);
10631063 if (RPI.isPaired())
1064 dbgs() << ", " << TRI->getName(Reg2);
1064 dbgs() << ", " << printReg(Reg2, TRI);
10651065 dbgs() << ") -> fi#(" << RPI.FrameIdx;
10661066 if (RPI.isPaired())
10671067 dbgs() << ", " << RPI.FrameIdx+1;
11221122 LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
11231123 else
11241124 LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
1125 DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1);
1125 DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
11261126 if (RPI.isPaired())
1127 dbgs() << ", " << TRI->getName(Reg2);
1127 dbgs() << ", " << printReg(Reg2, TRI);
11281128 dbgs() << ") -> fi#(" << RPI.FrameIdx;
11291129 if (RPI.isPaired())
11301130 dbgs() << ", " << RPI.FrameIdx+1;
12331233 if (BigStack) {
12341234 if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) {
12351235 DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
1236 << " to get a scratch register.\n");
1236 << " to get a scratch register.\n");
12371237 SavedRegs.set(UnspilledCSGPR);
12381238 // MachO's compact unwind format relies on all registers being stored in
12391239 // pairs, so if we need to spill one extra for BigStack, then we need to
545545 if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg()))
546546 return;
547547 unsigned AndOpReg = RegN->getReg();
548 DEBUG(dbgs() << "Examine %" << TargetRegisterInfo::virtReg2Index(AndOpReg)
549 << '\n');
548 DEBUG(dbgs() << "Examine " << printReg(AndOpReg) << '\n');
550549
551550 // Examine the PHI insns in the MachineBasicBlock to found out the
552551 // definitions of this virtual register. At this stage (DAG2DAG
55 ; CHECK: - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
66 ; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true,
77 ; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()',
8 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !DIExpression(), debug-location !12
8 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !11, !DIExpression(), debug-location !12
99 define void @debug_declare(i32 %in) #0 !dbg !7 {
1010 entry:
1111 %in.addr = alloca i32, align 4
1616 }
1717
1818 ; CHECK-LABEL: name: debug_declare_vla
19 ; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use _, !14, !DIExpression(), debug-location !15
19 ; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use %noreg, !14, !DIExpression(), debug-location !15
2020 define void @debug_declare_vla(i32 %in) #0 !dbg !13 {
2121 entry:
2222 %vla.addr = alloca i32, i32 %in
2828 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
2929 define void @debug_value(i32 %in) #0 !dbg !16 {
3030 %addr = alloca i32
31 ; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use _, !17, !DIExpression(), debug-location !18
31 ; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use %noreg, !17, !DIExpression(), debug-location !18
3232 call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
3333 store i32 %in, i32* %addr
34 ; CHECK: DBG_VALUE debug-use %1(p0), debug-use _, !17, !DIExpression(DW_OP_deref), debug-location !18
34 ; CHECK: DBG_VALUE debug-use %1(p0), debug-use %noreg, !17, !DIExpression(DW_OP_deref), debug-location !18
3535 call void @llvm.dbg.value(metadata i32* %addr, i64 0, metadata !17, metadata !DIExpression(DW_OP_deref)), !dbg !18
3636 ; CHECK: DBG_VALUE 123, 0, !17, !DIExpression(), debug-location !18
3737 call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
3838 ; CHECK: DBG_VALUE float 1.000000e+00, 0, !17, !DIExpression(), debug-location !18
3939 call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
40 ; CHECK: DBG_VALUE _, 0, !17, !DIExpression(), debug-location !18
40 ; CHECK: DBG_VALUE %noreg, 0, !17, !DIExpression(), debug-location !18
4141 call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
4242 ret void
4343 }
3535 bb.0:
3636 liveins: %w0
3737 %0:_(s32) = COPY %w0
38 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9
39 DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9
38 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
39 DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
4040
41 ; CHECK: DBG_VALUE _, 0, !7, !DIExpression(), debug-location !9
42 DBG_VALUE _, 0, !7, !DIExpression(), debug-location !9
41 ; CHECK: DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9
42 DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9
4343 ...
4545 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
4646 ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY]]
4747 ; CHECK: %w0 = COPY [[ADDWrr]]
48 ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use _, !7, !DIExpression(), debug-location !9
48 ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use %noreg, !7, !DIExpression(), debug-location !9
4949 %0:gpr(s32) = COPY %w0
5050 %1:gpr(s32) = G_ADD %0, %0
5151 %w0 = COPY %1(s32)
52 DBG_VALUE debug-use %1(s32), debug-use _, !7, !DIExpression(), debug-location !9
52 DBG_VALUE debug-use %1(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
5353 ...
5454
5555 ---
6161 liveins: %w0
6262 ; CHECK-LABEL: name: test_dbg_value_dead
6363 ; CHECK-NOT: COPY
64 ; CHECK: DBG_VALUE debug-use _, debug-use _, !7, !DIExpression(), debug-location !9
64 ; CHECK: DBG_VALUE debug-use %noreg, debug-use %noreg, !7, !DIExpression(), debug-location !9
6565 %0:gpr(s32) = COPY %w0
66 DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9
66 DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
6767 ...
119119 !26 = !DILocation(line: 29, column: 9, scope: !18)
120120 !27 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 35, type: !9, isLocal: false, isDefinition: true, scopeLine: 35, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
121121 !33 = !DILocation(line: 36, column: 1, scope: !27)
122 !35 = !DILocation(line: 38, column: 1, scope: !27)
122 !35 = !DILocation(line: 38, column: 1, scope: !27)
7171 }
7272
7373 attributes #0 = { nounwind }
74 attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" }
74 attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" }
547547
548548 %flat_scr_lo = S_ADD_U32 %sgpr6, %sgpr9, implicit-def %scc
549549 %flat_scr_hi = S_ADDC_U32 %sgpr7, 0, implicit-def %scc, implicit %scc
550 DBG_VALUE _, 2, !5, !11, debug-location !12
550 DBG_VALUE %noreg, 2, !5, !11, debug-location !12
551551 %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
552552 dead %sgpr6_sgpr7 = KILL %sgpr4_sgpr5
553553 %sgpr8 = S_MOV_B32 %sgpr5
129129 }
130130
131131 attributes #0 = { norecurse nounwind "amdgpu-waves-per-eu"="1,1" }
132 attributes #1 = { norecurse nounwind }
132 attributes #1 = { norecurse nounwind }
6262 %19.sub1 = COPY killed %18
6363 %10 = S_MOV_B32 61440
6464 %11 = S_MOV_B32 0
65 DBG_VALUE debug-use %11, debug-use _, !1, !8, debug-location !9
65 DBG_VALUE debug-use %11, debug-use %noreg, !1, !8, debug-location !9
6666 undef %12.sub0 = COPY killed %11
6767 %12.sub1 = COPY killed %10
6868 undef %13.sub0_sub1 = COPY killed %4
119119 bb.0.entry:
120120 liveins: %r0, %r1, %r2, %r3, %lr, %r7
121121
122 DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
123 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
124 DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
125 DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
126 t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31
122 DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
123 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
124 DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
125 DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
126 t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31
127127 t2Bcc %bb.2.if.end, 2, killed %cpsr
128128
129129 bb.1:
130130 liveins: %lr, %r7
131131
132 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
133 %r0 = t2MOVi -1, 14, _, _
134 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
135 tBX_RET 14, _, implicit %r0, debug-location !34
132 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
133 %r0 = t2MOVi -1, 14, %noreg, %noreg
134 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
135 tBX_RET 14, %noreg, implicit %r0, debug-location !34
136136
137137 bb.2.if.end:
138138 liveins: %r0, %r2, %r3, %r7, %lr
139139
140 %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr
140 %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr
141141 frame-setup CFI_INSTRUCTION def_cfa_offset 8
142142 frame-setup CFI_INSTRUCTION offset %lr, -4
143143 frame-setup CFI_INSTRUCTION offset %r7, -8
144 DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
145 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
146 DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
147 DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
144 DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
145 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
146 DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
147 DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
148148 %r1 = COPY killed %r2, debug-location !32
149 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
149 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
150150 %r2 = COPY killed %r3, debug-location !32
151 tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
152 %r0 = t2MOVi 0, 14, _, _
153 %sp = t2LDMIA_UPD %sp, 14, _, def %r7, def %lr
154 tBX_RET 14, _, implicit %r0, debug-location !34
151 tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
152 %r0 = t2MOVi 0, 14, %noreg, %noreg
153 %sp = t2LDMIA_UPD %sp, 14, %noreg, def %r7, def %lr
154 tBX_RET 14, %noreg, implicit %r0, debug-location !34
155155 # Verify that the DBG_VALUE is ignored.
156 # CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0
156 # CHECK: %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0
157157
158158 ...
66 ; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY %r0
77 ; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
88 ; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
9 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
9 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
1010 ; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
1111 ; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
1212 ; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
13 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
13 ; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
1414 entry:
1515 notail call arm_aapcscc void %fptr()
1616 ret void
2020
2121 define arm_aapcscc void @test_direct_call() {
2222 ; CHECK-LABEL: name: test_direct_call
23 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
23 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
2424 ; CHECK: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp
25 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
25 ; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
2626 entry:
2727 notail call arm_aapcscc void @call_target()
2828 ret void
6868 ; CHECK-LABEL: name: test_icmp_eq_s32
6969 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
7070 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
71 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
72 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
71 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
72 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
7373 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
74 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
75 ; CHECK: %r0 = COPY [[ANDri]]
76 ; CHECK: BX_RET 14, _, implicit %r0
74 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
75 ; CHECK: %r0 = COPY [[ANDri]]
76 ; CHECK: BX_RET 14, %noreg, implicit %r0
7777 %0(s32) = COPY %r0
7878 %1(s32) = COPY %r1
7979 %2(s1) = G_ICMP intpred(eq), %0(s32), %1
8080 %3(s32) = G_ZEXT %2(s1)
8181 %r0 = COPY %3(s32)
82 BX_RET 14, _, implicit %r0
82 BX_RET 14, %noreg, implicit %r0
8383 ...
8484 ---
8585 name: test_icmp_ne_s32
9898 ; CHECK-LABEL: name: test_icmp_ne_s32
9999 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
100100 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
101 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
102 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
101 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
102 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
103103 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
104 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
105 ; CHECK: %r0 = COPY [[ANDri]]
106 ; CHECK: BX_RET 14, _, implicit %r0
104 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
105 ; CHECK: %r0 = COPY [[ANDri]]
106 ; CHECK: BX_RET 14, %noreg, implicit %r0
107107 %0(s32) = COPY %r0
108108 %1(s32) = COPY %r1
109109 %2(s1) = G_ICMP intpred(ne), %0(s32), %1
110110 %3(s32) = G_ZEXT %2(s1)
111111 %r0 = COPY %3(s32)
112 BX_RET 14, _, implicit %r0
112 BX_RET 14, %noreg, implicit %r0
113113 ...
114114 ---
115115 name: test_icmp_ugt_s32
128128 ; CHECK-LABEL: name: test_icmp_ugt_s32
129129 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
130130 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
131 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
132 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
131 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
132 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
133133 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
134 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
135 ; CHECK: %r0 = COPY [[ANDri]]
136 ; CHECK: BX_RET 14, _, implicit %r0
134 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
135 ; CHECK: %r0 = COPY [[ANDri]]
136 ; CHECK: BX_RET 14, %noreg, implicit %r0
137137 %0(s32) = COPY %r0
138138 %1(s32) = COPY %r1
139139 %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
140140 %3(s32) = G_ZEXT %2(s1)
141141 %r0 = COPY %3(s32)
142 BX_RET 14, _, implicit %r0
142 BX_RET 14, %noreg, implicit %r0
143143 ...
144144 ---
145145 name: test_icmp_uge_s32
158158 ; CHECK-LABEL: name: test_icmp_uge_s32
159159 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
160160 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
161 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
162 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
161 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
162 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
163163 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, %cpsr
164 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
165 ; CHECK: %r0 = COPY [[ANDri]]
166 ; CHECK: BX_RET 14, _, implicit %r0
164 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
165 ; CHECK: %r0 = COPY [[ANDri]]
166 ; CHECK: BX_RET 14, %noreg, implicit %r0
167167 %0(s32) = COPY %r0
168168 %1(s32) = COPY %r1
169169 %2(s1) = G_ICMP intpred(uge), %0(s32), %1
170170 %3(s32) = G_ZEXT %2(s1)
171171 %r0 = COPY %3(s32)
172 BX_RET 14, _, implicit %r0
172 BX_RET 14, %noreg, implicit %r0
173173 ...
174174 ---
175175 name: test_icmp_ult_s32
188188 ; CHECK-LABEL: name: test_icmp_ult_s32
189189 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
190190 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
191 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
192 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
191 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
192 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
193193 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, %cpsr
194 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
195 ; CHECK: %r0 = COPY [[ANDri]]
196 ; CHECK: BX_RET 14, _, implicit %r0
194 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
195 ; CHECK: %r0 = COPY [[ANDri]]
196 ; CHECK: BX_RET 14, %noreg, implicit %r0
197197 %0(s32) = COPY %r0
198198 %1(s32) = COPY %r1
199199 %2(s1) = G_ICMP intpred(ult), %0(s32), %1
200200 %3(s32) = G_ZEXT %2(s1)
201201 %r0 = COPY %3(s32)
202 BX_RET 14, _, implicit %r0
202 BX_RET 14, %noreg, implicit %r0
203203 ...
204204 ---
205205 name: test_icmp_ule_s32
218218 ; CHECK-LABEL: name: test_icmp_ule_s32
219219 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
220220 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
221 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
222 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
221 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
222 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
223223 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
224 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
225 ; CHECK: %r0 = COPY [[ANDri]]
226 ; CHECK: BX_RET 14, _, implicit %r0
224 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
225 ; CHECK: %r0 = COPY [[ANDri]]
226 ; CHECK: BX_RET 14, %noreg, implicit %r0
227227 %0(s32) = COPY %r0
228228 %1(s32) = COPY %r1
229229 %2(s1) = G_ICMP intpred(ule), %0(s32), %1
230230 %3(s32) = G_ZEXT %2(s1)
231231 %r0 = COPY %3(s32)
232 BX_RET 14, _, implicit %r0
232 BX_RET 14, %noreg, implicit %r0
233233 ...
234234 ---
235235 name: test_icmp_sgt_s32
248248 ; CHECK-LABEL: name: test_icmp_sgt_s32
249249 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
250250 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
251 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
252 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
251 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
252 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
253253 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
254 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
255 ; CHECK: %r0 = COPY [[ANDri]]
256 ; CHECK: BX_RET 14, _, implicit %r0
254 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
255 ; CHECK: %r0 = COPY [[ANDri]]
256 ; CHECK: BX_RET 14, %noreg, implicit %r0
257257 %0(s32) = COPY %r0
258258 %1(s32) = COPY %r1
259259 %2(s1) = G_ICMP intpred(sgt), %0(s32), %1
260260 %3(s32) = G_ZEXT %2(s1)
261261 %r0 = COPY %3(s32)
262 BX_RET 14, _, implicit %r0
262 BX_RET 14, %noreg, implicit %r0
263263 ...
264264 ---
265265 name: test_icmp_sge_s32
278278 ; CHECK-LABEL: name: test_icmp_sge_s32
279279 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
280280 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
281 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
282 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
281 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
282 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
283283 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
284 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
285 ; CHECK: %r0 = COPY [[ANDri]]
286 ; CHECK: BX_RET 14, _, implicit %r0
284 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
285 ; CHECK: %r0 = COPY [[ANDri]]
286 ; CHECK: BX_RET 14, %noreg, implicit %r0
287287 %0(s32) = COPY %r0
288288 %1(s32) = COPY %r1
289289 %2(s1) = G_ICMP intpred(sge), %0(s32), %1
290290 %3(s32) = G_ZEXT %2(s1)
291291 %r0 = COPY %3(s32)
292 BX_RET 14, _, implicit %r0
292 BX_RET 14, %noreg, implicit %r0
293293 ...
294294 ---
295295 name: test_icmp_slt_s32
308308 ; CHECK-LABEL: name: test_icmp_slt_s32
309309 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
310310 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
311 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
312 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
311 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
312 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
313313 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
314 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
315 ; CHECK: %r0 = COPY [[ANDri]]
316 ; CHECK: BX_RET 14, _, implicit %r0
314 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
315 ; CHECK: %r0 = COPY [[ANDri]]
316 ; CHECK: BX_RET 14, %noreg, implicit %r0
317317 %0(s32) = COPY %r0
318318 %1(s32) = COPY %r1
319319 %2(s1) = G_ICMP intpred(slt), %0(s32), %1
320320 %3(s32) = G_ZEXT %2(s1)
321321 %r0 = COPY %3(s32)
322 BX_RET 14, _, implicit %r0
322 BX_RET 14, %noreg, implicit %r0
323323 ...
324324 ---
325325 name: test_icmp_sle_s32
338338 ; CHECK-LABEL: name: test_icmp_sle_s32
339339 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
340340 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
341 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
342 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
341 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
342 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
343343 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
344 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
345 ; CHECK: %r0 = COPY [[ANDri]]
346 ; CHECK: BX_RET 14, _, implicit %r0
344 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
345 ; CHECK: %r0 = COPY [[ANDri]]
346 ; CHECK: BX_RET 14, %noreg, implicit %r0
347347 %0(s32) = COPY %r0
348348 %1(s32) = COPY %r1
349349 %2(s1) = G_ICMP intpred(sle), %0(s32), %1
350350 %3(s32) = G_ZEXT %2(s1)
351351 %r0 = COPY %3(s32)
352 BX_RET 14, _, implicit %r0
352 BX_RET 14, %noreg, implicit %r0
353353 ...
354354 ---
355355 name: test_fcmp_true_s32
366366 liveins: %s0, %s1
367367
368368 ; CHECK-LABEL: name: test_fcmp_true_s32
369 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, _, _
370 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _
371 ; CHECK: %r0 = COPY [[ANDri]]
372 ; CHECK: BX_RET 14, _, implicit %r0
369 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, %noreg, %noreg
370 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
371 ; CHECK: %r0 = COPY [[ANDri]]
372 ; CHECK: BX_RET 14, %noreg, implicit %r0
373373 %0(s32) = COPY %s0
374374 %1(s32) = COPY %s1
375375 %2(s1) = G_FCMP floatpred(true), %0(s32), %1
376376 %3(s32) = G_ZEXT %2(s1)
377377 %r0 = COPY %3(s32)
378 BX_RET 14, _, implicit %r0
378 BX_RET 14, %noreg, implicit %r0
379379 ...
380380 ---
381381 name: test_fcmp_false_s32
392392 liveins: %s0, %s1
393393
394394 ; CHECK-LABEL: name: test_fcmp_false_s32
395 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
396 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _
397 ; CHECK: %r0 = COPY [[ANDri]]
398 ; CHECK: BX_RET 14, _, implicit %r0
395 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
396 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
397 ; CHECK: %r0 = COPY [[ANDri]]
398 ; CHECK: BX_RET 14, %noreg, implicit %r0
399399 %0(s32) = COPY %s0
400400 %1(s32) = COPY %s1
401401 %2(s1) = G_FCMP floatpred(false), %0(s32), %1
402402 %3(s32) = G_ZEXT %2(s1)
403403 %r0 = COPY %3(s32)
404 BX_RET 14, _, implicit %r0
404 BX_RET 14, %noreg, implicit %r0
405405 ...
406406 ---
407407 name: test_fcmp_oeq_s32
420420 ; CHECK-LABEL: name: test_fcmp_oeq_s32
421421 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
422422 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
423 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
424 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
425 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
423 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
424 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
425 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
426426 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
427 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
428 ; CHECK: %r0 = COPY [[ANDri]]
429 ; CHECK: BX_RET 14, _, implicit %r0
427 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
428 ; CHECK: %r0 = COPY [[ANDri]]
429 ; CHECK: BX_RET 14, %noreg, implicit %r0
430430 %0(s32) = COPY %s0
431431 %1(s32) = COPY %s1
432432 %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
433433 %3(s32) = G_ZEXT %2(s1)
434434 %r0 = COPY %3(s32)
435 BX_RET 14, _, implicit %r0
435 BX_RET 14, %noreg, implicit %r0
436436 ...
437437 ---
438438 name: test_fcmp_ogt_s32
451451 ; CHECK-LABEL: name: test_fcmp_ogt_s32
452452 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
453453 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
454 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
455 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
456 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
454 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
455 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
456 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
457457 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
458 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
459 ; CHECK: %r0 = COPY [[ANDri]]
460 ; CHECK: BX_RET 14, _, implicit %r0
458 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
459 ; CHECK: %r0 = COPY [[ANDri]]
460 ; CHECK: BX_RET 14, %noreg, implicit %r0
461461 %0(s32) = COPY %s0
462462 %1(s32) = COPY %s1
463463 %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
464464 %3(s32) = G_ZEXT %2(s1)
465465 %r0 = COPY %3(s32)
466 BX_RET 14, _, implicit %r0
466 BX_RET 14, %noreg, implicit %r0
467467 ...
468468 ---
469469 name: test_fcmp_oge_s32
482482 ; CHECK-LABEL: name: test_fcmp_oge_s32
483483 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
484484 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
485 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
486 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
487 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
485 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
486 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
487 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
488488 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
489 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
490 ; CHECK: %r0 = COPY [[ANDri]]
491 ; CHECK: BX_RET 14, _, implicit %r0
489 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
490 ; CHECK: %r0 = COPY [[ANDri]]
491 ; CHECK: BX_RET 14, %noreg, implicit %r0
492492 %0(s32) = COPY %s0
493493 %1(s32) = COPY %s1
494494 %2(s1) = G_FCMP floatpred(oge), %0(s32), %1
495495 %3(s32) = G_ZEXT %2(s1)
496496 %r0 = COPY %3(s32)
497 BX_RET 14, _, implicit %r0
497 BX_RET 14, %noreg, implicit %r0
498498 ...
499499 ---
500500 name: test_fcmp_olt_s32
513513 ; CHECK-LABEL: name: test_fcmp_olt_s32
514514 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
515515 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
516 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
517 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
518 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
516 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
517 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
518 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
519519 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr
520 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
521 ; CHECK: %r0 = COPY [[ANDri]]
522 ; CHECK: BX_RET 14, _, implicit %r0
520 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
521 ; CHECK: %r0 = COPY [[ANDri]]
522 ; CHECK: BX_RET 14, %noreg, implicit %r0
523523 %0(s32) = COPY %s0
524524 %1(s32) = COPY %s1
525525 %2(s1) = G_FCMP floatpred(olt), %0(s32), %1
526526 %3(s32) = G_ZEXT %2(s1)
527527 %r0 = COPY %3(s32)
528 BX_RET 14, _, implicit %r0
528 BX_RET 14, %noreg, implicit %r0
529529 ...
530530 ---
531531 name: test_fcmp_ole_s32
544544 ; CHECK-LABEL: name: test_fcmp_ole_s32
545545 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
546546 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
547 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
548 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
549 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
547 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
548 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
549 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
550550 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
551 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
552 ; CHECK: %r0 = COPY [[ANDri]]
553 ; CHECK: BX_RET 14, _, implicit %r0
551 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
552 ; CHECK: %r0 = COPY [[ANDri]]
553 ; CHECK: BX_RET 14, %noreg, implicit %r0
554554 %0(s32) = COPY %s0
555555 %1(s32) = COPY %s1
556556 %2(s1) = G_FCMP floatpred(ole), %0(s32), %1
557557 %3(s32) = G_ZEXT %2(s1)
558558 %r0 = COPY %3(s32)
559 BX_RET 14, _, implicit %r0
559 BX_RET 14, %noreg, implicit %r0
560560 ...
561561 ---
562562 name: test_fcmp_ord_s32
575575 ; CHECK-LABEL: name: test_fcmp_ord_s32
576576 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
577577 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
578 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
579 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
580 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
578 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
579 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
580 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
581581 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr
582 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
583 ; CHECK: %r0 = COPY [[ANDri]]
584 ; CHECK: BX_RET 14, _, implicit %r0
582 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
583 ; CHECK: %r0 = COPY [[ANDri]]
584 ; CHECK: BX_RET 14, %noreg, implicit %r0
585585 %0(s32) = COPY %s0
586586 %1(s32) = COPY %s1
587587 %2(s1) = G_FCMP floatpred(ord), %0(s32), %1
588588 %3(s32) = G_ZEXT %2(s1)
589589 %r0 = COPY %3(s32)
590 BX_RET 14, _, implicit %r0
590 BX_RET 14, %noreg, implicit %r0
591591 ...
592592 ---
593593 name: test_fcmp_ugt_s32
606606 ; CHECK-LABEL: name: test_fcmp_ugt_s32
607607 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
608608 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
609 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
610 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
611 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
609 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
610 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
611 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
612612 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
613 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
614 ; CHECK: %r0 = COPY [[ANDri]]
615 ; CHECK: BX_RET 14, _, implicit %r0
613 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
614 ; CHECK: %r0 = COPY [[ANDri]]
615 ; CHECK: BX_RET 14, %noreg, implicit %r0
616616 %0(s32) = COPY %s0
617617 %1(s32) = COPY %s1
618618 %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
619619 %3(s32) = G_ZEXT %2(s1)
620620 %r0 = COPY %3(s32)
621 BX_RET 14, _, implicit %r0
621 BX_RET 14, %noreg, implicit %r0
622622 ...
623623 ---
624624 name: test_fcmp_uge_s32
637637 ; CHECK-LABEL: name: test_fcmp_uge_s32
638638 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
639639 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
640 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
641 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
642 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
640 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
641 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
642 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
643643 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr
644 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
645 ; CHECK: %r0 = COPY [[ANDri]]
646 ; CHECK: BX_RET 14, _, implicit %r0
644 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
645 ; CHECK: %r0 = COPY [[ANDri]]
646 ; CHECK: BX_RET 14, %noreg, implicit %r0
647647 %0(s32) = COPY %s0
648648 %1(s32) = COPY %s1
649649 %2(s1) = G_FCMP floatpred(uge), %0(s32), %1
650650 %3(s32) = G_ZEXT %2(s1)
651651 %r0 = COPY %3(s32)
652 BX_RET 14, _, implicit %r0
652 BX_RET 14, %noreg, implicit %r0
653653 ...
654654 ---
655655 name: test_fcmp_ult_s32
668668 ; CHECK-LABEL: name: test_fcmp_ult_s32
669669 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
670670 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
671 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
672 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
673 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
671 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
672 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
673 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
674674 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
675 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
676 ; CHECK: %r0 = COPY [[ANDri]]
677 ; CHECK: BX_RET 14, _, implicit %r0
675 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
676 ; CHECK: %r0 = COPY [[ANDri]]
677 ; CHECK: BX_RET 14, %noreg, implicit %r0
678678 %0(s32) = COPY %s0
679679 %1(s32) = COPY %s1
680680 %2(s1) = G_FCMP floatpred(ult), %0(s32), %1
681681 %3(s32) = G_ZEXT %2(s1)
682682 %r0 = COPY %3(s32)
683 BX_RET 14, _, implicit %r0
683 BX_RET 14, %noreg, implicit %r0
684684 ...
685685 ---
686686 name: test_fcmp_ule_s32
699699 ; CHECK-LABEL: name: test_fcmp_ule_s32
700700 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
701701 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
702 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
703 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
704 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
702 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
703 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
704 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
705705 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
706 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
707 ; CHECK: %r0 = COPY [[ANDri]]
708 ; CHECK: BX_RET 14, _, implicit %r0
706 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
707 ; CHECK: %r0 = COPY [[ANDri]]
708 ; CHECK: BX_RET 14, %noreg, implicit %r0
709709 %0(s32) = COPY %s0
710710 %1(s32) = COPY %s1
711711 %2(s1) = G_FCMP floatpred(ule), %0(s32), %1
712712 %3(s32) = G_ZEXT %2(s1)
713713 %r0 = COPY %3(s32)
714 BX_RET 14, _, implicit %r0
714 BX_RET 14, %noreg, implicit %r0
715715 ...
716716 ---
717717 name: test_fcmp_une_s32
730730 ; CHECK-LABEL: name: test_fcmp_une_s32
731731 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
732732 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
733 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
734 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
735 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
733 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
734 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
735 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
736736 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
737 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
738 ; CHECK: %r0 = COPY [[ANDri]]
739 ; CHECK: BX_RET 14, _, implicit %r0
737 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
738 ; CHECK: %r0 = COPY [[ANDri]]
739 ; CHECK: BX_RET 14, %noreg, implicit %r0
740740 %0(s32) = COPY %s0
741741 %1(s32) = COPY %s1
742742 %2(s1) = G_FCMP floatpred(une), %0(s32), %1
743743 %3(s32) = G_ZEXT %2(s1)
744744 %r0 = COPY %3(s32)
745 BX_RET 14, _, implicit %r0
745 BX_RET 14, %noreg, implicit %r0
746746 ...
747747 ---
748748 name: test_fcmp_uno_s32
761761 ; CHECK-LABEL: name: test_fcmp_uno_s32
762762 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
763763 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
764 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
765 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
766 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
764 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
765 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
766 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
767767 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr
768 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
769 ; CHECK: %r0 = COPY [[ANDri]]
770 ; CHECK: BX_RET 14, _, implicit %r0
768 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
769 ; CHECK: %r0 = COPY [[ANDri]]
770 ; CHECK: BX_RET 14, %noreg, implicit %r0
771771 %0(s32) = COPY %s0
772772 %1(s32) = COPY %s1
773773 %2(s1) = G_FCMP floatpred(uno), %0(s32), %1
774774 %3(s32) = G_ZEXT %2(s1)
775775 %r0 = COPY %3(s32)
776 BX_RET 14, _, implicit %r0
776 BX_RET 14, %noreg, implicit %r0
777777 ...
778778 ---
779779 name: test_fcmp_one_s32
792792 ; CHECK-LABEL: name: test_fcmp_one_s32
793793 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
794794 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
795 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
796 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
797 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
795 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
796 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
797 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
798798 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
799 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
800 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
799 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
800 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
801801 ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr
802 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _
803 ; CHECK: %r0 = COPY [[ANDri]]
804 ; CHECK: BX_RET 14, _, implicit %r0
802 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
803 ; CHECK: %r0 = COPY [[ANDri]]
804 ; CHECK: BX_RET 14, %noreg, implicit %r0
805805 %0(s32) = COPY %s0
806806 %1(s32) = COPY %s1
807807 %2(s1) = G_FCMP floatpred(one), %0(s32), %1
808808 %3(s32) = G_ZEXT %2(s1)
809809 %r0 = COPY %3(s32)
810 BX_RET 14, _, implicit %r0
810 BX_RET 14, %noreg, implicit %r0
811811 ...
812812 ---
813813 name: test_fcmp_ueq_s32
826826 ; CHECK-LABEL: name: test_fcmp_ueq_s32
827827 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
828828 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
829 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
830 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
831 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
829 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
830 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
831 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
832832 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
833 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
834 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
833 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
834 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
835835 ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr
836 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _
837 ; CHECK: %r0 = COPY [[ANDri]]
838 ; CHECK: BX_RET 14, _, implicit %r0
836 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
837 ; CHECK: %r0 = COPY [[ANDri]]
838 ; CHECK: BX_RET 14, %noreg, implicit %r0
839839 %0(s32) = COPY %s0
840840 %1(s32) = COPY %s1
841841 %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
842842 %3(s32) = G_ZEXT %2(s1)
843843 %r0 = COPY %3(s32)
844 BX_RET 14, _, implicit %r0
844 BX_RET 14, %noreg, implicit %r0
845845 ...
846846 ---
847847 name: test_fcmp_true_s64
858858 liveins: %d0, %d1
859859
860860 ; CHECK-LABEL: name: test_fcmp_true_s64
861 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, _, _
862 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _
863 ; CHECK: %r0 = COPY [[ANDri]]
864 ; CHECK: BX_RET 14, _, implicit %r0
861 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, %noreg, %noreg
862 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
863 ; CHECK: %r0 = COPY [[ANDri]]
864 ; CHECK: BX_RET 14, %noreg, implicit %r0
865865 %0(s64) = COPY %d0
866866 %1(s64) = COPY %d1
867867 %2(s1) = G_FCMP floatpred(true), %0(s64), %1
868868 %3(s32) = G_ZEXT %2(s1)
869869 %r0 = COPY %3(s32)
870 BX_RET 14, _, implicit %r0
870 BX_RET 14, %noreg, implicit %r0
871871 ...
872872 ---
873873 name: test_fcmp_false_s64
884884 liveins: %d0, %d1
885885
886886 ; CHECK-LABEL: name: test_fcmp_false_s64
887 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
888 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _
889 ; CHECK: %r0 = COPY [[ANDri]]
890 ; CHECK: BX_RET 14, _, implicit %r0
887 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
888 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
889 ; CHECK: %r0 = COPY [[ANDri]]
890 ; CHECK: BX_RET 14, %noreg, implicit %r0
891891 %0(s64) = COPY %d0
892892 %1(s64) = COPY %d1
893893 %2(s1) = G_FCMP floatpred(false), %0(s64), %1
894894 %3(s32) = G_ZEXT %2(s1)
895895 %r0 = COPY %3(s32)
896 BX_RET 14, _, implicit %r0
896 BX_RET 14, %noreg, implicit %r0
897897 ...
898898 ---
899899 name: test_fcmp_oeq_s64
912912 ; CHECK-LABEL: name: test_fcmp_oeq_s64
913913 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
914914 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
915 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
916 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
917 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
915 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
916 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
917 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
918918 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
919 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
920 ; CHECK: %r0 = COPY [[ANDri]]
921 ; CHECK: BX_RET 14, _, implicit %r0
919 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
920 ; CHECK: %r0 = COPY [[ANDri]]
921 ; CHECK: BX_RET 14, %noreg, implicit %r0
922922 %0(s64) = COPY %d0
923923 %1(s64) = COPY %d1
924924 %2(s1) = G_FCMP floatpred(oeq), %0(s64), %1
925925 %3(s32) = G_ZEXT %2(s1)
926926 %r0 = COPY %3(s32)
927 BX_RET 14, _, implicit %r0
927 BX_RET 14, %noreg, implicit %r0
928928 ...
929929 ---
930930 name: test_fcmp_ogt_s64
943943 ; CHECK-LABEL: name: test_fcmp_ogt_s64
944944 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
945945 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
946 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
947 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
948 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
946 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
947 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
948 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
949949 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
950 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
951 ; CHECK: %r0 = COPY [[ANDri]]
952 ; CHECK: BX_RET 14, _, implicit %r0
950 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
951 ; CHECK: %r0 = COPY [[ANDri]]
952 ; CHECK: BX_RET 14, %noreg, implicit %r0
953953 %0(s64) = COPY %d0
954954 %1(s64) = COPY %d1
955955 %2(s1) = G_FCMP floatpred(ogt), %0(s64), %1
956956 %3(s32) = G_ZEXT %2(s1)
957957 %r0 = COPY %3(s32)
958 BX_RET 14, _, implicit %r0
958 BX_RET 14, %noreg, implicit %r0
959959 ...
960960 ---
961961 name: test_fcmp_oge_s64
974974 ; CHECK-LABEL: name: test_fcmp_oge_s64
975975 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
976976 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
977 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
978 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
979 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
977 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
978 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
979 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
980980 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
981 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
982 ; CHECK: %r0 = COPY [[ANDri]]
983 ; CHECK: BX_RET 14, _, implicit %r0
981 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
982 ; CHECK: %r0 = COPY [[ANDri]]
983 ; CHECK: BX_RET 14, %noreg, implicit %r0
984984 %0(s64) = COPY %d0
985985 %1(s64) = COPY %d1
986986 %2(s1) = G_FCMP floatpred(oge), %0(s64), %1
987987 %3(s32) = G_ZEXT %2(s1)
988988 %r0 = COPY %3(s32)
989 BX_RET 14, _, implicit %r0
989 BX_RET 14, %noreg, implicit %r0
990990 ...
991991 ---
992992 name: test_fcmp_olt_s64
10051005 ; CHECK-LABEL: name: test_fcmp_olt_s64
10061006 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
10071007 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1008 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1009 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1010 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1008 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1009 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1010 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
10111011 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr
1012 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
1013 ; CHECK: %r0 = COPY [[ANDri]]
1014 ; CHECK: BX_RET 14, _, implicit %r0
1012 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
1013 ; CHECK: %r0 = COPY [[ANDri]]
1014 ; CHECK: BX_RET 14, %noreg, implicit %r0
10151015 %0(s64) = COPY %d0
10161016 %1(s64) = COPY %d1
10171017 %2(s1) = G_FCMP floatpred(olt), %0(s64), %1
10181018 %3(s32) = G_ZEXT %2(s1)
10191019 %r0 = COPY %3(s32)
1020 BX_RET 14, _, implicit %r0
1020 BX_RET 14, %noreg, implicit %r0
10211021 ...
10221022 ---
10231023 name: test_fcmp_ole_s64
10361036 ; CHECK-LABEL: name: test_fcmp_ole_s64
10371037 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
10381038 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1039 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1040 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1041 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1039 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1040 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1041 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
10421042 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
1043 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
1044 ; CHECK: %r0 = COPY [[ANDri]]
1045 ; CHECK: BX_RET 14, _, implicit %r0
1043 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
1044 ; CHECK: %r0 = COPY [[ANDri]]
1045 ; CHECK: BX_RET 14, %noreg, implicit %r0
10461046 %0(s64) = COPY %d0
10471047 %1(s64) = COPY %d1
10481048 %2(s1) = G_FCMP floatpred(ole), %0(s64), %1
10491049 %3(s32) = G_ZEXT %2(s1)
10501050 %r0 = COPY %3(s32)
1051 BX_RET 14, _, implicit %r0
1051 BX_RET 14, %noreg, implicit %r0
10521052 ...
10531053 ---
10541054 name: test_fcmp_ord_s64
10671067 ; CHECK-LABEL: name: test_fcmp_ord_s64
10681068 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
10691069 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1070 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1071 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1072 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1070 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1071 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1072 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
10731073 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr
1074 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
1075 ; CHECK: %r0 = COPY [[ANDri]]
1076 ; CHECK: BX_RET 14, _, implicit %r0
1074 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
1075 ; CHECK: %r0 = COPY [[ANDri]]
1076 ; CHECK: BX_RET 14, %noreg, implicit %r0
10771077 %0(s64) = COPY %d0
10781078 %1(s64) = COPY %d1
10791079 %2(s1) = G_FCMP floatpred(ord), %0(s64), %1
10801080 %3(s32) = G_ZEXT %2(s1)
10811081 %r0 = COPY %3(s32)
1082 BX_RET 14, _, implicit %r0
1082 BX_RET 14, %noreg, implicit %r0
10831083 ...
10841084 ---
10851085 name: test_fcmp_ugt_s64
10981098 ; CHECK-LABEL: name: test_fcmp_ugt_s64
10991099 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
11001100 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1101 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1102 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1103 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1101 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1102 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1103 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
11041104 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
1105 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
1106 ; CHECK: %r0 = COPY [[ANDri]]
1107 ; CHECK: BX_RET 14, _, implicit %r0
1105 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
1106 ; CHECK: %r0 = COPY [[ANDri]]
1107 ; CHECK: BX_RET 14, %noreg, implicit %r0
11081108 %0(s64) = COPY %d0
11091109 %1(s64) = COPY %d1
11101110 %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
11111111 %3(s32) = G_ZEXT %2(s1)
11121112 %r0 = COPY %3(s32)
1113 BX_RET 14, _, implicit %r0
1113 BX_RET 14, %noreg, implicit %r0
11141114 ...
11151115 ---
11161116 name: test_fcmp_uge_s64
11291129 ; CHECK-LABEL: name: test_fcmp_uge_s64
11301130 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
11311131 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1132 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1133 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1134 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1132 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1133 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1134 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
11351135 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr
1136 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
1137 ; CHECK: %r0 = COPY [[ANDri]]
1138 ; CHECK: BX_RET 14, _, implicit %r0
1136 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
1137 ; CHECK: %r0 = COPY [[ANDri]]
1138 ; CHECK: BX_RET 14, %noreg, implicit %r0
11391139 %0(s64) = COPY %d0
11401140 %1(s64) = COPY %d1
11411141 %2(s1) = G_FCMP floatpred(uge), %0(s64), %1
11421142 %3(s32) = G_ZEXT %2(s1)
11431143 %r0 = COPY %3(s32)
1144 BX_RET 14, _, implicit %r0
1144 BX_RET 14, %noreg, implicit %r0
11451145 ...
11461146 ---
11471147 name: test_fcmp_ult_s64
11601160 ; CHECK-LABEL: name: test_fcmp_ult_s64
11611161 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
11621162 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1163 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1164 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1165 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1163 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1164 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1165 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
11661166 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
1167 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
1168 ; CHECK: %r0 = COPY [[ANDri]]
1169 ; CHECK: BX_RET 14, _, implicit %r0
1167 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
1168 ; CHECK: %r0 = COPY [[ANDri]]
1169 ; CHECK: BX_RET 14, %noreg, implicit %r0
11701170 %0(s64) = COPY %d0
11711171 %1(s64) = COPY %d1
11721172 %2(s1) = G_FCMP floatpred(ult), %0(s64), %1
11731173 %3(s32) = G_ZEXT %2(s1)
11741174 %r0 = COPY %3(s32)
1175 BX_RET 14, _, implicit %r0
1175 BX_RET 14, %noreg, implicit %r0
11761176 ...
11771177 ---
11781178 name: test_fcmp_ule_s64
11911191 ; CHECK-LABEL: name: test_fcmp_ule_s64
11921192 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
11931193 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1194 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1195 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1196 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1194 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1195 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1196 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
11971197 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
1198 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
1199 ; CHECK: %r0 = COPY [[ANDri]]
1200 ; CHECK: BX_RET 14, _, implicit %r0
1198 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
1199 ; CHECK: %r0 = COPY [[ANDri]]
1200 ; CHECK: BX_RET 14, %noreg, implicit %r0
12011201 %0(s64) = COPY %d0
12021202 %1(s64) = COPY %d1
12031203 %2(s1) = G_FCMP floatpred(ule), %0(s64), %1
12041204 %3(s32) = G_ZEXT %2(s1)
12051205 %r0 = COPY %3(s32)
1206 BX_RET 14, _, implicit %r0
1206 BX_RET 14, %noreg, implicit %r0
12071207 ...
12081208 ---
12091209 name: test_fcmp_une_s64
12221222 ; CHECK-LABEL: name: test_fcmp_une_s64
12231223 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
12241224 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1225 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1226 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1227 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1225 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1226 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1227 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
12281228 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
1229 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
1230 ; CHECK: %r0 = COPY [[ANDri]]
1231 ; CHECK: BX_RET 14, _, implicit %r0
1229 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
1230 ; CHECK: %r0 = COPY [[ANDri]]
1231 ; CHECK: BX_RET 14, %noreg, implicit %r0
12321232 %0(s64) = COPY %d0
12331233 %1(s64) = COPY %d1
12341234 %2(s1) = G_FCMP floatpred(une), %0(s64), %1
12351235 %3(s32) = G_ZEXT %2(s1)
12361236 %r0 = COPY %3(s32)
1237 BX_RET 14, _, implicit %r0
1237 BX_RET 14, %noreg, implicit %r0
12381238 ...
12391239 ---
12401240 name: test_fcmp_uno_s64
12531253 ; CHECK-LABEL: name: test_fcmp_uno_s64
12541254 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
12551255 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1256 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1257 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1258 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1256 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1257 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1258 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
12591259 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr
1260 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
1261 ; CHECK: %r0 = COPY [[ANDri]]
1262 ; CHECK: BX_RET 14, _, implicit %r0
1260 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
1261 ; CHECK: %r0 = COPY [[ANDri]]
1262 ; CHECK: BX_RET 14, %noreg, implicit %r0
12631263 %0(s64) = COPY %d0
12641264 %1(s64) = COPY %d1
12651265 %2(s1) = G_FCMP floatpred(uno), %0(s64), %1
12661266 %3(s32) = G_ZEXT %2(s1)
12671267 %r0 = COPY %3(s32)
1268 BX_RET 14, _, implicit %r0
1268 BX_RET 14, %noreg, implicit %r0
12691269 ...
12701270 ---
12711271 name: test_fcmp_one_s64
12841284 ; CHECK-LABEL: name: test_fcmp_one_s64
12851285 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
12861286 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1287 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1288 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1289 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1287 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1288 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1289 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
12901290 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
1291 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1292 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1291 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1292 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
12931293 ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr
1294 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _
1295 ; CHECK: %r0 = COPY [[ANDri]]
1296 ; CHECK: BX_RET 14, _, implicit %r0
1294 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
1295 ; CHECK: %r0 = COPY [[ANDri]]
1296 ; CHECK: BX_RET 14, %noreg, implicit %r0
12971297 %0(s64) = COPY %d0
12981298 %1(s64) = COPY %d1
12991299 %2(s1) = G_FCMP floatpred(one), %0(s64), %1
13001300 %3(s32) = G_ZEXT %2(s1)
13011301 %r0 = COPY %3(s32)
1302 BX_RET 14, _, implicit %r0
1302 BX_RET 14, %noreg, implicit %r0
13031303 ...
13041304 ---
13051305 name: test_fcmp_ueq_s64
13181318 ; CHECK-LABEL: name: test_fcmp_ueq_s64
13191319 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
13201320 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
1321 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
1322 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1323 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1321 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
1322 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1323 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
13241324 ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
1325 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1326 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1325 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
1326 ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
13271327 ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr
1328 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _
1329 ; CHECK: %r0 = COPY [[ANDri]]
1330 ; CHECK: BX_RET 14, _, implicit %r0
1328 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
1329 ; CHECK: %r0 = COPY [[ANDri]]
1330 ; CHECK: BX_RET 14, %noreg, implicit %r0
13311331 %0(s64) = COPY %d0
13321332 %1(s64) = COPY %d1
13331333 %2(s1) = G_FCMP floatpred(ueq), %0(s64), %1
13341334 %3(s32) = G_ZEXT %2(s1)
13351335 %r0 = COPY %3(s32)
1336 BX_RET 14, _, implicit %r0
1337 ...
1336 BX_RET 14, %noreg, implicit %r0
1337 ...
4949
5050 %3(s32) = G_MUL %0, %1
5151 %4(s32) = G_ADD %3, %2
52 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
53
54 %r0 = COPY %4(s32)
55 ; CHECK: %r0 = COPY [[VREGR]]
56
57 BX_RET 14, _, implicit %r0
58 ; CHECK: BX_RET 14, _, implicit %r0
52 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
53
54 %r0 = COPY %4(s32)
55 ; CHECK: %r0 = COPY [[VREGR]]
56
57 BX_RET 14, %noreg, implicit %r0
58 ; CHECK: BX_RET 14, %noreg, implicit %r0
5959 ...
6060 ---
6161 name: test_mla_commutative
8383
8484 %3(s32) = G_MUL %0, %1
8585 %4(s32) = G_ADD %2, %3
86 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
87
88 %r0 = COPY %4(s32)
89 ; CHECK: %r0 = COPY [[VREGR]]
90
91 BX_RET 14, _, implicit %r0
92 ; CHECK: BX_RET 14, _, implicit %r0
86 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
87
88 %r0 = COPY %4(s32)
89 ; CHECK: %r0 = COPY [[VREGR]]
90
91 BX_RET 14, %noreg, implicit %r0
92 ; CHECK: BX_RET 14, %noreg, implicit %r0
9393 ...
9494 ---
9595 name: test_mla_v5
117117
118118 %3(s32) = G_MUL %0, %1
119119 %4(s32) = G_ADD %3, %2
120 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
121
122 %r0 = COPY %4(s32)
123 ; CHECK: %r0 = COPY [[VREGR]]
124
125 BX_RET 14, _, implicit %r0
126 ; CHECK: BX_RET 14, _, implicit %r0
120 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
121
122 %r0 = COPY %4(s32)
123 ; CHECK: %r0 = COPY [[VREGR]]
124
125 BX_RET 14, %noreg, implicit %r0
126 ; CHECK: BX_RET 14, %noreg, implicit %r0
127127 ...
128128 ---
129129 name: test_mls
151151
152152 %3(s32) = G_MUL %0, %1
153153 %4(s32) = G_SUB %2, %3
154 ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, _
155
156 %r0 = COPY %4(s32)
157 ; CHECK: %r0 = COPY [[VREGR]]
158
159 BX_RET 14, _, implicit %r0
160 ; CHECK: BX_RET 14, _, implicit %r0
154 ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg
155
156 %r0 = COPY %4(s32)
157 ; CHECK: %r0 = COPY [[VREGR]]
158
159 BX_RET 14, %noreg, implicit %r0
160 ; CHECK: BX_RET 14, %noreg, implicit %r0
161161 ...
162162 ---
163163 name: test_no_mls
185185
186186 %3(s32) = G_MUL %0, %1
187187 %4(s32) = G_SUB %2, %3
188 ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, _, _
189 ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, _, _
190
191 %r0 = COPY %4(s32)
192 ; CHECK: %r0 = COPY [[VREGR]]
193
194 BX_RET 14, _, implicit %r0
195 ; CHECK: BX_RET 14, _, implicit %r0
188 ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg
189 ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, %noreg, %noreg
190
191 %r0 = COPY %4(s32)
192 ; CHECK: %r0 = COPY [[VREGR]]
193
194 BX_RET 14, %noreg, implicit %r0
195 ; CHECK: BX_RET 14, %noreg, implicit %r0
196196 ...
197197 ---
198198 name: test_shifts_to_revsh
237237 %r0 = COPY %9(s32)
238238 ; CHECK: %r0 = COPY [[VREGR]]
239239
240 BX_RET 14, _, implicit %r0
241 ; CHECK: BX_RET 14, _, implicit %r0
240 BX_RET 14, %noreg, implicit %r0
241 ; CHECK: BX_RET 14, %noreg, implicit %r0
242242 ...
243243 ---
244244 name: test_shifts_to_revsh_commutative
283283 %r0 = COPY %9(s32)
284284 ; CHECK: %r0 = COPY [[VREGR]]
285285
286 BX_RET 14, _, implicit %r0
287 ; CHECK: BX_RET 14, _, implicit %r0
286 BX_RET 14, %noreg, implicit %r0
287 ; CHECK: BX_RET 14, %noreg, implicit %r0
288288 ...
289289 ---
290290 name: test_shifts_no_revsh_features
328328
329329 %r0 = COPY %9(s32)
330330
331 BX_RET 14, _, implicit %r0
331 BX_RET 14, %noreg, implicit %r0
332332 ...
333333 ---
334334 name: test_shifts_no_revsh_constants
372372
373373 %r0 = COPY %9(s32)
374374
375 BX_RET 14, _, implicit %r0
375 BX_RET 14, %noreg, implicit %r0
376376 ...
377377 ---
378378 name: test_bicrr
399399 %2(s32) = G_CONSTANT i32 -1
400400 %3(s32) = G_XOR %1, %2
401401 %4(s32) = G_AND %0, %3
402 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, _, _
403
404 %r0 = COPY %4(s32)
405 ; CHECK: %r0 = COPY [[VREGR]]
406
407 BX_RET 14, _, implicit %r0
408 ; CHECK: BX_RET 14, _, implicit %r0
402 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
403
404 %r0 = COPY %4(s32)
405 ; CHECK: %r0 = COPY [[VREGR]]
406
407 BX_RET 14, %noreg, implicit %r0
408 ; CHECK: BX_RET 14, %noreg, implicit %r0
409409 ...
410410 ---
411411 name: test_bicrr_commutative
432432 %2(s32) = G_CONSTANT i32 -1
433433 %3(s32) = G_XOR %1, %2
434434 %4(s32) = G_AND %3, %0
435 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, _, _
436
437 %r0 = COPY %4(s32)
438 ; CHECK: %r0 = COPY [[VREGR]]
439
440 BX_RET 14, _, implicit %r0
441 ; CHECK: BX_RET 14, _, implicit %r0
435 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
436
437 %r0 = COPY %4(s32)
438 ; CHECK: %r0 = COPY [[VREGR]]
439
440 BX_RET 14, %noreg, implicit %r0
441 ; CHECK: BX_RET 14, %noreg, implicit %r0
442442 ...
443443 ---
444444 name: test_bicri
470470 %2(s32) = G_CONSTANT i32 -1
471471 %3(s32) = G_XOR %1, %2
472472 %4(s32) = G_AND %0, %3
473 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _
474
475 %r0 = COPY %4(s32)
476 ; CHECK: %r0 = COPY [[VREGR]]
477
478 BX_RET 14, _, implicit %r0
479 ; CHECK: BX_RET 14, _, implicit %r0
473 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
474
475 %r0 = COPY %4(s32)
476 ; CHECK: %r0 = COPY [[VREGR]]
477
478 BX_RET 14, %noreg, implicit %r0
479 ; CHECK: BX_RET 14, %noreg, implicit %r0
480480 ...
481481 ---
482482 name: test_bicri_commutative_xor
503503 %2(s32) = G_CONSTANT i32 -1
504504 %3(s32) = G_XOR %2, %1
505505 %4(s32) = G_AND %0, %3
506 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _
507
508 %r0 = COPY %4(s32)
509 ; CHECK: %r0 = COPY [[VREGR]]
510
511 BX_RET 14, _, implicit %r0
512 ; CHECK: BX_RET 14, _, implicit %r0
506 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
507
508 %r0 = COPY %4(s32)
509 ; CHECK: %r0 = COPY [[VREGR]]
510
511 BX_RET 14, %noreg, implicit %r0
512 ; CHECK: BX_RET 14, %noreg, implicit %r0
513513 ...
514514 ---
515515 name: test_bicri_commutative_and
536536 %2(s32) = G_CONSTANT i32 -1
537537 %3(s32) = G_XOR %1, %2
538538 %4(s32) = G_AND %3, %0
539 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _
540
541 %r0 = COPY %4(s32)
542 ; CHECK: %r0 = COPY [[VREGR]]
543
544 BX_RET 14, _, implicit %r0
545 ; CHECK: BX_RET 14, _, implicit %r0
539 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
540
541 %r0 = COPY %4(s32)
542 ; CHECK: %r0 = COPY [[VREGR]]
543
544 BX_RET 14, %noreg, implicit %r0
545 ; CHECK: BX_RET 14, %noreg, implicit %r0
546546 ...
547547 ---
548548 name: test_bicri_commutative_both
569569 %2(s32) = G_CONSTANT i32 -1
570570 %3(s32) = G_XOR %2, %1
571571 %4(s32) = G_AND %3, %0
572 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _
573
574 %r0 = COPY %4(s32)
575 ; CHECK: %r0 = COPY [[VREGR]]
576
577 BX_RET 14, _, implicit %r0
578 ; CHECK: BX_RET 14, _, implicit %r0
579 ...
572 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
573
574 %r0 = COPY %4(s32)
575 ; CHECK: %r0 = COPY [[VREGR]]
576
577 BX_RET 14, %noreg, implicit %r0
578 ; CHECK: BX_RET 14, %noreg, implicit %r0
579 ...
8080 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
8181
8282 %2(s32) = G_ZEXT %1(s1)
83 ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, _, _
83 ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg
8484
8585 %r0 = COPY %2(s32)
8686 ; CHECK: %r0 = COPY [[VREGEXT]]
8787
88 BX_RET 14, _, implicit %r0
89 ; CHECK: BX_RET 14, _, implicit %r0
88 BX_RET 14, %noreg, implicit %r0
89 ; CHECK: BX_RET 14, %noreg, implicit %r0
9090 ...
9191 ---
9292 name: test_trunc_and_sext_s1
110110 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
111111
112112 %2(s32) = G_SEXT %1(s1)
113 ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, _, _
114 ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, _, _
113 ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg
114 ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, %noreg, %noreg
115115
116116 %r0 = COPY %2(s32)
117117 ; CHECK: %r0 = COPY [[VREGEXT]]
118118
119 BX_RET 14, _, implicit %r0
120 ; CHECK: BX_RET 14, _, implicit %r0
119 BX_RET 14, %noreg, implicit %r0
120 ; CHECK: BX_RET 14, %noreg, implicit %r0
121121 ...
122122 ---
123123 name: test_trunc_and_sext_s8
141141 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
142142
143143 %2(s32) = G_SEXT %1(s8)
144 ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, _
144 ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, %noreg
145145
146146 %r0 = COPY %2(s32)
147147 ; CHECK: %r0 = COPY [[VREGEXT]]
148148
149 BX_RET 14, _, implicit %r0
150 ; CHECK: BX_RET 14, _, implicit %r0
149 BX_RET 14, %noreg, implicit %r0
150 ; CHECK: BX_RET 14, %noreg, implicit %r0
151151 ...
152152 ---
153153 name: test_trunc_and_zext_s16
171171 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
172172
173173 %2(s32) = G_ZEXT %1(s16)
174 ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, _
174 ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, %noreg
175175
176176 %r0 = COPY %2(s32)
177177 ; CHECK: %r0 = COPY [[VREGEXT]]
178178
179 BX_RET 14, _, implicit %r0
180 ; CHECK: BX_RET 14, _, implicit %r0
179 BX_RET 14, %noreg, implicit %r0
180 ; CHECK: BX_RET 14, %noreg, implicit %r0
181181 ...
182182 ---
183183 name: test_trunc_and_anyext_s8
206206 %r0 = COPY %2(s32)
207207 ; CHECK: %r0 = COPY [[VREGEXT]]
208208
209 BX_RET 14, _, implicit %r0
210 ; CHECK: BX_RET 14, _, implicit %r0
209 BX_RET 14, %noreg, implicit %r0
210 ; CHECK: BX_RET 14, %noreg, implicit %r0
211211 ...
212212 ---
213213 name: test_trunc_and_anyext_s16
236236 %r0 = COPY %2(s32)
237237 ; CHECK: %r0 = COPY [[VREGEXT]]
238238
239 BX_RET 14, _, implicit %r0
240 ; CHECK: BX_RET 14, _, implicit %r0
239 BX_RET 14, %noreg, implicit %r0
240 ; CHECK: BX_RET 14, %noreg, implicit %r0
241241 ...
242242 ---
243243 name: test_add_s32
261261 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
262262
263263 %2(s32) = G_ADD %0, %1
264 ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _
264 ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
265265
266266 %r0 = COPY %2(s32)
267267 ; CHECK: %r0 = COPY [[VREGSUM]]
268268
269 BX_RET 14, _, implicit %r0
270 ; CHECK: BX_RET 14, _, implicit %r0
269 BX_RET 14, %noreg, implicit %r0
270 ; CHECK: BX_RET 14, %noreg, implicit %r0
271271 ...
272272 ---
273273 name: test_add_fold_imm_s32
289289
290290 %1(s32) = G_CONSTANT i32 255
291291 %2(s32) = G_ADD %0, %1
292 ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, _, _
292 ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, %noreg, %noreg
293293
294294 %r0 = COPY %2(s32)
295295 ; CHECK: %r0 = COPY [[VREGSUM]]
296296
297 BX_RET 14, _, implicit %r0
298 ; CHECK: BX_RET 14, _, implicit %r0
297 BX_RET 14, %noreg, implicit %r0
298 ; CHECK: BX_RET 14, %noreg, implicit %r0
299299 ...
300300 ---
301301 name: test_add_no_fold_imm_s32
316316 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
317317
318318 %1(s32) = G_CONSTANT i32 65535
319 ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, _
319 ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, %noreg
320320
321321 %2(s32) = G_ADD %0, %1
322 ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _
322 ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
323323
324324 %r0 = COPY %2(s32)
325325 ; CHECK: %r0 = COPY [[VREGSUM]]
326326
327 BX_RET 14, _, implicit %r0
328 ; CHECK: BX_RET 14, _, implicit %r0
327 BX_RET 14, %noreg, implicit %r0
328 ; CHECK: BX_RET 14, %noreg, implicit %r0
329329 ...
330330 ---
331331 name: test_fadd_s32
349349 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
350350
351351 %2(s32) = G_FADD %0, %1
352 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, _
352 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, %noreg
353353
354354 %s0 = COPY %2(s32)
355355 ; CHECK: %s0 = COPY [[VREGSUM]]
356356
357 BX_RET 14, _, implicit %s0
358 ; CHECK: BX_RET 14, _, implicit %s0
357 BX_RET 14, %noreg, implicit %s0
358 ; CHECK: BX_RET 14, %noreg, implicit %s0
359359 ...
360360 ---
361361 name: test_fadd_s64
379379 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
380380
381381 %2(s64) = G_FADD %0, %1
382 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, _
382 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, %noreg
383383
384384 %d0 = COPY %2(s64)
385385 ; CHECK: %d0 = COPY [[VREGSUM]]
386386
387 BX_RET 14, _, implicit %d0
388 ; CHECK: BX_RET 14, _, implicit %d0
387 BX_RET 14, %noreg, implicit %d0
388 ; CHECK: BX_RET 14, %noreg, implicit %d0
389389 ...
390390 ---
391391 name: test_fsub_s32
409409 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
410410
411411 %2(s32) = G_FSUB %0, %1
412 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, _
412 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, %noreg
413413
414414 %s0 = COPY %2(s32)
415415 ; CHECK: %s0 = COPY [[VREGSUM]]
416416
417 BX_RET 14, _, implicit %s0
418 ; CHECK: BX_RET 14, _, implicit %s0
417 BX_RET 14, %noreg, implicit %s0
418 ; CHECK: BX_RET 14, %noreg, implicit %s0
419419 ...
420420 ---
421421 name: test_fsub_s64
439439 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
440440
441441 %2(s64) = G_FSUB %0, %1
442 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, _
442 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, %noreg
443443
444444 %d0 = COPY %2(s64)
445445 ; CHECK: %d0 = COPY [[VREGSUM]]
446446
447 BX_RET 14, _, implicit %d0
448 ; CHECK: BX_RET 14, _, implicit %d0
447 BX_RET 14, %noreg, implicit %d0
448 ; CHECK: BX_RET 14, %noreg, implicit %d0
449449 ...
450450 ---
451451 name: test_fmul_s32
469469 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
470470
471471 %2(s32) = G_FMUL %0, %1
472 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, _
472 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, %noreg
473473
474474 %s0 = COPY %2(s32)
475475 ; CHECK: %s0 = COPY [[VREGSUM]]
476476
477 BX_RET 14, _, implicit %s0
478 ; CHECK: BX_RET 14, _, implicit %s0
477 BX_RET 14, %noreg, implicit %s0
478 ; CHECK: BX_RET 14, %noreg, implicit %s0
479479 ...
480480 ---
481481 name: test_fmul_s64
499499 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
500500
501501 %2(s64) = G_FMUL %0, %1
502 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, _
502 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, %noreg
503503
504504 %d0 = COPY %2(s64)
505505 ; CHECK: %d0 = COPY [[VREGSUM]]
506506
507 BX_RET 14, _, implicit %d0
508 ; CHECK: BX_RET 14, _, implicit %d0
507 BX_RET 14, %noreg, implicit %d0
508 ; CHECK: BX_RET 14, %noreg, implicit %d0
509509 ...
510510 ---
511511 name: test_fdiv_s32
529529 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
530530
531531 %2(s32) = G_FDIV %0, %1
532 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, _
532 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, %noreg
533533
534534 %s0 = COPY %2(s32)
535535 ; CHECK: %s0 = COPY [[VREGSUM]]
536536
537 BX_RET 14, _, implicit %s0
538 ; CHECK: BX_RET 14, _, implicit %s0
537 BX_RET 14, %noreg, implicit %s0
538 ; CHECK: BX_RET 14, %noreg, implicit %s0
539539 ...
540540 ---
541541 name: test_fdiv_s64
559559 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
560560
561561 %2(s64) = G_FDIV %0, %1
562 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, _
562 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, %noreg
563563
564564 %d0 = COPY %2(s64)
565565 ; CHECK: %d0 = COPY [[VREGSUM]]
566566
567 BX_RET 14, _, implicit %d0
568 ; CHECK: BX_RET 14, _, implicit %d0
567 BX_RET 14, %noreg, implicit %d0
568 ; CHECK: BX_RET 14, %noreg, implicit %d0
569569 ...
570570 ---
571571 name: test_sub_s32
589589 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
590590
591591 %2(s32) = G_SUB %0, %1
592 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, _, _
592 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
593593
594594 %r0 = COPY %2(s32)
595595 ; CHECK: %r0 = COPY [[VREGRES]]
596596
597 BX_RET 14, _, implicit %r0
598 ; CHECK: BX_RET 14, _, implicit %r0
597 BX_RET 14, %noreg, implicit %r0
598 ; CHECK: BX_RET 14, %noreg, implicit %r0
599599 ...
600600 ---
601601 name: test_sub_imm_s32
617617
618618 %1(s32) = G_CONSTANT i32 17
619619 %2(s32) = G_SUB %0, %1
620 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, _, _
620 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, %noreg, %noreg
621621
622622 %r0 = COPY %2(s32)
623623 ; CHECK: %r0 = COPY [[VREGRES]]
624624
625 BX_RET 14, _, implicit %r0
626 ; CHECK: BX_RET 14, _, implicit %r0
625 BX_RET 14, %noreg, implicit %r0
626 ; CHECK: BX_RET 14, %noreg, implicit %r0
627627 ...
628628 ---
629629 name: test_sub_rev_imm_s32
645645
646646 %1(s32) = G_CONSTANT i32 17
647647 %2(s32) = G_SUB %1, %0
648 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, _, _
648 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, %noreg, %noreg
649649
650650 %r0 = COPY %2(s32)
651651 ; CHECK: %r0 = COPY [[VREGRES]]
652652
653 BX_RET 14, _, implicit %r0
654 ; CHECK: BX_RET 14, _, implicit %r0
653 BX_RET 14, %noreg, implicit %r0
654 ; CHECK: BX_RET 14, %noreg, implicit %r0
655655 ...
656656 ---
657657 name: test_mul_s32
675675 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
676676
677677 %2(s32) = G_MUL %0, %1
678 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, _, _
678 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, %noreg, %noreg
679679
680680 %r0 = COPY %2(s32)
681681 ; CHECK: %r0 = COPY [[VREGRES]]
682682
683 BX_RET 14, _, implicit %r0
684 ; CHECK: BX_RET 14, _, implicit %r0
683 BX_RET 14, %noreg, implicit %r0
684 ; CHECK: BX_RET 14, %noreg, implicit %r0
685685 ...
686686 ---
687687 name: test_mulv5_s32
705705 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
706706
707707 %2(s32) = G_MUL %0, %1
708 ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, _, _
708 ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg
709709
710710 %r0 = COPY %2(s32)
711711 ; CHECK: %r0 = COPY [[VREGRES]]
712712
713 BX_RET 14, _, implicit %r0
714 ; CHECK: BX_RET 14, _, implicit %r0
713 BX_RET 14, %noreg, implicit %r0
714 ; CHECK: BX_RET 14, %noreg, implicit %r0
715715 ...
716716 ---
717717 name: test_sdiv_s32
735735 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
736736
737737 %2(s32) = G_SDIV %0, %1
738 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, _
738 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, %noreg
739739
740740 %r0 = COPY %2(s32)
741741 ; CHECK: %r0 = COPY [[VREGRES]]
742742
743 BX_RET 14, _, implicit %r0
744 ; CHECK: BX_RET 14, _, implicit %r0
743 BX_RET 14, %noreg, implicit %r0
744 ; CHECK: BX_RET 14, %noreg, implicit %r0
745745 ...
746746 ---
747747 name: test_udiv_s32
765765 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
766766
767767 %2(s32) = G_UDIV %0, %1
768 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, _
768 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, %noreg
769769
770770 %r0 = COPY %2(s32)
771771 ; CHECK: %r0 = COPY [[VREGRES]]
772772
773 BX_RET 14, _, implicit %r0
774 ; CHECK: BX_RET 14, _, implicit %r0
773 BX_RET 14, %noreg, implicit %r0
774 ; CHECK: BX_RET 14, %noreg, implicit %r0
775775 ...
776776 ---
777777 name: test_lshr_s32
795795 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
796796
797797 %2(s32) = G_LSHR %0, %1
798 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, _, _
798 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, %noreg, %noreg
799799
800800 %r0 = COPY %2(s32)
801801 ; CHECK: %r0 = COPY [[VREGRES]]
802802
803 BX_RET 14, _, implicit %r0
804 ; CHECK: BX_RET 14, _, implicit %r0
803 BX_RET 14, %noreg, implicit %r0
804 ; CHECK: BX_RET 14, %noreg, implicit %r0
805805 ...
806806 ---
807807 name: test_ashr_s32
825825 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
826826
827827 %2(s32) = G_ASHR %0, %1
828 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, _, _
828 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, %noreg, %noreg
829829
830830 %r0 = COPY %2(s32)
831831 ; CHECK: %r0 = COPY [[VREGRES]]
832832
833 BX_RET 14, _, implicit %r0
834 ; CHECK: BX_RET 14, _, implicit %r0
833 BX_RET 14, %noreg, implicit %r0
834 ; CHECK: BX_RET 14, %noreg, implicit %r0
835835 ...
836836 ---
837837 name: test_shl_s32
855855 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
856856
857857 %2(s32) = G_SHL %0, %1
858 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, _, _
858 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, %noreg, %noreg
859859
860860 %r0 = COPY %2(s32)
861861 ; CHECK: %r0 = COPY [[VREGRES]]
862862
863 BX_RET 14, _, implicit %r0
864 ; CHECK: BX_RET 14, _, implicit %r0
863 BX_RET 14, %noreg, implicit %r0
864 ; CHECK: BX_RET 14, %noreg, implicit %r0
865865 ...
866866 ---
867867 name: test_load_from_stack
887887 liveins: %r0, %r1, %r2, %r3
888888
889889 %0(p0) = G_FRAME_INDEX %fixed-stack.2
890 ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
890 ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, %noreg, %noreg
891891
892892 %1(s32) = G_LOAD %0(p0) :: (load 4)
893 ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, _
893 ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, %noreg
894894
895895 %r0 = COPY %1
896896 ; CHECK: %r0 = COPY [[LD32VREG]]
897897
898898 %2(p0) = G_FRAME_INDEX %fixed-stack.0
899 ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, _, _
899 ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, %noreg, %noreg
900900
901901 %3(s1) = G_LOAD %2(p0) :: (load 1)
902 ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, _
902 ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, %noreg
903903
904904 %4(s32) = G_ANYEXT %3(s1)
905905 ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
907907 %r0 = COPY %4
908908 ; CHECK: %r0 = COPY [[RES]]
909909
910 BX_RET 14, _
911 ; CHECK: BX_RET 14, _
910 BX_RET 14, %noreg
911 ; CHECK: BX_RET 14, %noreg
912912 ...
913913 ---
914914 name: test_load_f32
928928 ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0
929929
930930 %1(s32) = G_LOAD %0(p0) :: (load 4)
931 ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, _
931 ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, %noreg
932932
933933 %s0 = COPY %1
934934 ; CHECK: %s0 = COPY %[[V]]
935935
936 BX_RET 14, _, implicit %s0
937 ; CHECK: BX_RET 14, _, implicit %s0
936 BX_RET 14, %noreg, implicit %s0
937 ; CHECK: BX_RET 14, %noreg, implicit %s0
938938 ...
939939 ---
940940 name: test_load_f64
954954 ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0
955955
956956 %1(s64) = G_LOAD %0(p0) :: (load 8)
957 ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, _
957 ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, %noreg
958958
959959 %d0 = COPY %1
960960 ; CHECK: %d0 = COPY %[[V]]
961961
962 BX_RET 14, _, implicit %d0
963 ; CHECK: BX_RET 14, _, implicit %d0
962 BX_RET 14, %noreg, implicit %d0
963 ; CHECK: BX_RET 14, %noreg, implicit %d0
964964 ...
965965 ---
966966 name: test_stores
994994 %2(s16) = G_TRUNC %3(s32)
995995
996996 G_STORE %1(s8), %0(p0) :: (store 1)
997 ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, _
997 ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, %noreg
998998
999999 G_STORE %2(s16), %0(p0) :: (store 2)
1000 ; CHECK: STRH %[[I16]], %[[P]], _, 0, 14, _
1000 ; CHECK: STRH %[[I16]], %[[P]], %noreg, 0, 14, %noreg
10011001
10021002 G_STORE %3(s32), %0(p0) :: (store 4)
1003 ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, _
1003 ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, %noreg
10041004
10051005 G_STORE %4(s32), %0(p0) :: (store 4)
1006 ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, _
1006 ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, %noreg
10071007
10081008 G_STORE %5(s64), %0(p0) :: (store 8)
1009 ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, _
1010
1011 BX_RET 14, _
1009 ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, %noreg
1010
1011 BX_RET 14, %noreg
10121012 ...
10131013 ---
10141014 name: test_gep
10321032 ; CHECK: %[[OFF:[0-9]+]]:gpr = COPY %r1
10331033
10341034 %2(p0) = G_GEP %0, %1(s32)
1035 ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, _, _
1035 ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, %noreg, %noreg
10361036
10371037 %r0 = COPY %2(p0)
1038 BX_RET 14, _, implicit %r0
1038 BX_RET 14, %noreg, implicit %r0
10391039 ...
10401040 ---
10411041 name: test_constant_imm
10491049 body: |
10501050 bb.0:
10511051 %0(s32) = G_CONSTANT 42
1052 ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, _, _
1052 ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg
10531053
10541054 %r0 = COPY %0(s32)
1055 BX_RET 14, _, implicit %r0
1055 BX_RET 14, %noreg, implicit %r0
10561056 ...
10571057 ---
10581058 name: test_constant_cimm
10681068 ; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm.
10691069 ; We still want to see the same thing in the output though.
10701070 %0(s32) = G_CONSTANT i32 42
1071 ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, _, _
1071 ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg
10721072
10731073 %r0 = COPY %0(s32)
1074 BX_RET 14, _, implicit %r0
1074 BX_RET 14, %noreg, implicit %r0
10751075 ...
10761076 ---
10771077 name: test_select_s32
10991099 ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY [[VREGY]]
11001100
11011101 %3(s32) = G_SELECT %2(s1), %0, %1
1102 ; CHECK: CMPri [[VREGC]], 0, 14, _, implicit-def %cpsr
1102 ; CHECK: CMPri [[VREGC]], 0, 14, %noreg, implicit-def %cpsr
11031103 ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
11041104
11051105 %r0 = COPY %3(s32)
11061106 ; CHECK: %r0 = COPY [[RES]]
11071107
1108 BX_RET 14, _, implicit %r0
1109 ; CHECK: BX_RET 14, _, implicit %r0
1108 BX_RET 14, %noreg, implicit %r0
1109 ; CHECK: BX_RET 14, %noreg, implicit %r0
11101110 ...
11111111 ---
11121112 name: test_select_ptr
11381138 ; CHECK: [[VREGD:%[0-9]+]]:gpr = COPY [[VREGC]]
11391139
11401140 %4(p0) = G_SELECT %3(s1), %0, %1
1141 ; CHECK: CMPri [[VREGD]], 0, 14, _, implicit-def %cpsr
1141 ; CHECK: CMPri [[VREGD]], 0, 14, %noreg, implicit-def %cpsr
11421142 ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
11431143
11441144 %r0 = COPY %4(p0)
11451145 ; CHECK: %r0 = COPY [[RES]]
11461146
1147 BX_RET 14, _, implicit %r0
1148 ; CHECK: BX_RET 14, _, implicit %r0
1147 BX_RET 14, %noreg, implicit %r0
1148 ; CHECK: BX_RET 14, %noreg, implicit %r0
11491149 ...
11501150 ---
11511151 name: test_br
11691169 ; CHECK: [[COND:%[0-9]+]]:gpr = COPY [[COND32]]
11701170
11711171 G_BRCOND %1(s1), %bb.1
1172 ; CHECK: TSTri [[COND]], 1, 14, _, implicit-def %cpsr
1172 ; CHECK: TSTri [[COND]], 1, 14, %noreg, implicit-def %cpsr
11731173 ; CHECK: Bcc %bb.1, 1, %cpsr
11741174 G_BR %bb.2
11751175 ; CHECK: B %bb.2
11841184 bb.2:
11851185 ; CHECK: bb.2
11861186
1187 BX_RET 14, _
1188 ; CHECK: BX_RET 14, _
1187 BX_RET 14, %noreg
1188 ; CHECK: BX_RET 14, %noreg
11891189 ...
11901190 ---
11911191 name: test_soft_fp_double
12221222 %r1 = COPY %4
12231223 ; CHECK: %r1 = COPY [[OUT2]]
12241224
1225 BX_RET 14, _, implicit %r0, implicit %r1
1226 ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
1227 ...
1225 BX_RET 14, %noreg, implicit %r0, implicit %r1
1226 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
1227 ...
22
33 define void @test_void_return() {
44 ; CHECK-LABEL: name: test_void_return
5 ; CHECK: BX_RET 14, _
5 ; CHECK: BX_RET 14, %noreg
66 entry:
77 ret void
88 }
1717 ; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]]
1818 ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]]
1919 ; CHECK: %r0 = COPY [[EXT]](s32)
20 ; CHECK: BX_RET 14, _, implicit %r0
20 ; CHECK: BX_RET 14, %noreg, implicit %r0
2121 entry:
2222 %sum = add i1 %x, %y
2323 ret i1 %sum
3333 ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]]
3434 ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
3535 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
36 ; CHECK: BX_RET 14, _, implicit %r0
36 ; CHECK: BX_RET 14, %noreg, implicit %r0
3737 entry:
3838 %sum = add i8 %x, %y
3939 ret i8 %sum
4949 ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]]
5050 ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
5151 ; CHECK: %r0 = COPY [[RES_EXT]](s32)
52 ; CHECK: BX_RET 14, _, implicit %r0
52 ; CHECK: BX_RET 14, %noreg, implicit %r0
5353 entry:
5454 %res = sub i8 %x, %y
5555 ret i8 %res
6262 ; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
6363 ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]
6464 ; CHECK: %r0 = COPY [[VREGEXT]](s32)
65 ; CHECK: BX_RET 14, _, implicit %r0
65 ; CHECK: BX_RET 14, %noreg, implicit %r0
6666 entry:
6767 ret i8 %x
6868 }
7777 ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]]
7878 ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
7979 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
80 ; CHECK: BX_RET 14, _, implicit %r0
80 ; CHECK: BX_RET 14, %noreg, implicit %r0
8181 entry:
8282 %sum = add i16 %x, %y
8383 ret i16 %sum
9393 ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]]
9494 ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
9595 ; CHECK: %r0 = COPY [[RES_EXT]](s32)
96 ; CHECK: BX_RET 14, _, implicit %r0
96 ; CHECK: BX_RET 14, %noreg, implicit %r0
9797 entry:
9898 %res = sub i16 %x, %y
9999 ret i16 %res
106106 ; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
107107 ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]
108108 ; CHECK: %r0 = COPY [[VREGEXT]](s32)
109 ; CHECK: BX_RET 14, _, implicit %r0
109 ; CHECK: BX_RET 14, %noreg, implicit %r0
110110 entry:
111111 ret i16 %x
112112 }
118118 ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
119119 ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]]
120120 ; CHECK: %r0 = COPY [[SUM]](s32)
121 ; CHECK: BX_RET 14, _, implicit %r0
121 ; CHECK: BX_RET 14, %noreg, implicit %r0
122122 entry:
123123 %sum = add i32 %x, %y
124124 ret i32 %sum
131131 ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
132132 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]]
133133 ; CHECK: %r0 = COPY [[RES]](s32)
134 ; CHECK: BX_RET 14, _, implicit %r0
134 ; CHECK: BX_RET 14, %noreg, implicit %r0
135135 entry:
136136 %res = sub i32 %x, %y
137137 ret i32 %res
148148 ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4
149149 ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]]
150150 ; CHECK: %r0 = COPY [[SUM]]
151 ; CHECK: BX_RET 14, _, implicit %r0
151 ; CHECK: BX_RET 14, %noreg, implicit %r0
152152 entry:
153153 %sum = add i32 %p2, %p5
154154 ret i32 %sum
169169 ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]]
170170 ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
171171 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
172 ; CHECK: BX_RET 14, _, implicit %r0
172 ; CHECK: BX_RET 14, %noreg, implicit %r0
173173 entry:
174174 %sum = add i16 %p1, %p5
175175 ret i16 %sum
190190 ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
191191 ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
192192 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
193 ; CHECK: BX_RET 14, _, implicit %r0
193 ; CHECK: BX_RET 14, %noreg, implicit %r0
194194 entry:
195195 %sum = add i8 %p2, %p4
196196 ret i8 %sum
210210 ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
211211 ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
212212 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
213 ; CHECK: BX_RET 14, _, implicit %r0
213 ; CHECK: BX_RET 14, %noreg, implicit %r0
214214 entry:
215215 %sum = add i8 %p2, %p4
216216 ret i8 %sum
228228 ; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]]
229229 ; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]]
230230 ; CHECK: %r0 = COPY [[VREGP5ZEXT]]
231 ; CHECK: BX_RET 14, _, implicit %r0
231 ; CHECK: BX_RET 14, %noreg, implicit %r0
232232 entry:
233233 ret i16 %p5
234234 }
250250 ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0
251251 ; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4
252252 ; CHECK: %r0 = COPY [[VREGV]]
253 ; CHECK: BX_RET 14, _, implicit %r0
253 ; CHECK: BX_RET 14, %noreg, implicit %r0
254254 entry:
255255 %v = load i32*, i32** %p
256256 ret i32* %v
265265 ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4
266266 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4
267267 ; CHECK: %r0 = COPY [[VREGV]]
268 ; CHECK: BX_RET 14, _, implicit %r0
268 ; CHECK: BX_RET 14, %noreg, implicit %r0
269269 entry:
270270 %v = load i32, i32* %p
271271 ret i32 %v
283283 ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
284284 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]]
285285 ; CHECK: %r0 = COPY [[VREGV]]
286 ; CHECK: BX_RET 14, _, implicit %r0
286 ; CHECK: BX_RET 14, %noreg, implicit %r0
287287 entry:
288288 %v = fadd float %p1, %p5
289289 ret float %v
312312 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4
313313 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]]
314314 ; CHECK: %s0 = COPY [[VREGV]]
315 ; CHECK: BX_RET 14, _, implicit %s0
315 ; CHECK: BX_RET 14, %noreg, implicit %s0
316316 entry:
317317 %v = fadd float %p1, %q1
318318 ret float %v
333333 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
334334 ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
335335 ; CHECK: %d0 = COPY [[VREGV]]
336 ; CHECK: BX_RET 14, _, implicit %d0
336 ; CHECK: BX_RET 14, %noreg, implicit %d0
337337 entry:
338338 %v = fadd double %p1, %q1
339339 ret double %v
359359 ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
360360 ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
361361 ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
362 ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
362 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
363363 entry:
364364 %v = fadd double %p1, %p5
365365 ret double %v
381381 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
382382 ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
383383 ; CHECK: %d0 = COPY [[VREGV]]
384 ; CHECK: BX_RET 14, _, implicit %d0
384 ; CHECK: BX_RET 14, %noreg, implicit %d0
385385 entry:
386386 %v = fadd double %p1, %q1
387387 ret double %v
404404 ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
405405 ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
406406 ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
407 ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
407 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
408408 entry:
409409 %v = fadd double %p0, %p1
410410 ret double %v
427427 ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
428428 ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
429429 ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
430 ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
430 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
431431 entry:
432432 %v = fadd double %p0, %p1
433433 ret double %v
5454 %2(s32) = G_SDIV %0, %1
5555 ; CHECK: %r0 = COPY [[R]]
5656 %r0 = COPY %2(s32)
57 BX_RET 14, _, implicit %r0
57 BX_RET 14, %noreg, implicit %r0
5858 ...
5959 ---
6060 name: test_udiv_i32
9090 %2(s32) = G_UDIV %0, %1
9191 ; CHECK: %r0 = COPY [[R]]
9292 %r0 = COPY %2(s32)
93 BX_RET 14, _, implicit %r0
93 BX_RET 14, %noreg, implicit %r0
9494 ...
9595 ---
9696 name: test_sdiv_i16
144144 ; CHECK: %r0 = COPY [[R]]
145145 %5(s32) = G_SEXT %4(s16)
146146 %r0 = COPY %5(s32)
147 BX_RET 14, _, implicit %r0
147 BX_RET 14, %noreg, implicit %r0
148148 ...
149149 ---
150150 name: test_udiv_i16
196196 ; CHECK: %r0 = COPY [[R]]
197197 %5(s32) = G_ZEXT %4(s16)
198198 %r0 = COPY %5(s32)
199 BX_RET 14, _, implicit %r0
199 BX_RET 14, %noreg, implicit %r0
200200 ...
201201 ---
202202 name: test_sdiv_i8
250250 ; CHECK: %r0 = COPY [[R]]
251251 %5(s32) = G_SEXT %4(s8)
252252 %r0 = COPY %5(s32)
253 BX_RET 14, _, implicit %r0
253 BX_RET 14, %noreg, implicit %r0
254254 ...
255255 ---
256256 name: test_udiv_i8
302302 ; CHECK: %r0 = COPY [[R]]
303303 %5(s32) = G_ZEXT %4(s8)
304304 %r0 = COPY %5(s32)
305 BX_RET 14, _, implicit %r0
305 BX_RET 14, %noreg, implicit %r0
306306 ...
307307 ---
308308 name: test_srem_i32
340340 %2(s32) = G_SREM %0, %1
341341 ; CHECK: %r0 = COPY [[R]]
342342 %r0 = COPY %2(s32)
343 BX_RET 14, _, implicit %r0
343 BX_RET 14, %noreg, implicit %r0
344344 ...
345345 ---
346346 name: test_urem_i32
378378 %2(s32) = G_UREM %0, %1
379379 ; CHECK: %r0 = COPY [[R]]
380380 %r0 = COPY %2(s32)
381 BX_RET 14, _, implicit %r0
381 BX_RET 14, %noreg, implicit %r0
382382 ...
383383 ---
384384 name: test_srem_i16
434434 ; CHECK: %r0 = COPY [[R]]
435435 %5(s32) = G_SEXT %4(s16)
436436 %r0 = COPY %5(s32)
437 BX_RET 14, _, implicit %r0
437 BX_RET 14, %noreg, implicit %r0
438438 ...
439439 ---
440440 name: test_urem_i16
488488 ; CHECK: %r0 = COPY [[R]]
489489 %5(s32) = G_ZEXT %4(s16)
490490 %r0 = COPY %5(s32)
491 BX_RET 14, _, implicit %r0
491 BX_RET 14, %noreg, implicit %r0
492492 ...
493493 ---
494494 name: test_srem_i8
544544 ; CHECK: %r0 = COPY [[R]]
545545 %5(s32) = G_SEXT %4(s8)
546546 %r0 = COPY %5(s32)
547 BX_RET 14, _, implicit %r0
547 BX_RET 14, %noreg, implicit %r0
548548 ...
549549 ---
550550 name: test_urem_i8
598598 ; CHECK: %r0 = COPY [[R]]
599599 %5(s32) = G_ZEXT %4(s8)
600600 %r0 = COPY %5(s32)
601 BX_RET 14, _, implicit %r0
602 ...
601 BX_RET 14, %noreg, implicit %r0
602 ...
9292 %2(s32) = G_FREM %0, %1
9393 ; CHECK: %r0 = COPY [[R]]
9494 %r0 = COPY %2(s32)
95 BX_RET 14, _, implicit %r0
95 BX_RET 14, %noreg, implicit %r0
9696 ...
9797 ---
9898 name: test_frem_double
150150 %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
151151 %r0 = COPY %7(s32)
152152 %r1 = COPY %8(s32)
153 BX_RET 14, _, implicit %r0, implicit %r1
153 BX_RET 14, %noreg, implicit %r0, implicit %r1
154154 ...
155155 ---
156156 name: test_fpow_float
187187 %2(s32) = G_FPOW %0, %1
188188 ; CHECK: %r0 = COPY [[R]]
189189 %r0 = COPY %2(s32)
190 BX_RET 14, _, implicit %r0
190 BX_RET 14, %noreg, implicit %r0
191191 ...
192192 ---
193193 name: test_fpow_double
245245 %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
246246 %r0 = COPY %7(s32)
247247 %r1 = COPY %8(s32)
248 BX_RET 14, _, implicit %r0, implicit %r1
248 BX_RET 14, %noreg, implicit %r0, implicit %r1
249249 ...
250250 ---
251251 name: test_fadd_float
280280 %2(s32) = G_FADD %0, %1
281281 ; CHECK: %r0 = COPY [[R]]
282282 %r0 = COPY %2(s32)
283 BX_RET 14, _, implicit %r0
283 BX_RET 14, %noreg, implicit %r0
284284 ...
285285 ---
286286 name: test_fadd_double
332332 %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
333333 %r0 = COPY %7(s32)
334334 %r1 = COPY %8(s32)
335 BX_RET 14, _, implicit %r0, implicit %r1
335 BX_RET 14, %noreg, implicit %r0, implicit %r1
336336 ...
337337 ---
338338 name: test_fsub_float
367367 %2(s32) = G_FSUB %0, %1
368368 ; CHECK: %r0 = COPY [[R]]
369369 %r0 = COPY %2(s32)
370 BX_RET 14, _, implicit %r0
370 BX_RET 14, %noreg, implicit %r0
371371 ...
372372 ---
373373 name: test_fsub_double
419419 %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
420420 %r0 = COPY %7(s32)
421421 %r1 = COPY %8(s32)
422 BX_RET 14, _, implicit %r0, implicit %r1
422 BX_RET 14, %noreg, implicit %r0, implicit %r1
423423 ...
424424 ---
425425 name: test_fmul_float
454454 %2(s32) = G_FMUL %0, %1
455455 ; CHECK: %r0 = COPY [[R]]
456456 %r0 = COPY %2(s32)
457 BX_RET 14, _, implicit %r0
457 BX_RET 14, %noreg, implicit %r0
458458 ...
459459 ---
460460 name: test_fmul_double
506506 %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
507507 %r0 = COPY %7(s32)
508508 %r1 = COPY %8(s32)
509 BX_RET 14, _, implicit %r0, implicit %r1
509 BX_RET 14, %noreg, implicit %r0, implicit %r1
510510 ...
511511 ---
512512 name: test_fdiv_float
541541 %2(s32) = G_FDIV %0, %1
542542 ; CHECK: %r0 = COPY [[R]]
543543 %r0 = COPY %2(s32)
544 BX_RET 14, _, implicit %r0
544 BX_RET 14, %noreg, implicit %r0
545545 ...
546546 ---
547547 name: test_fdiv_double
593593 %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
594594 %r0 = COPY %7(s32)
595595 %r1 = COPY %8(s32)
596 BX_RET 14, _, implicit %r0, implicit %r1
596 BX_RET 14, %noreg, implicit %r0, implicit %r1
597597 ...
598598 ---
599599 name: test_fcmp_true_s32
617617 %2(s1) = G_FCMP floatpred(true), %0(s32), %1
618618 %3(s32) = G_ZEXT %2(s1)
619619 %r0 = COPY %3(s32)
620 BX_RET 14, _, implicit %r0
620 BX_RET 14, %noreg, implicit %r0
621621 ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
622622 ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
623623 ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
654654