llvm.org GIT mirror llvm / e5af2d3
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63266 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 10 years ago
6 changed file(s) with 567 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
779779 SDValue CombineTo(SDNode *N, const std::vector &To);
780780 SDValue CombineTo(SDNode *N, SDValue Res);
781781 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1);
782
783 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
782784 };
783785
784786 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
101101 SDValue To[] = { Res0, Res1 };
102102 return CombineTo(N, To, 2, AddTo);
103103 }
104
105 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
104106
105107 private:
106108
297299 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
298300 }
299301
302 void TargetLowering::DAGCombinerInfo::
303 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
304 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
305 }
300306
301307 //===----------------------------------------------------------------------===//
302308 // Helper Functions
538544 return SDValue(N, 0);
539545 }
540546
547 void
548 DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
549 TLO) {
550 // Replace all uses. If any nodes become isomorphic to other nodes and
551 // are deleted, make sure to remove them from our worklist.
552 WorkListRemover DeadNodes(*this);
553 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
554
555 // Push the new node and any (possibly new) users onto the worklist.
556 AddToWorkList(TLO.New.getNode());
557 AddUsersToWorkList(TLO.New.getNode());
558
559 // Finally, if the node is now dead, remove it from the graph. The node
560 // may not be dead if the replacement process recursively simplified to
561 // something else needing this node.
562 if (TLO.Old.getNode()->use_empty()) {
563 removeFromWorkList(TLO.Old.getNode());
564
565 // If the operands of this node are only used by the node, they will now
566 // be dead. Make sure to visit them first to delete dead nodes early.
567 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
568 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
569 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
570
571 DAG.DeleteNode(TLO.Old.getNode());
572 }
573 }
574
541575 /// SimplifyDemandedBits - Check the specified integer node value to see if
542576 /// it can be simplified or if things it uses can be simplified by bit
543577 /// propagation. If so, return true.
556590 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
557591 DOUT << '\n';
558592
559 // Replace all uses. If any nodes become isomorphic to other nodes and
560 // are deleted, make sure to remove them from our worklist.
561 WorkListRemover DeadNodes(*this);
562 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
563
564 // Push the new node and any (possibly new) users onto the worklist.
565 AddToWorkList(TLO.New.getNode());
566 AddUsersToWorkList(TLO.New.getNode());
567
568 // Finally, if the node is now dead, remove it from the graph. The node
569 // may not be dead if the replacement process recursively simplified to
570 // something else needing this node.
571 if (TLO.Old.getNode()->use_empty()) {
572 removeFromWorkList(TLO.Old.getNode());
573
574 // If the operands of this node are only used by the node, they will now
575 // be dead. Make sure to visit them first to delete dead nodes early.
576 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
577 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
578 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
579
580 DAG.DeleteNode(TLO.Old.getNode());
581 }
593 CommitTargetLoweringOpt(TLO);
582594 return true;
583595 }
584596
723723 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
724724 const APInt &Demanded) {
725725 // FIXME: ISD::SELECT, ISD::SELECT_CC
726 switch(Op.getOpcode()) {
726 switch (Op.getOpcode()) {
727727 default: break;
728728 case ISD::AND:
729729 case ISD::OR:
10531053 }
10541054 break;
10551055 case ISD::SRA:
1056 // If this is an arithmetic shift right and only the low-bit is set, we can
1057 // always convert this into a logical shr, even if the shift amount is
1058 // variable. The low bit of the shift cannot be an input sign bit unless
1059 // the shift amount is >= the size of the datatype, which is undefined.
1060 if (DemandedMask == 1)
1061 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, Op.getValueType(),
1062 Op.getOperand(0), Op.getOperand(1)));
1063
10561064 if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) {
10571065 MVT VT = Op.getValueType();
10581066 unsigned ShAmt = SA->getZExtValue();
13311339 return 1;
13321340 }
13331341
1342 static bool ValueHasAtMostOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1343 // Logical shift right or left won't ever introduce new set bits.
1344 // We check for this case because we don't care which bits are
1345 // set, but ComputeMaskedBits won't know anything unless it can
1346 // determine which specific bits may be set.
1347 if (Val.getOpcode() == ISD::SHL || Val.getOpcode() == ISD::SRL)
1348 return ValueHasAtMostOneBitSet(Val.getOperand(0), DAG);
1349
1350 MVT OpVT = Val.getValueType();
1351 unsigned BitWidth = OpVT.getSizeInBits();
1352 APInt Mask = APInt::getAllOnesValue(BitWidth);
1353 APInt KnownZero, KnownOne;
1354 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1355 return KnownZero.countPopulation() == BitWidth - 1;
1356 }
13341357
13351358 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
13361359 /// and cc. If it is unable to simplify it, return a null SDValue.
17901813 }
17911814 }
17921815 }
1816
1817 // Simpify x&y == y to x&y == 0 if y has exactly one bit set.
1818 if (N0.getOpcode() == ISD::AND)
1819 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1820 if (ValueHasAtMostOneBitSet(N1, DAG)) {
1821 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1822 SDValue Zero = DAG.getConstant(0, N1.getValueType());
1823 return DAG.getSetCC(VT, N0, Zero, Cond);
1824 }
1825 }
1826 if (N1.getOpcode() == ISD::AND)
1827 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1828 if (ValueHasAtMostOneBitSet(N0, DAG)) {
1829 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1830 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1831 return DAG.getSetCC(VT, N1, Zero, Cond);
1832 }
1833 }
17931834 }
17941835
17951836 // Fold away ALL boolean setcc's.
51135113 SDValue Op1 = Op.getOperand(1);
51145114 ISD::CondCode CC = cast(Op.getOperand(2))->get();
51155115
5116 // Lower (X & (1 << N)) == 0 to BT.
5117 // Lower ((X >>u N) & 1) != 0 to BT.
5118 // Lower ((X >>s N) & 1) != 0 to BT.
5116 // Lower (X & (1 << N)) == 0 to BT(X, N).
5117 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5118 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
51195119 if (Op0.getOpcode() == ISD::AND &&
51205120 Op0.hasOneUse() &&
51215121 Op1.getOpcode() == ISD::Constant &&
5122 Op0.getOperand(1).getOpcode() == ISD::Constant &&
5122 cast(Op1)->getZExtValue() == 0 &&
51235123 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5124 ConstantSDNode *AndRHS = cast(Op0.getOperand(1));
5125 ConstantSDNode *CmpRHS = cast(Op1);
5126 SDValue AndLHS = Op0.getOperand(0);
5127 if (CmpRHS->getZExtValue() == 0 && AndRHS->getZExtValue() == 1 &&
5128 AndLHS.getOpcode() == ISD::SRL) {
5129 SDValue LHS = AndLHS.getOperand(0);
5130 SDValue RHS = AndLHS.getOperand(1);
5131
5124 SDValue LHS, RHS;
5125 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5126 if (ConstantSDNode *Op010C =
5127 dyn_cast(Op0.getOperand(1).getOperand(0)))
5128 if (Op010C->getZExtValue() == 1) {
5129 LHS = Op0.getOperand(0);
5130 RHS = Op0.getOperand(1).getOperand(1);
5131 }
5132 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5133 if (ConstantSDNode *Op000C =
5134 dyn_cast(Op0.getOperand(0).getOperand(0)))
5135 if (Op000C->getZExtValue() == 1) {
5136 LHS = Op0.getOperand(1);
5137 RHS = Op0.getOperand(0).getOperand(1);
5138 }
5139 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5140 ConstantSDNode *AndRHS = cast(Op0.getOperand(1));
5141 SDValue AndLHS = Op0.getOperand(0);
5142 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5143 LHS = AndLHS.getOperand(0);
5144 RHS = AndLHS.getOperand(1);
5145 }
5146 }
5147
5148 if (LHS.getNode()) {
51325149 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
51335150 // instruction. Since the shift amount is in-range-or-undefined, we know
51345151 // that doing a bittest on the i16 value is ok. We extend to i32 because
51405157 // BT ignores high bits (like shifts) we can use anyextend.
51415158 if (LHS.getValueType() != RHS.getValueType())
51425159 RHS = DAG.getNode(ISD::ANY_EXTEND, LHS.getValueType(), RHS);
5143
5160
51445161 SDValue BT = DAG.getNode(X86ISD::BT, MVT::i32, LHS, RHS);
51455162 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5146 return DAG.getNode(X86ISD::SETCC, MVT::i8,
5163 return DAG.getNode(X86ISD::SETCC, MVT::i8,
51475164 DAG.getConstant(Cond, MVT::i8), BT);
51485165 }
51495166 }
52945311 !isScalarFPTypeInSSEReg(VT)) // FPStack?
52955312 IllegalFPCMov = !hasFPCMov(cast(CC)->getSExtValue());
52965313
5297 if (isX86LogicalCmp(Opc) && !IllegalFPCMov) {
5314 if ((isX86LogicalCmp(Opc) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME
52985315 Cond = Cmp;
52995316 addTest = false;
53005317 }
75467563
75477564 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
75487565 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
7566 TargetLowering::DAGCombinerInfo &DCI,
75497567 const X86Subtarget *Subtarget,
75507568 const TargetLowering &TLI) {
75517569 unsigned NumOps = N->getNumOperands();
75867604 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
75877605 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
75887606 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
7589 DAG.ReplaceAllUsesOfValueWith(SDValue(Base, 1), ResNode.getValue(1));
7607 TargetLowering::TargetLoweringOpt TLO(DAG);
7608 TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
7609 DCI.CommitTargetLoweringOpt(TLO);
75907610 return ResNode;
75917611 }
75927612
78747894 return SDValue();
78757895 }
78767896
7897 static SDValue PerformBTCombine(SDNode *N,
7898 SelectionDAG &DAG,
7899 TargetLowering::DAGCombinerInfo &DCI) {
7900 // BT ignores high bits in the bit index operand.
7901 SDValue Op1 = N->getOperand(1);
7902 if (Op1.hasOneUse()) {
7903 unsigned BitWidth = Op1.getValueSizeInBits();
7904 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
7905 APInt KnownZero, KnownOne;
7906 TargetLowering::TargetLoweringOpt TLO(DAG);
7907 TargetLowering &TLI = DAG.getTargetLoweringInfo();
7908 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
7909 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
7910 DCI.CommitTargetLoweringOpt(TLO);
7911 }
7912 return SDValue();
7913 }
78777914
78787915 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
78797916 DAGCombinerInfo &DCI) const {
78827919 default: break;
78837920 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
78847921 case ISD::BUILD_VECTOR:
7885 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
7922 return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this);
78867923 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
78877924 case ISD::SHL:
78887925 case ISD::SRA:
78917928 case X86ISD::FXOR:
78927929 case X86ISD::FOR: return PerformFORCombine(N, DAG);
78937930 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
7931 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
78947932 }
78957933
78967934 return SDValue();
None ; RUN: llvm-as < %s | llc | grep btl
0 ; RUN: llvm-as < %s | llc -march=x86 | grep btl | count 28
11 ; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | not grep esp
22 ; RUN: llvm-as < %s | llc -mcpu=penryn | grep btl | not grep esp
33 ; PR3253
66 ; pentium4, however it is currently disabled due to the register+memory
77 ; form having different semantics than the register+register form.
88
9 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
10 target triple = "i386-apple-darwin8"
9 ; Test these patterns:
10 ; (X & (1 << N)) != 0 --> BT(X, N).
11 ; ((X >>u N) & 1) != 0 --> BT(X, N).
12 ; as well as several variations:
13 ; - The second form can use an arithmetic shift.
14 ; - Either form can use == instead of !=.
15 ; - Either form can compare with an operand of the &
16 ; instead of with 0.
17 ; - The comparison can be commuted (only cases where neither
18 ; operand is constant are included).
19 ; - The and can be commuted.
1120
1221 define void @test2(i32 %x, i32 %n) nounwind {
1322 entry:
2433 ret void
2534 }
2635
36 define void @test2b(i32 %x, i32 %n) nounwind {
37 entry:
38 %tmp29 = lshr i32 %x, %n ; [#uses=1]
39 %tmp3 = and i32 1, %tmp29
40 %tmp4 = icmp eq i32 %tmp3, 0 ; [#uses=1]
41 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
42
43 bb: ; preds = %entry
44 call void @foo()
45 ret void
46
47 UnifiedReturnBlock: ; preds = %entry
48 ret void
49 }
50
51 define void @atest2(i32 %x, i32 %n) nounwind {
52 entry:
53 %tmp29 = ashr i32 %x, %n ; [#uses=1]
54 %tmp3 = and i32 %tmp29, 1 ; [#uses=1]
55 %tmp4 = icmp eq i32 %tmp3, 0 ; [#uses=1]
56 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
57
58 bb: ; preds = %entry
59 call void @foo()
60 ret void
61
62 UnifiedReturnBlock: ; preds = %entry
63 ret void
64 }
65
66 define void @atest2b(i32 %x, i32 %n) nounwind {
67 entry:
68 %tmp29 = ashr i32 %x, %n ; [#uses=1]
69 %tmp3 = and i32 1, %tmp29
70 %tmp4 = icmp eq i32 %tmp3, 0 ; [#uses=1]
71 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
72
73 bb: ; preds = %entry
74 call void @foo()
75 ret void
76
77 UnifiedReturnBlock: ; preds = %entry
78 ret void
79 }
80
81 define void @test3(i32 %x, i32 %n) nounwind {
82 entry:
83 %tmp29 = shl i32 1, %n ; [#uses=1]
84 %tmp3 = and i32 %tmp29, %x ; [#uses=1]
85 %tmp4 = icmp eq i32 %tmp3, 0 ; [#uses=1]
86 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
87
88 bb: ; preds = %entry
89 call void @foo()
90 ret void
91
92 UnifiedReturnBlock: ; preds = %entry
93 ret void
94 }
95
96 define void @test3b(i32 %x, i32 %n) nounwind {
97 entry:
98 %tmp29 = shl i32 1, %n ; [#uses=1]
99 %tmp3 = and i32 %x, %tmp29
100 %tmp4 = icmp eq i32 %tmp3, 0 ; [#uses=1]
101 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
102
103 bb: ; preds = %entry
104 call void @foo()
105 ret void
106
107 UnifiedReturnBlock: ; preds = %entry
108 ret void
109 }
110
111 define void @testne2(i32 %x, i32 %n) nounwind {
112 entry:
113 %tmp29 = lshr i32 %x, %n ; [#uses=1]
114 %tmp3 = and i32 %tmp29, 1 ; [#uses=1]
115 %tmp4 = icmp ne i32 %tmp3, 0 ; [#uses=1]
116 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
117
118 bb: ; preds = %entry
119 call void @foo()
120 ret void
121
122 UnifiedReturnBlock: ; preds = %entry
123 ret void
124 }
125
126 define void @testne2b(i32 %x, i32 %n) nounwind {
127 entry:
128 %tmp29 = lshr i32 %x, %n ; [#uses=1]
129 %tmp3 = and i32 1, %tmp29
130 %tmp4 = icmp ne i32 %tmp3, 0 ; [#uses=1]
131 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
132
133 bb: ; preds = %entry
134 call void @foo()
135 ret void
136
137 UnifiedReturnBlock: ; preds = %entry
138 ret void
139 }
140
141 define void @atestne2(i32 %x, i32 %n) nounwind {
142 entry:
143 %tmp29 = ashr i32 %x, %n ; [#uses=1]
144 %tmp3 = and i32 %tmp29, 1 ; [#uses=1]
145 %tmp4 = icmp ne i32 %tmp3, 0 ; [#uses=1]
146 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
147
148 bb: ; preds = %entry
149 call void @foo()
150 ret void
151
152 UnifiedReturnBlock: ; preds = %entry
153 ret void
154 }
155
156 define void @atestne2b(i32 %x, i32 %n) nounwind {
157 entry:
158 %tmp29 = ashr i32 %x, %n ; [#uses=1]
159 %tmp3 = and i32 1, %tmp29
160 %tmp4 = icmp ne i32 %tmp3, 0 ; [#uses=1]
161 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
162
163 bb: ; preds = %entry
164 call void @foo()
165 ret void
166
167 UnifiedReturnBlock: ; preds = %entry
168 ret void
169 }
170
171 define void @testne3(i32 %x, i32 %n) nounwind {
172 entry:
173 %tmp29 = shl i32 1, %n ; [#uses=1]
174 %tmp3 = and i32 %tmp29, %x ; [#uses=1]
175 %tmp4 = icmp ne i32 %tmp3, 0 ; [#uses=1]
176 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
177
178 bb: ; preds = %entry
179 call void @foo()
180 ret void
181
182 UnifiedReturnBlock: ; preds = %entry
183 ret void
184 }
185
186 define void @testne3b(i32 %x, i32 %n) nounwind {
187 entry:
188 %tmp29 = shl i32 1, %n ; [#uses=1]
189 %tmp3 = and i32 %x, %tmp29
190 %tmp4 = icmp ne i32 %tmp3, 0 ; [#uses=1]
191 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
192
193 bb: ; preds = %entry
194 call void @foo()
195 ret void
196
197 UnifiedReturnBlock: ; preds = %entry
198 ret void
199 }
200
201 define void @query2(i32 %x, i32 %n) nounwind {
202 entry:
203 %tmp29 = lshr i32 %x, %n ; [#uses=1]
204 %tmp3 = and i32 %tmp29, 1 ; [#uses=1]
205 %tmp4 = icmp eq i32 %tmp3, 1 ; [#uses=1]
206 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
207
208 bb: ; preds = %entry
209 call void @foo()
210 ret void
211
212 UnifiedReturnBlock: ; preds = %entry
213 ret void
214 }
215
216 define void @query2b(i32 %x, i32 %n) nounwind {
217 entry:
218 %tmp29 = lshr i32 %x, %n ; [#uses=1]
219 %tmp3 = and i32 1, %tmp29
220 %tmp4 = icmp eq i32 %tmp3, 1 ; [#uses=1]
221 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
222
223 bb: ; preds = %entry
224 call void @foo()
225 ret void
226
227 UnifiedReturnBlock: ; preds = %entry
228 ret void
229 }
230
231 define void @aquery2(i32 %x, i32 %n) nounwind {
232 entry:
233 %tmp29 = ashr i32 %x, %n ; [#uses=1]
234 %tmp3 = and i32 %tmp29, 1 ; [#uses=1]
235 %tmp4 = icmp eq i32 %tmp3, 1 ; [#uses=1]
236 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
237
238 bb: ; preds = %entry
239 call void @foo()
240 ret void
241
242 UnifiedReturnBlock: ; preds = %entry
243 ret void
244 }
245
246 define void @aquery2b(i32 %x, i32 %n) nounwind {
247 entry:
248 %tmp29 = ashr i32 %x, %n ; [#uses=1]
249 %tmp3 = and i32 1, %tmp29
250 %tmp4 = icmp eq i32 %tmp3, 1 ; [#uses=1]
251 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
252
253 bb: ; preds = %entry
254 call void @foo()
255 ret void
256
257 UnifiedReturnBlock: ; preds = %entry
258 ret void
259 }
260
261 define void @query3(i32 %x, i32 %n) nounwind {
262 entry:
263 %tmp29 = shl i32 1, %n ; [#uses=1]
264 %tmp3 = and i32 %tmp29, %x ; [#uses=1]
265 %tmp4 = icmp eq i32 %tmp3, %tmp29 ; [#uses=1]
266 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
267
268 bb: ; preds = %entry
269 call void @foo()
270 ret void
271
272 UnifiedReturnBlock: ; preds = %entry
273 ret void
274 }
275
276 define void @query3b(i32 %x, i32 %n) nounwind {
277 entry:
278 %tmp29 = shl i32 1, %n ; [#uses=1]
279 %tmp3 = and i32 %x, %tmp29
280 %tmp4 = icmp eq i32 %tmp3, %tmp29 ; [#uses=1]
281 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
282
283 bb: ; preds = %entry
284 call void @foo()
285 ret void
286
287 UnifiedReturnBlock: ; preds = %entry
288 ret void
289 }
290
291 define void @query3x(i32 %x, i32 %n) nounwind {
292 entry:
293 %tmp29 = shl i32 1, %n ; [#uses=1]
294 %tmp3 = and i32 %tmp29, %x ; [#uses=1]
295 %tmp4 = icmp eq i32 %tmp29, %tmp3 ; [#uses=1]
296 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
297
298 bb: ; preds = %entry
299 call void @foo()
300 ret void
301
302 UnifiedReturnBlock: ; preds = %entry
303 ret void
304 }
305
306 define void @query3bx(i32 %x, i32 %n) nounwind {
307 entry:
308 %tmp29 = shl i32 1, %n ; [#uses=1]
309 %tmp3 = and i32 %x, %tmp29
310 %tmp4 = icmp eq i32 %tmp29, %tmp3 ; [#uses=1]
311 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
312
313 bb: ; preds = %entry
314 call void @foo()
315 ret void
316
317 UnifiedReturnBlock: ; preds = %entry
318 ret void
319 }
320
321 define void @queryne2(i32 %x, i32 %n) nounwind {
322 entry:
323 %tmp29 = lshr i32 %x, %n ; [#uses=1]
324 %tmp3 = and i32 %tmp29, 1 ; [#uses=1]
325 %tmp4 = icmp ne i32 %tmp3, 1 ; [#uses=1]
326 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
327
328 bb: ; preds = %entry
329 call void @foo()
330 ret void
331
332 UnifiedReturnBlock: ; preds = %entry
333 ret void
334 }
335
336 define void @queryne2b(i32 %x, i32 %n) nounwind {
337 entry:
338 %tmp29 = lshr i32 %x, %n ; [#uses=1]
339 %tmp3 = and i32 1, %tmp29
340 %tmp4 = icmp ne i32 %tmp3, 1 ; [#uses=1]
341 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
342
343 bb: ; preds = %entry
344 call void @foo()
345 ret void
346
347 UnifiedReturnBlock: ; preds = %entry
348 ret void
349 }
350
351 define void @aqueryne2(i32 %x, i32 %n) nounwind {
352 entry:
353 %tmp29 = ashr i32 %x, %n ; [#uses=1]
354 %tmp3 = and i32 %tmp29, 1 ; [#uses=1]
355 %tmp4 = icmp ne i32 %tmp3, 1 ; [#uses=1]
356 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
357
358 bb: ; preds = %entry
359 call void @foo()
360 ret void
361
362 UnifiedReturnBlock: ; preds = %entry
363 ret void
364 }
365
366 define void @aqueryne2b(i32 %x, i32 %n) nounwind {
367 entry:
368 %tmp29 = ashr i32 %x, %n ; [#uses=1]
369 %tmp3 = and i32 1, %tmp29
370 %tmp4 = icmp ne i32 %tmp3, 1 ; [#uses=1]
371 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
372
373 bb: ; preds = %entry
374 call void @foo()
375 ret void
376
377 UnifiedReturnBlock: ; preds = %entry
378 ret void
379 }
380
381 define void @queryne3(i32 %x, i32 %n) nounwind {
382 entry:
383 %tmp29 = shl i32 1, %n ; [#uses=1]
384 %tmp3 = and i32 %tmp29, %x ; [#uses=1]
385 %tmp4 = icmp ne i32 %tmp3, %tmp29 ; [#uses=1]
386 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
387
388 bb: ; preds = %entry
389 call void @foo()
390 ret void
391
392 UnifiedReturnBlock: ; preds = %entry
393 ret void
394 }
395
396 define void @queryne3b(i32 %x, i32 %n) nounwind {
397 entry:
398 %tmp29 = shl i32 1, %n ; [#uses=1]
399 %tmp3 = and i32 %x, %tmp29
400 %tmp4 = icmp ne i32 %tmp3, %tmp29 ; [#uses=1]
401 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
402
403 bb: ; preds = %entry
404 call void @foo()
405 ret void
406
407 UnifiedReturnBlock: ; preds = %entry
408 ret void
409 }
410
411 define void @queryne3x(i32 %x, i32 %n) nounwind {
412 entry:
413 %tmp29 = shl i32 1, %n ; [#uses=1]
414 %tmp3 = and i32 %tmp29, %x ; [#uses=1]
415 %tmp4 = icmp ne i32 %tmp29, %tmp3 ; [#uses=1]
416 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
417
418 bb: ; preds = %entry
419 call void @foo()
420 ret void
421
422 UnifiedReturnBlock: ; preds = %entry
423 ret void
424 }
425
426 define void @queryne3bx(i32 %x, i32 %n) nounwind {
427 entry:
428 %tmp29 = shl i32 1, %n ; [#uses=1]
429 %tmp3 = and i32 %x, %tmp29
430 %tmp4 = icmp ne i32 %tmp29, %tmp3 ; [#uses=1]
431 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
432
433 bb: ; preds = %entry
434 call void @foo()
435 ret void
436
437 UnifiedReturnBlock: ; preds = %entry
438 ret void
439 }
440
27441 declare void @foo()
None ; RUN: llvm-as < %s | llc -march=x86 | grep {cmove 16(%esp)}
0 ; RUN: llvm-as < %s | llc -march=x86 > %t
1 ; RUN: grep btl %t | count 2
2 ; RUN: grep cmov %t | count 2
3 ; RUN: not grep test %t
4 ; RUN: not grep set %t
5 ; RUN: not grep j %t
6 ; RUN: not grep cmovne %t
7 ; RUN: not grep cmove %t
18
9 define i32 @foo(i32 %x, i32 %n, i32 %w, i32 %v) nounwind readnone {
10 entry:
11 %0 = lshr i32 %x, %n ; [#uses=1]
12 %1 = and i32 %0, 1 ; [#uses=1]
13 %toBool = icmp eq i32 %1, 0 ; [#uses=1]
14 %.0 = select i1 %toBool, i32 %v, i32 12 ; [#uses=1]
15 ret i32 %.0
16 }
217 define i32 @bar(i32 %x, i32 %n, i32 %w, i32 %v) nounwind readnone {
318 entry:
419 %0 = lshr i32 %x, %n ; [#uses=1]