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[X86][AVX512] Regenerate shift tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308168 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 3 years ago
1 changed file(s) with 95 addition(s) and 53 deletion(s). Raw diff Collapse all Expand all
None ;RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
1 ;RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck --check-prefix=SKX %s
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=KNL
2 ;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=CHECK --check-prefix=SKX
23
3 ;CHECK-LABEL: shift_16_i32
4 ;CHECK: vpsrld
5 ;CHECK: vpslld
6 ;CHECK: vpsrad
7 ;CHECK: ret
84 define <16 x i32> @shift_16_i32(<16 x i32> %a) {
5 ; CHECK-LABEL: shift_16_i32:
6 ; CHECK: # BB#0:
7 ; CHECK-NEXT: vpsrld $1, %zmm0, %zmm0
8 ; CHECK-NEXT: vpslld $12, %zmm0, %zmm0
9 ; CHECK-NEXT: vpsrad $12, %zmm0, %zmm0
10 ; CHECK-NEXT: retq
911 %b = lshr <16 x i32> %a,
1012 %c = shl <16 x i32> %b,
1113 %d = ashr <16 x i32> %c,
1214 ret <16 x i32> %d;
1315 }
1416
15 ;CHECK-LABEL: shift_8_i64
16 ;CHECK: vpsrlq
17 ;CHECK: vpsllq
18 ;CHECK: vpsraq
19 ;CHECK: ret
2017 define <8 x i64> @shift_8_i64(<8 x i64> %a) {
18 ; CHECK-LABEL: shift_8_i64:
19 ; CHECK: # BB#0:
20 ; CHECK-NEXT: vpsrlq $1, %zmm0, %zmm0
21 ; CHECK-NEXT: vpsllq $12, %zmm0, %zmm0
22 ; CHECK-NEXT: vpsraq $12, %zmm0, %zmm0
23 ; CHECK-NEXT: retq
2124 %b = lshr <8 x i64> %a,
2225 %c = shl <8 x i64> %b,
2326 %d = ashr <8 x i64> %c,
2427 ret <8 x i64> %d;
2528 }
2629
27 ;SKX-LABEL: shift_4_i64
28 ;SKX: vpsrlq
29 ;SKX: vpsllq
30 ;SKX: vpsraq
31 ;SKX: ret
3230 define <4 x i64> @shift_4_i64(<4 x i64> %a) {
31 ; KNL-LABEL: shift_4_i64:
32 ; KNL: # BB#0:
33 ; KNL-NEXT: vpsrlq $1, %ymm0, %ymm0
34 ; KNL-NEXT: vpsllq $12, %ymm0, %ymm0
35 ; KNL-NEXT: vpsraq $12, %zmm0, %zmm0
36 ; KNL-NEXT: # kill: %YMM0 %YMM0 %ZMM0
37 ; KNL-NEXT: retq
38 ;
39 ; SKX-LABEL: shift_4_i64:
40 ; SKX: # BB#0:
41 ; SKX-NEXT: vpsrlq $1, %ymm0, %ymm0
42 ; SKX-NEXT: vpsllq $12, %ymm0, %ymm0
43 ; SKX-NEXT: vpsraq $12, %ymm0, %ymm0
44 ; SKX-NEXT: retq
3345 %b = lshr <4 x i64> %a,
3446 %c = shl <4 x i64> %b,
3547 %d = ashr <4 x i64> %c,
3648 ret <4 x i64> %d;
3749 }
3850
39 ; CHECK-LABEL: variable_shl4
40 ; CHECK: vpsllvq %zmm
41 ; CHECK: ret
4251 define <8 x i64> @variable_shl4(<8 x i64> %x, <8 x i64> %y) {
52 ; CHECK-LABEL: variable_shl4:
53 ; CHECK: # BB#0:
54 ; CHECK-NEXT: vpsllvq %zmm1, %zmm0, %zmm0
55 ; CHECK-NEXT: retq
4356 %k = shl <8 x i64> %x, %y
4457 ret <8 x i64> %k
4558 }
4659
47 ; CHECK-LABEL: variable_shl5
48 ; CHECK: vpsllvd %zmm
49 ; CHECK: ret
5060 define <16 x i32> @variable_shl5(<16 x i32> %x, <16 x i32> %y) {
61 ; CHECK-LABEL: variable_shl5:
62 ; CHECK: # BB#0:
63 ; CHECK-NEXT: vpsllvd %zmm1, %zmm0, %zmm0
64 ; CHECK-NEXT: retq
5165 %k = shl <16 x i32> %x, %y
5266 ret <16 x i32> %k
5367 }
5468
55 ; CHECK-LABEL: variable_srl0
56 ; CHECK: vpsrlvd
57 ; CHECK: ret
5869 define <16 x i32> @variable_srl0(<16 x i32> %x, <16 x i32> %y) {
70 ; CHECK-LABEL: variable_srl0:
71 ; CHECK: # BB#0:
72 ; CHECK-NEXT: vpsrlvd %zmm1, %zmm0, %zmm0
73 ; CHECK-NEXT: retq
5974 %k = lshr <16 x i32> %x, %y
6075 ret <16 x i32> %k
6176 }
6277
63 ; CHECK-LABEL: variable_srl2
64 ; CHECK: psrlvq
65 ; CHECK: ret
6678 define <8 x i64> @variable_srl2(<8 x i64> %x, <8 x i64> %y) {
79 ; CHECK-LABEL: variable_srl2:
80 ; CHECK: # BB#0:
81 ; CHECK-NEXT: vpsrlvq %zmm1, %zmm0, %zmm0
82 ; CHECK-NEXT: retq
6783 %k = lshr <8 x i64> %x, %y
6884 ret <8 x i64> %k
6985 }
7086
71 ; CHECK-LABEL: variable_sra1
72 ; CHECK: vpsravd
73 ; CHECK: ret
7487 define <16 x i32> @variable_sra1(<16 x i32> %x, <16 x i32> %y) {
88 ; CHECK-LABEL: variable_sra1:
89 ; CHECK: # BB#0:
90 ; CHECK-NEXT: vpsravd %zmm1, %zmm0, %zmm0
91 ; CHECK-NEXT: retq
7592 %k = ashr <16 x i32> %x, %y
7693 ret <16 x i32> %k
7794 }
7895
79 ; CHECK-LABEL: variable_sra2
80 ; CHECK: vpsravq %zmm
81 ; CHECK: ret
8296 define <8 x i64> @variable_sra2(<8 x i64> %x, <8 x i64> %y) {
97 ; CHECK-LABEL: variable_sra2:
98 ; CHECK: # BB#0:
99 ; CHECK-NEXT: vpsravq %zmm1, %zmm0, %zmm0
100 ; CHECK-NEXT: retq
83101 %k = ashr <8 x i64> %x, %y
84102 ret <8 x i64> %k
85103 }
86104
87 ; SKX-LABEL: variable_sra3
88 ; SKX: vpsravq %ymm
89 ; SKX: ret
90105 define <4 x i64> @variable_sra3(<4 x i64> %x, <4 x i64> %y) {
106 ; KNL-LABEL: variable_sra3:
107 ; KNL: # BB#0:
108 ; KNL-NEXT: # kill: %YMM1 %YMM1 %ZMM1
109 ; KNL-NEXT: # kill: %YMM0 %YMM0 %ZMM0
110 ; KNL-NEXT: vpsravq %zmm1, %zmm0, %zmm0
111 ; KNL-NEXT: # kill: %YMM0 %YMM0 %ZMM0
112 ; KNL-NEXT: retq
113 ;
114 ; SKX-LABEL: variable_sra3:
115 ; SKX: # BB#0:
116 ; SKX-NEXT: vpsravq %ymm1, %ymm0, %ymm0
117 ; SKX-NEXT: retq
91118 %k = ashr <4 x i64> %x, %y
92119 ret <4 x i64> %k
93120 }
94121
95 ; SKX-LABEL: variable_sra4
96 ; SKX: vpsravw %xmm
97 ; SKX: ret
98122 define <8 x i16> @variable_sra4(<8 x i16> %x, <8 x i16> %y) {
123 ; KNL-LABEL: variable_sra4:
124 ; KNL: # BB#0:
125 ; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
126 ; KNL-NEXT: vpmovsxwd %xmm0, %ymm0
127 ; KNL-NEXT: vpsravd %ymm1, %ymm0, %ymm0
128 ; KNL-NEXT: vpmovdw %zmm0, %ymm0
129 ; KNL-NEXT: # kill: %XMM0 %XMM0 %YMM0
130 ; KNL-NEXT: retq
131 ;
132 ; SKX-LABEL: variable_sra4:
133 ; SKX: # BB#0:
134 ; SKX-NEXT: vpsravw %xmm1, %xmm0, %xmm0
135 ; SKX-NEXT: retq
99136 %k = ashr <8 x i16> %x, %y
100137 ret <8 x i16> %k
101138 }
102139
103 ; CHECK-LABEL: variable_sra01_load
104 ; CHECK: vpsravd (%
105 ; CHECK: ret
106140 define <16 x i32> @variable_sra01_load(<16 x i32> %x, <16 x i32>* %y) {
141 ; CHECK-LABEL: variable_sra01_load:
142 ; CHECK: # BB#0:
143 ; CHECK-NEXT: vpsravd (%rdi), %zmm0, %zmm0
144 ; CHECK-NEXT: retq
107145 %y1 = load <16 x i32>, <16 x i32>* %y
108146 %k = ashr <16 x i32> %x, %y1
109147 ret <16 x i32> %k
110148 }
111149
112 ; CHECK-LABEL: variable_shl1_load
113 ; CHECK: vpsllvd (%
114 ; CHECK: ret
115150 define <16 x i32> @variable_shl1_load(<16 x i32> %x, <16 x i32>* %y) {
151 ; CHECK-LABEL: variable_shl1_load:
152 ; CHECK: # BB#0:
153 ; CHECK-NEXT: vpsllvd (%rdi), %zmm0, %zmm0
154 ; CHECK-NEXT: retq
116155 %y1 = load <16 x i32>, <16 x i32>* %y
117156 %k = shl <16 x i32> %x, %y1
118157 ret <16 x i32> %k
119158 }
120 ; CHECK: variable_srl0_load
121 ; CHECK: vpsrlvd (%
122 ; CHECK: ret
159
123160 define <16 x i32> @variable_srl0_load(<16 x i32> %x, <16 x i32>* %y) {
161 ; CHECK-LABEL: variable_srl0_load:
162 ; CHECK: # BB#0:
163 ; CHECK-NEXT: vpsrlvd (%rdi), %zmm0, %zmm0
164 ; CHECK-NEXT: retq
124165 %y1 = load <16 x i32>, <16 x i32>* %y
125166 %k = lshr <16 x i32> %x, %y1
126167 ret <16 x i32> %k
127168 }
128169
129 ; CHECK: variable_srl3_load
130 ; CHECK: vpsrlvq (%
131 ; CHECK: ret
132170 define <8 x i64> @variable_srl3_load(<8 x i64> %x, <8 x i64>* %y) {
171 ; CHECK-LABEL: variable_srl3_load:
172 ; CHECK: # BB#0:
173 ; CHECK-NEXT: vpsrlvq (%rdi), %zmm0, %zmm0
174 ; CHECK-NEXT: retq
133175 %y1 = load <8 x i64>, <8 x i64>* %y
134176 %k = lshr <8 x i64> %x, %y1
135177 ret <8 x i64> %k