llvm.org GIT mirror llvm / e566cd0
Remove some more patterns by custom lowering intrinsics to target specific nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149052 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 7 years ago
2 changed file(s) with 14 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
93579357 case Intrinsic::x86_avx2_psign_d:
93589358 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
93599359 Op.getOperand(1), Op.getOperand(2));
9360 case Intrinsic::x86_sse41_insertps:
9361 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9362 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9363 case Intrinsic::x86_avx_vperm2f128_ps_256:
9364 case Intrinsic::x86_avx_vperm2f128_pd_256:
9365 case Intrinsic::x86_avx_vperm2f128_si_256:
9366 case Intrinsic::x86_avx2_vperm2i128:
9367 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9368 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
93609369
93619370 // ptest and testp intrinsics. The intrinsic these come from are designed to
93629371 // return an integer value, not just an instruction so lower it to the ptest
58585858 let Constraints = "$src1 = $dst" in
58595859 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
58605860 }
5861
5862 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5863 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5864 Requires<[HasAVX]>;
5865 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5866 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5867 Requires<[HasSSE41]>;
58685861
58695862 //===----------------------------------------------------------------------===//
58705863 // SSE4.1 - Round Instructions
71787171 }
71797172
71807173 let Predicates = [HasAVX] in {
7181 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
7182 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7183 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
7184 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
71857174 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
71867175 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7187
7188 def : Pat<(int_x86_avx_vperm2f128_ps_256
7189 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
7190 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7191 def : Pat<(int_x86_avx_vperm2f128_pd_256
7192 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
7193 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
71947176 def : Pat<(int_x86_avx_vperm2f128_si_256
71957177 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)), imm:$src3),
71967178 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
73977379 //===----------------------------------------------------------------------===//
73987380 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
73997381 //
7382 let neverHasSideEffects = 1 in {
74007383 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
74017384 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
74027385 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7403 [(set VR256:$dst,
7404 (int_x86_avx2_vperm2i128 VR256:$src1, VR256:$src2, imm:$src3))]>,
7405 VEX_4V;
7386 []>, VEX_4V;
7387 let mayLoad = 1 in
74067388 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
74077389 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
74087390 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7409 [(set VR256:$dst,
7410 (int_x86_avx2_vperm2i128 VR256:$src1, (memopv4i64 addr:$src2),
7411 imm:$src3))]>,
7412 VEX_4V;
7391 []>, VEX_4V;
7392 }
74137393
74147394 let Predicates = [HasAVX2] in {
74157395 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),