llvm.org GIT mirror llvm / e53f4a0
Move some methods out of MachineInstr into MachineOperand git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 13 years ago
15 changed file(s) with 56 addition(s) and 70 deletion(s). Raw diff Collapse all Expand all
233233 extra.regNum = Reg;
234234 }
235235
236 void setImmedValue(int immVal) {
236 void setImmedValue(int64_t immVal) {
237237 assert(isImmediate() && "Wrong MachineOperand mutator");
238238 contents.immedVal = immVal;
239239 }
243243 isJumpTableIndex()) &&
244244 "Wrong MachineOperand accessor");
245245 extra.offset = Offset;
246 }
247
248 /// ChangeToImmediate - Replace this operand with a new immediate operand of
249 /// the specified value. If an operand is known to be an immediate already,
250 /// the setImmedValue method should be used.
251 void ChangeToImmediate(int64_t ImmVal) {
252 opType = MO_Immediate;
253 contents.immedVal = ImmVal;
254 }
255
256 /// ChangeToRegister - Replace this operand with a new register operand of
257 /// the specified value. If an operand is known to be an register already,
258 /// the setReg method should be used.
259 void ChangeToRegister(unsigned Reg) {
260 opType = MO_VirtualRegister;
261 extra.regNum = Reg;
246262 }
247263
248264 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
435451 //===--------------------------------------------------------------------===//
436452 // Accessors used to modify instructions in place.
437453 //
438 // FIXME: Move this stuff to MachineOperand itself!
439454
440455 /// setOpcode - Replace the opcode of the current instruction with a new one.
441456 ///
447462 void RemoveOperand(unsigned i) {
448463 operands.erase(operands.begin()+i);
449464 }
450
451 // Access to set the operands when building the machine instruction
452 //
453 void SetMachineOperandConst(unsigned i,
454 MachineOperand::MachineOperandType operandType,
455 int intValue);
456
457 void SetMachineOperandReg(unsigned i, int regNum);
458465 };
459466
460467 //===----------------------------------------------------------------------===//
186186 MRegisterInfo::isVirtualRegister(mop.getReg())) {
187187 // replace register with representative register
188188 unsigned reg = rep(mop.getReg());
189 mii->SetMachineOperandReg(i, reg);
189 mii->getOperand(i).setReg(reg);
190190
191191 LiveInterval &RegInt = getInterval(reg);
192192 RegInt.weight +=
262262 if (NewRegLiveIn && mop.isUse()) {
263263 // We already emitted a reload of this value, reuse it for
264264 // subsequent operands.
265 MI->SetMachineOperandReg(i, NewRegLiveIn);
265 MI->getOperand(i).setReg(NewRegLiveIn);
266266 DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
267267 << " for operand #" << i << '\n');
268268 } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
299299
300300 // create a new register for this spill
301301 NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
302 MI->SetMachineOperandReg(i, NewRegLiveIn);
302 MI->getOperand(i).setReg(NewRegLiveIn);
303303 vrm.grow();
304304 vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
305305 LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
104104 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
105105 return true; // Broken: we have all the operands of this instruction!
106106 return false;
107 }
108
109 void
110 MachineInstr::SetMachineOperandConst(unsigned i,
111 MachineOperand::MachineOperandType opTy,
112 int intValue) {
113 assert(i < getNumOperands());
114 operands[i].opType = opTy;
115 operands[i].contents.immedVal = intValue;
116 operands[i].extra.regNum = -1;
117 operands[i].flags = 0;
118 }
119
120 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
121 assert(i < getNumOperands());
122
123 operands[i].opType = MachineOperand::MO_VirtualRegister;
124 operands[i].contents.GV = NULL;
125 operands[i].extra.regNum = regNum;
126107 }
127108
128109 void MachineInstr::dump() const {
442442 // and return.
443443 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
444444 MarkPhysRegRecentlyUsed(PR); // Already have this value available!
445 MI->SetMachineOperandReg(OpNum, PR); // Assign the input register
445 MI->getOperand(OpNum).setReg(PR); // Assign the input register
446446 return MI;
447447 }
448448
480480 ++NumLoads; // Update statistics
481481
482482 PhysRegsEverUsed[PhysReg] = true;
483 MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register
483 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
484484 return MI;
485485 }
486486
598598 DestPhysReg = getReg(MBB, MI, DestVirtReg);
599599 PhysRegsEverUsed[DestPhysReg] = true;
600600 markVirtRegModified(DestVirtReg);
601 MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register
601 MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
602602 }
603603 }
604604
210210 Virt2PhysRegMap[virtualReg] = physReg;
211211 }
212212 }
213 MI->SetMachineOperandReg(i, physReg);
213 MI->getOperand(i).setReg(physReg);
214214 DEBUG(std::cerr << "virt: " << virtualReg <<
215215 ", phys: " << op.getReg() << "\n");
216216 }
199199 for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
200200 if (mi->getOperand(i).isRegister() &&
201201 mi->getOperand(i).getReg() == regB)
202 mi->SetMachineOperandReg(i, regA);
202 mi->getOperand(i).setReg(regA);
203203 }
204204 }
205205
181181 }
182182 }
183183 PhysRegsUsed[PhysReg] = true;
184 MI.SetMachineOperandReg(i, PhysReg);
184 MI.getOperand(i).setReg(PhysReg);
185185 } else {
186186 PhysRegsUsed[MO.getReg()] = true;
187187 }
457457 // Any stores to this stack slot are not dead anymore.
458458 MaybeDeadStores.erase(NewOp.StackSlot);
459459
460 MI->SetMachineOperandReg(NewOp.Operand, NewPhysReg);
460 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
461461
462462 Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
463463 ++NumLoads;
535535 // This virtual register was assigned a physreg!
536536 unsigned Phys = VRM.getPhys(VirtReg);
537537 PhysRegsUsed[Phys] = true;
538 MI.SetMachineOperandReg(i, Phys);
538 MI.getOperand(i).setReg(Phys);
539539 continue;
540540 }
541541
566566 << MRI->getName(PhysReg) << " for vreg"
567567 << VirtReg <<" instead of reloading into physreg "
568568 << MRI->getName(VRM.getPhys(VirtReg)) << "\n");
569 MI.SetMachineOperandReg(i, PhysReg);
569 MI.getOperand(i).setReg(PhysReg);
570570
571571 // The only technical detail we have is that we don't know that
572572 // PhysReg won't be clobbered by a reloaded stack slot that occurs
617617 << MRI->getName(PhysReg) << " for vreg"
618618 << VirtReg
619619 << " instead of reloading into same physreg.\n");
620 MI.SetMachineOperandReg(i, PhysReg);
620 MI.getOperand(i).setReg(PhysReg);
621621 ++NumReused;
622622 continue;
623623 }
632632 Spills.ClobberPhysReg(DesignatedReg);
633633
634634 Spills.addAvailable(StackSlot, DesignatedReg);
635 MI.SetMachineOperandReg(i, DesignatedReg);
635 MI.getOperand(i).setReg(DesignatedReg);
636636 DEBUG(std::cerr << '\t' << *prior(MII));
637637 ++NumReused;
638638 continue;
661661 MaybeDeadStores.erase(StackSlot);
662662 Spills.addAvailable(StackSlot, PhysReg);
663663 ++NumLoads;
664 MI.SetMachineOperandReg(i, PhysReg);
664 MI.getOperand(i).setReg(PhysReg);
665665 DEBUG(std::cerr << '\t' << *prior(MII));
666666 }
667667
816816 PhysRegsUsed[PhysReg] = true;
817817 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
818818 DEBUG(std::cerr << "Store:\t" << *next(MII));
819 MI.SetMachineOperandReg(i, PhysReg);
819 MI.getOperand(i).setReg(PhysReg);
820820
821821 // Check to see if this is a noop copy. If so, eliminate the
822822 // instruction before considering the dest reg to be changed.
215215 int FrameIndex = MI.getOperand(i).getFrameIndex();
216216
217217 // Add the base register of R30 (SP) or R15 (FP).
218 MI.SetMachineOperandReg(i + 1, FP ? Alpha::R15 : Alpha::R30);
218 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30);
219219
220220 // Now add the frame object offset to the offset from the virtual frame index.
221221 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
232232 //so in this case, we need to use a temporary register, and move the original
233233 //inst off the SP/FP
234234 //fix up the old:
235 MI.SetMachineOperandReg(i + 1, Alpha::R28);
236 MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate,
237 getLower16(Offset));
235 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28);
236 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
238237 //insert the new
239238 MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
240239 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
241240 MBB.insert(II, nMI);
242241 } else {
243 MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset);
242 MI.getOperand(i).ChangeToImmediate(Offset);
244243 }
245244 }
246245
154154 // choose a base register: ( hasFP? framepointer : stack pointer )
155155 unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
156156 // Add the base register
157 MI.SetMachineOperandReg(i, BaseRegister);
157 MI.getOperand(i).ChangeToRegister(BaseRegister);
158158
159159 // Now add the frame object offset to the offset from r1.
160160 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
167167 // XXX: we use 'r22' as another hack+slash temporary register here :(
168168 if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
169169 //fix up the old:
170 MI.SetMachineOperandReg(i, IA64::r22);
170 MI.getOperand(i).ChangeToRegister(IA64::r22);
171171 MI.getOperand(i).setUse(); // mark r22 as being used
172172 // (the bundler wants to know this)
173173 //insert the new
176176 MBB.insert(II, nMI);
177177 } else { // it's big
178178 //fix up the old:
179 MI.SetMachineOperandReg(i, IA64::r22);
179 MI.getOperand(i).ChangeToRegister(IA64::r22);
180180 MI.getOperand(i).setUse(); // mark r22 as being used
181181 // (the bundler wants to know this)
182182 MachineInstr* nMI;
135135 // Swap op1/op2
136136 unsigned Reg1 = MI->getOperand(1).getReg();
137137 unsigned Reg2 = MI->getOperand(2).getReg();
138 MI->SetMachineOperandReg(2, Reg1);
139 MI->SetMachineOperandReg(1, Reg2);
138 MI->getOperand(2).setReg(Reg1);
139 MI->getOperand(1).setReg(Reg2);
140140
141141 // Swap the mask around.
142142 unsigned MB = MI->getOperand(4).getImmedValue();
293293 int FrameIndex = MI.getOperand(i).getFrameIndex();
294294
295295 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
296 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
296 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
297297
298298 // Take into account whether it's an add or mem instruction
299299 unsigned OffIdx = (i == 2) ? 1 : 2;
320320 "No indexed form of load or store available!");
321321 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
322322 MI.setOpcode(NewOpcode);
323 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
324 MI.SetMachineOperandReg(2, PPC::R0);
323 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
324 MI.getOperand(2).ChangeToRegister(PPC::R0);
325325 } else {
326326 switch (MI.getOpcode()) {
327327 case PPC::LWA:
332332 Offset >>= 2; // The actual encoded value has the low two bits zero.
333333 break;
334334 }
335 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_Immediate, Offset);
335 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
336336 }
337337 }
338338
103103 else
104104 assert(0 && "Unknown opcode!");
105105
106 MI->SetMachineOperandReg(0, EvenDestReg);
107 MI->SetMachineOperandReg(1, EvenSrcReg);
106 MI->getOperand(0).setReg(EvenDestReg);
107 MI->getOperand(1).setReg(EvenSrcReg);
108108 DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
109109 // Insert copy for the other half of the double.
110110 if (DestDReg != SrcDReg) {
134134 if (Offset >= -4096 && Offset <= 4095) {
135135 // If the offset is small enough to fit in the immediate field, directly
136136 // encode it.
137 MI.SetMachineOperandReg(i, SP::I6);
138 MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset);
137 MI.getOperand(i).ChangeToRegister(SP::I6);
138 MI.getOperand(i+1).ChangeToImmediate(Offset);
139139 } else {
140140 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
141141 // scavenge a register here instead of reserving G1 all of the time.
145145 BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
146146 SP::G1).addReg(SP::G1).addReg(SP::I6);
147147 // Insert: G1+%lo(offset) into the user.
148 MI.SetMachineOperandReg(i, SP::G1);
149 MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate,
150 Offset & ((1 << 10)-1));
148 MI.getOperand(i).ChangeToRegister(SP::G1);
149 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
151150 }
152151 }
153152
4545 "This only knows how to commute register operands so far");
4646 unsigned Reg1 = MI->getOperand(1).getReg();
4747 unsigned Reg2 = MI->getOperand(1).getReg();
48 MI->SetMachineOperandReg(2, Reg1);
49 MI->SetMachineOperandReg(1, Reg2);
48 MI->getOperand(2).setReg(Reg1);
49 MI->getOperand(1).setReg(Reg2);
5050 return MI;
5151 }
664664
665665 // This must be part of a four operand memory reference. Replace the
666666 // FrameIndex with base register with EBP. Add add an offset to the offset.
667 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
667 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
668668
669669 // Now add the frame object offset to the offset from EBP.
670670 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
675675 else
676676 Offset += 4; // Skip the saved EBP
677677
678 MI.SetMachineOperandConst(i+3, MachineOperand::MO_Immediate, Offset);
678 MI.getOperand(i+3).ChangeToImmediate(Offset);
679679 }
680680
681681 void