llvm.org GIT mirror llvm / e50ed30
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8 Owen Anderson 10 years ago
104 changed file(s) with 7282 addition(s) and 7282 deletion(s). Raw diff Collapse all Expand all
5353 LocInfo HTP : 6;
5454
5555 /// ValVT - The type of the value being assigned.
56 MVT ValVT;
56 EVT ValVT;
5757
5858 /// LocVT - The type of the location being assigned to.
59 MVT LocVT;
59 EVT LocVT;
6060 public:
6161
62 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
63 unsigned RegNo, MVT LocVT,
62 static CCValAssign getReg(unsigned ValNo, EVT ValVT,
63 unsigned RegNo, EVT LocVT,
6464 LocInfo HTP) {
6565 CCValAssign Ret;
6666 Ret.ValNo = ValNo;
7373 return Ret;
7474 }
7575
76 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
77 unsigned RegNo, MVT LocVT,
76 static CCValAssign getCustomReg(unsigned ValNo, EVT ValVT,
77 unsigned RegNo, EVT LocVT,
7878 LocInfo HTP) {
7979 CCValAssign Ret;
8080 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
8282 return Ret;
8383 }
8484
85 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
86 unsigned Offset, MVT LocVT,
85 static CCValAssign getMem(unsigned ValNo, EVT ValVT,
86 unsigned Offset, EVT LocVT,
8787 LocInfo HTP) {
8888 CCValAssign Ret;
8989 Ret.ValNo = ValNo;
9696 return Ret;
9797 }
9898
99 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
100 unsigned Offset, MVT LocVT,
99 static CCValAssign getCustomMem(unsigned ValNo, EVT ValVT,
100 unsigned Offset, EVT LocVT,
101101 LocInfo HTP) {
102102 CCValAssign Ret;
103103 Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
106106 }
107107
108108 unsigned getValNo() const { return ValNo; }
109 MVT getValVT() const { return ValVT; }
109 EVT getValVT() const { return ValVT; }
110110
111111 bool isRegLoc() const { return !isMem; }
112112 bool isMemLoc() const { return isMem; }
115115
116116 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
117117 unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
118 MVT getLocVT() const { return LocVT; }
118 EVT getLocVT() const { return LocVT; }
119119
120120 LocInfo getLocInfo() const { return HTP; }
121121 bool isExtInLoc() const {
126126
127127 /// CCAssignFn - This function assigns a location for Val, updating State to
128128 /// reflect the change.
129 typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
130 MVT LocVT, CCValAssign::LocInfo LocInfo,
129 typedef bool CCAssignFn(unsigned ValNo, EVT ValVT,
130 EVT LocVT, CCValAssign::LocInfo LocInfo,
131131 ISD::ArgFlagsTy ArgFlags, CCState &State);
132132
133133 /// CCCustomFn - This function assigns a location for Val, possibly updating
134134 /// all args to reflect changes and indicates if it handled it. It must set
135135 /// isCustom if it handles the arg and returns true.
136 typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
137 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
136 typedef bool CCCustomFn(unsigned &ValNo, EVT &ValVT,
137 EVT &LocVT, CCValAssign::LocInfo &LocInfo,
138138 ISD::ArgFlagsTy &ArgFlags, CCState &State);
139139
140140 /// CCState - This class holds information needed while lowering arguments and
188188
189189 /// AnalyzeCallOperands - Same as above except it takes vectors of types
190190 /// and argument flags.
191 void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
191 void AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs,
192192 SmallVectorImpl &Flags,
193193 CCAssignFn Fn);
194194
199199
200200 /// AnalyzeCallResult - Same as above except it's specialized for calls which
201201 /// produce a single value.
202 void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
202 void AnalyzeCallResult(EVT VT, CCAssignFn Fn);
203203
204204 /// getFirstUnallocated - Return the first unallocated register in the set, or
205205 /// NumRegs if they are all allocated.
268268 // HandleByVal - Allocate a stack slot large enough to pass an argument by
269269 // value. The size and alignment information of the argument is encoded in its
270270 // parameter attribute.
271 void HandleByVal(unsigned ValNo, MVT ValVT,
272 MVT LocVT, CCValAssign::LocInfo LocInfo,
271 void HandleByVal(unsigned ValNo, EVT ValVT,
272 EVT LocVT, CCValAssign::LocInfo LocInfo,
273273 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
274274
275275 private:
3434 return false;
3535 if (Chain->getNumOperands() > 0) {
3636 SDValue C0 = Chain->getOperand(0);
37 if (C0.getValueType() == MVT::Other)
37 if (C0.getValueType() == EVT::Other)
3838 return C0.getNode() != Op && IsChainCompatible(C0.getNode(), Op);
3939 }
4040 return true;
136136 /// FastEmit_r - This method is called by target-independent code
137137 /// to request that an instruction with the given type and opcode
138138 /// be emitted.
139 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
140 MVT::SimpleValueType RetVT,
139 virtual unsigned FastEmit_(EVT::SimpleValueType VT,
140 EVT::SimpleValueType RetVT,
141141 ISD::NodeType Opcode);
142142
143143 /// FastEmit_r - This method is called by target-independent code
144144 /// to request that an instruction with the given type, opcode, and
145145 /// register operand be emitted.
146146 ///
147 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
148 MVT::SimpleValueType RetVT,
147 virtual unsigned FastEmit_r(EVT::SimpleValueType VT,
148 EVT::SimpleValueType RetVT,
149149 ISD::NodeType Opcode, unsigned Op0);
150150
151151 /// FastEmit_rr - This method is called by target-independent code
152152 /// to request that an instruction with the given type, opcode, and
153153 /// register operands be emitted.
154154 ///
155 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
156 MVT::SimpleValueType RetVT,
155 virtual unsigned FastEmit_rr(EVT::SimpleValueType VT,
156 EVT::SimpleValueType RetVT,
157157 ISD::NodeType Opcode,
158158 unsigned Op0, unsigned Op1);
159159
161161 /// to request that an instruction with the given type, opcode, and
162162 /// register and immediate operands be emitted.
163163 ///
164 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
165 MVT::SimpleValueType RetVT,
164 virtual unsigned FastEmit_ri(EVT::SimpleValueType VT,
165 EVT::SimpleValueType RetVT,
166166 ISD::NodeType Opcode,
167167 unsigned Op0, uint64_t Imm);
168168
170170 /// to request that an instruction with the given type, opcode, and
171171 /// register and floating-point immediate operands be emitted.
172172 ///
173 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
174 MVT::SimpleValueType RetVT,
173 virtual unsigned FastEmit_rf(EVT::SimpleValueType VT,
174 EVT::SimpleValueType RetVT,
175175 ISD::NodeType Opcode,
176176 unsigned Op0, ConstantFP *FPImm);
177177
179179 /// to request that an instruction with the given type, opcode, and
180180 /// register and immediate operands be emitted.
181181 ///
182 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
183 MVT::SimpleValueType RetVT,
182 virtual unsigned FastEmit_rri(EVT::SimpleValueType VT,
183 EVT::SimpleValueType RetVT,
184184 ISD::NodeType Opcode,
185185 unsigned Op0, unsigned Op1, uint64_t Imm);
186186
188188 /// to emit an instruction with an immediate operand using FastEmit_ri.
189189 /// If that fails, it materializes the immediate into a register and try
190190 /// FastEmit_rr instead.
191 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
191 unsigned FastEmit_ri_(EVT::SimpleValueType VT,
192192 ISD::NodeType Opcode,
193193 unsigned Op0, uint64_t Imm,
194 MVT::SimpleValueType ImmType);
194 EVT::SimpleValueType ImmType);
195195
196196 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
197197 /// to emit an instruction with an immediate operand using FastEmit_rf.
198198 /// If that fails, it materializes the immediate into a register and try
199199 /// FastEmit_rr instead.
200 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
200 unsigned FastEmit_rf_(EVT::SimpleValueType VT,
201201 ISD::NodeType Opcode,
202202 unsigned Op0, ConstantFP *FPImm,
203 MVT::SimpleValueType ImmType);
203 EVT::SimpleValueType ImmType);
204204
205205 /// FastEmit_i - This method is called by target-independent code
206206 /// to request that an instruction with the given type, opcode, and
207207 /// immediate operand be emitted.
208 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
209 MVT::SimpleValueType RetVT,
208 virtual unsigned FastEmit_i(EVT::SimpleValueType VT,
209 EVT::SimpleValueType RetVT,
210210 ISD::NodeType Opcode,
211211 uint64_t Imm);
212212
213213 /// FastEmit_f - This method is called by target-independent code
214214 /// to request that an instruction with the given type, opcode, and
215215 /// floating-point immediate operand be emitted.
216 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
217 MVT::SimpleValueType RetVT,
216 virtual unsigned FastEmit_f(EVT::SimpleValueType VT,
217 EVT::SimpleValueType RetVT,
218218 ISD::NodeType Opcode,
219219 ConstantFP *FPImm);
220220
267267
268268 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
269269 /// from a specified index of a superregister to a specified type.
270 unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
270 unsigned FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
271271 unsigned Op0, uint32_t Idx);
272272
273273 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
274274 /// with all but the least significant bit set to zero.
275 unsigned FastEmitZExtFromI1(MVT::SimpleValueType VT,
275 unsigned FastEmitZExtFromI1(EVT::SimpleValueType VT,
276276 unsigned Op);
277277
278278 /// FastEmitBranch - Emit an unconditional branch to the given block,
236236
237237 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
238238 /// UNKNOWN_LIBCALL if there is none.
239 Libcall getFPEXT(MVT OpVT, MVT RetVT);
239 Libcall getFPEXT(EVT OpVT, EVT RetVT);
240240
241241 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
242242 /// UNKNOWN_LIBCALL if there is none.
243 Libcall getFPROUND(MVT OpVT, MVT RetVT);
243 Libcall getFPROUND(EVT OpVT, EVT RetVT);
244244
245245 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
246246 /// UNKNOWN_LIBCALL if there is none.
247 Libcall getFPTOSINT(MVT OpVT, MVT RetVT);
247 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
248248
249249 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
250250 /// UNKNOWN_LIBCALL if there is none.
251 Libcall getFPTOUINT(MVT OpVT, MVT RetVT);
251 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
252252
253253 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
254254 /// UNKNOWN_LIBCALL if there is none.
255 Libcall getSINTTOFP(MVT OpVT, MVT RetVT);
255 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
256256
257257 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
258258 /// UNKNOWN_LIBCALL if there is none.
259 Libcall getUINTTOFP(MVT OpVT, MVT RetVT);
259 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
260260 }
261261 }
262262
192192 /// setRoot - Set the current root tag of the SelectionDAG.
193193 ///
194194 const SDValue &setRoot(SDValue N) {
195 assert((!N.getNode() || N.getValueType() == MVT::Other) &&
195 assert((!N.getNode() || N.getValueType() == EVT::Other) &&
196196 "DAG root value is not a chain!");
197197 return Root = N;
198198 }
243243
244244 /// getVTList - Return an SDVTList that represents the list of values
245245 /// specified.
246 SDVTList getVTList(MVT VT);
247 SDVTList getVTList(MVT VT1, MVT VT2);
248 SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3);
249 SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4);
250 SDVTList getVTList(const MVT *VTs, unsigned NumVTs);
246 SDVTList getVTList(EVT VT);
247 SDVTList getVTList(EVT VT1, EVT VT2);
248 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
249 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
250 SDVTList getVTList(const EVT *VTs, unsigned NumVTs);
251251
252252 //===--------------------------------------------------------------------===//
253253 // Node creation methods.
254254 //
255 SDValue getConstant(uint64_t Val, MVT VT, bool isTarget = false);
256 SDValue getConstant(const APInt &Val, MVT VT, bool isTarget = false);
257 SDValue getConstant(const ConstantInt &Val, MVT VT, bool isTarget = false);
255 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
256 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
257 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
258258 SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false);
259 SDValue getTargetConstant(uint64_t Val, MVT VT) {
259 SDValue getTargetConstant(uint64_t Val, EVT VT) {
260260 return getConstant(Val, VT, true);
261261 }
262 SDValue getTargetConstant(const APInt &Val, MVT VT) {
262 SDValue getTargetConstant(const APInt &Val, EVT VT) {
263263 return getConstant(Val, VT, true);
264264 }
265 SDValue getTargetConstant(const ConstantInt &Val, MVT VT) {
265 SDValue getTargetConstant(const ConstantInt &Val, EVT VT) {
266266 return getConstant(Val, VT, true);
267267 }
268 SDValue getConstantFP(double Val, MVT VT, bool isTarget = false);
269 SDValue getConstantFP(const APFloat& Val, MVT VT, bool isTarget = false);
270 SDValue getConstantFP(const ConstantFP &CF, MVT VT, bool isTarget = false);
271 SDValue getTargetConstantFP(double Val, MVT VT) {
268 SDValue getConstantFP(double Val, EVT VT, bool isTarget = false);
269 SDValue getConstantFP(const APFloat& Val, EVT VT, bool isTarget = false);
270 SDValue getConstantFP(const ConstantFP &CF, EVT VT, bool isTarget = false);
271 SDValue getTargetConstantFP(double Val, EVT VT) {
272272 return getConstantFP(Val, VT, true);
273273 }
274 SDValue getTargetConstantFP(const APFloat& Val, MVT VT) {
274 SDValue getTargetConstantFP(const APFloat& Val, EVT VT) {
275275 return getConstantFP(Val, VT, true);
276276 }
277 SDValue getTargetConstantFP(const ConstantFP &Val, MVT VT) {
277 SDValue getTargetConstantFP(const ConstantFP &Val, EVT VT) {
278278 return getConstantFP(Val, VT, true);
279279 }
280 SDValue getGlobalAddress(const GlobalValue *GV, MVT VT,
280 SDValue getGlobalAddress(const GlobalValue *GV, EVT VT,
281281 int64_t offset = 0, bool isTargetGA = false,
282282 unsigned char TargetFlags = 0);
283 SDValue getTargetGlobalAddress(const GlobalValue *GV, MVT VT,
283 SDValue getTargetGlobalAddress(const GlobalValue *GV, EVT VT,
284284 int64_t offset = 0,
285285 unsigned char TargetFlags = 0) {
286286 return getGlobalAddress(GV, VT, offset, true, TargetFlags);
287287 }
288 SDValue getFrameIndex(int FI, MVT VT, bool isTarget = false);
289 SDValue getTargetFrameIndex(int FI, MVT VT) {
288 SDValue getFrameIndex(int FI, EVT VT, bool isTarget = false);
289 SDValue getTargetFrameIndex(int FI, EVT VT) {
290290 return getFrameIndex(FI, VT, true);
291291 }
292 SDValue getJumpTable(int JTI, MVT VT, bool isTarget = false,
292 SDValue getJumpTable(int JTI, EVT VT, bool isTarget = false,
293293 unsigned char TargetFlags = 0);
294 SDValue getTargetJumpTable(int JTI, MVT VT, unsigned char TargetFlags = 0) {
294 SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags = 0) {
295295 return getJumpTable(JTI, VT, true, TargetFlags);
296296 }
297 SDValue getConstantPool(Constant *C, MVT VT,
297 SDValue getConstantPool(Constant *C, EVT VT,
298298 unsigned Align = 0, int Offs = 0, bool isT=false,
299299 unsigned char TargetFlags = 0);
300 SDValue getTargetConstantPool(Constant *C, MVT VT,
300 SDValue getTargetConstantPool(Constant *C, EVT VT,
301301 unsigned Align = 0, int Offset = 0,
302302 unsigned char TargetFlags = 0) {
303303 return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
304304 }
305 SDValue getConstantPool(MachineConstantPoolValue *C, MVT VT,
305 SDValue getConstantPool(MachineConstantPoolValue *C, EVT VT,
306306 unsigned Align = 0, int Offs = 0, bool isT=false,
307307 unsigned char TargetFlags = 0);
308308 SDValue getTargetConstantPool(MachineConstantPoolValue *C,
309 MVT VT, unsigned Align = 0,
309 EVT VT, unsigned Align = 0,
310310 int Offset = 0, unsigned char TargetFlags=0) {
311311 return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
312312 }
314314 // to provide debug info for the BB at that time, so keep this one around.
315315 SDValue getBasicBlock(MachineBasicBlock *MBB);
316316 SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl);
317 SDValue getExternalSymbol(const char *Sym, MVT VT);
318 SDValue getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT);
319 SDValue getTargetExternalSymbol(const char *Sym, MVT VT,
317 SDValue getExternalSymbol(const char *Sym, EVT VT);
318 SDValue getExternalSymbol(const char *Sym, DebugLoc dl, EVT VT);
319 SDValue getTargetExternalSymbol(const char *Sym, EVT VT,
320320 unsigned char TargetFlags = 0);
321 SDValue getValueType(MVT);
322 SDValue getRegister(unsigned Reg, MVT VT);
321 SDValue getValueType(EVT);
322 SDValue getRegister(unsigned Reg, EVT VT);
323323 SDValue getDbgStopPoint(DebugLoc DL, SDValue Root,
324324 unsigned Line, unsigned Col, Value *CU);
325325 SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root,
326326 unsigned LabelID);
327327
328328 SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
329 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
329 return getNode(ISD::CopyToReg, dl, EVT::Other, Chain,
330330 getRegister(Reg, N.getValueType()), N);
331331 }
332332
335335 // null) and that there should be a flag result.
336336 SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N,
337337 SDValue Flag) {
338 SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
338 SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
339339 SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
340340 return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
341341 }
343343 // Similar to last getCopyToReg() except parameter Reg is a SDValue
344344 SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N,
345345 SDValue Flag) {
346 SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
346 SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
347347 SDValue Ops[] = { Chain, Reg, N, Flag };
348348 return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
349349 }
350350
351 SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT) {
352 SDVTList VTs = getVTList(VT, MVT::Other);
351 SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT) {
352 SDVTList VTs = getVTList(VT, EVT::Other);
353353 SDValue Ops[] = { Chain, getRegister(Reg, VT) };
354354 return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
355355 }
357357 // This version of the getCopyFromReg method takes an extra operand, which
358358 // indicates that there is potentially an incoming flag value (if Flag is not
359359 // null) and that there should be a flag result.
360 SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT,
360 SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT,
361361 SDValue Flag) {
362 SDVTList VTs = getVTList(VT, MVT::Other, MVT::Flag);
362 SDVTList VTs = getVTList(VT, EVT::Other, EVT::Flag);
363363 SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
364364 return getNode(ISD::CopyFromReg, dl, VTs, Ops, Flag.getNode() ? 3 : 2);
365365 }
368368
369369 /// Returns the ConvertRndSat Note: Avoid using this node because it may
370370 /// disappear in the future and most targets don't support it.
371 SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy,
371 SDValue getConvertRndSat(EVT VT, DebugLoc dl, SDValue Val, SDValue DTy,
372372 SDValue STy,
373373 SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
374374
376376 /// elements in VT, which must be a vector type, must match the number of
377377 /// mask elements NumElts. A integer mask element equal to -1 is treated as
378378 /// undefined.
379 SDValue getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, SDValue N2,
379 SDValue getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, SDValue N2,
380380 const int *MaskElts);
381381
382382 /// getZeroExtendInReg - Return the expression required to zero extend the Op
383383 /// value assuming it was the smaller SrcTy value.
384 SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy);
384 SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT SrcTy);
385385
386386 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
387 SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT);
387 SDValue getNOT(DebugLoc DL, SDValue Val, EVT VT);
388388
389389 /// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
390390 /// a flag result (to ensure it's not CSE'd). CALLSEQ_START does not have a
391391 /// useful DebugLoc.
392392 SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
393 SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
393 SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
394394 SDValue Ops[] = { Chain, Op };
395395 return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
396396 VTs, Ops, 2);
401401 /// a useful DebugLoc.
402402 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
403403 SDValue InFlag) {
404 SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
404 SDVTList NodeTys = getVTList(EVT::Other, EVT::Flag);
405405 SmallVector Ops;
406406 Ops.push_back(Chain);
407407 Ops.push_back(Op1);
413413 }
414414
415415 /// getUNDEF - Return an UNDEF node. UNDEF does not have a useful DebugLoc.
416 SDValue getUNDEF(MVT VT) {
416 SDValue getUNDEF(EVT VT) {
417417 return getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), VT);
418418 }
419419
420420 /// getGLOBAL_OFFSET_TABLE - Return a GLOBAL_OFFSET_TABLE node. This does
421421 /// not have a useful DebugLoc.
422 SDValue getGLOBAL_OFFSET_TABLE(MVT VT) {
422 SDValue getGLOBAL_OFFSET_TABLE(EVT VT) {
423423 return getNode(ISD::GLOBAL_OFFSET_TABLE, DebugLoc::getUnknownLoc(), VT);
424424 }
425425
426426 /// getNode - Gets or creates the specified node.
427427 ///
428 SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT);
429 SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N);
430 SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2);
431 SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
428 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT);
429 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N);
430 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2);
431 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
432432 SDValue N1, SDValue N2, SDValue N3);
433 SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
433 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
434434 SDValue N1, SDValue N2, SDValue N3, SDValue N4);
435 SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
435 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
436436 SDValue N1, SDValue N2, SDValue N3, SDValue N4,
437437 SDValue N5);
438 SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
438 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
439439 const SDUse *Ops, unsigned NumOps);
440 SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
440 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
441441 const SDValue *Ops, unsigned NumOps);
442442 SDValue getNode(unsigned Opcode, DebugLoc DL,
443 const std::vector<MVT> &ResultTys,
443 const std::vector<EVT> &ResultTys,
444444 const SDValue *Ops, unsigned NumOps);
445 SDValue getNode(unsigned Opcode, DebugLoc DL, const MVT *VTs, unsigned NumVTs,
445 SDValue getNode(unsigned Opcode, DebugLoc DL, const EVT *VTs, unsigned NumVTs,
446446 const SDValue *Ops, unsigned NumOps);
447447 SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
448448 const SDValue *Ops, unsigned NumOps);
481481 /// getSetCC - Helper function to make it easier to build SetCC's if you just
482482 /// have an ISD::CondCode instead of an SDValue.
483483 ///
484 SDValue getSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS,
484 SDValue getSetCC(DebugLoc DL, EVT VT, SDValue LHS, SDValue RHS,
485485 ISD::CondCode Cond) {
486486 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
487487 }
489489 /// getVSetCC - Helper function to make it easier to build VSetCC's nodes
490490 /// if you just have an ISD::CondCode instead of an SDValue.
491491 ///
492 SDValue getVSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS,
492 SDValue getVSetCC(DebugLoc DL, EVT VT, SDValue LHS, SDValue RHS,
493493 ISD::CondCode Cond) {
494494 return getNode(ISD::VSETCC, DL, VT, LHS, RHS, getCondCode(Cond));
495495 }
505505
506506 /// getVAArg - VAArg produces a result and token chain, and takes a pointer
507507 /// and a source value as input.
508 SDValue getVAArg(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
508 SDValue getVAArg(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
509509 SDValue SV);
510510
511511 /// getAtomic - Gets a node for an atomic op, produces result and chain and
512512 /// takes 3 operands
513 SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
513 SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
514514 SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal,
515515 unsigned Alignment=0);
516516
517517 /// getAtomic - Gets a node for an atomic op, produces result and chain and
518518 /// takes 2 operands.
519 SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
519 SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
520520 SDValue Ptr, SDValue Val, const Value* PtrVal,
521521 unsigned Alignment = 0);
522522
523523 /// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a
524524 /// result and takes a list of operands.
525525 SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
526 const MVT *VTs, unsigned NumVTs,
526 const EVT *VTs, unsigned NumVTs,
527527 const SDValue *Ops, unsigned NumOps,
528 MVT MemVT, const Value *srcValue, int SVOff,
528 EVT MemVT, const Value *srcValue, int SVOff,
529529 unsigned Align = 0, bool Vol = false,
530530 bool ReadMem = true, bool WriteMem = true);
531531
532532 SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
533533 const SDValue *Ops, unsigned NumOps,
534 MVT MemVT, const Value *srcValue, int SVOff,
534 EVT MemVT, const Value *srcValue, int SVOff,
535535 unsigned Align = 0, bool Vol = false,
536536 bool ReadMem = true, bool WriteMem = true);
537537
541541 /// getLoad - Loads are not normal binary operators: their result type is not
542542 /// determined by their operands, and they produce a value AND a token chain.
543543 ///
544 SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
544 SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
545545 const Value *SV, int SVOffset, bool isVolatile=false,
546546 unsigned Alignment=0);
547 SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
547 SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
548548 SDValue Chain, SDValue Ptr, const Value *SV,
549 int SVOffset, MVT EVT, bool isVolatile=false,
549 int SVOffset, EVT EVT, bool isVolatile=false,
550550 unsigned Alignment=0);
551551 SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
552552 SDValue Offset, ISD::MemIndexedMode AM);
553553 SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType,
554 MVT VT, SDValue Chain,
554 EVT VT, SDValue Chain,
555555 SDValue Ptr, SDValue Offset,
556 const Value *SV, int SVOffset, MVT EVT,
556 const Value *SV, int SVOffset, EVT EVT,
557557 bool isVolatile=false, unsigned Alignment=0);
558558
559559 /// getStore - Helper function to build ISD::STORE nodes.
562562 const Value *SV, int SVOffset, bool isVolatile=false,
563563 unsigned Alignment=0);
564564 SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
565 const Value *SV, int SVOffset, MVT TVT,
565 const Value *SV, int SVOffset, EVT TVT,
566566 bool isVolatile=false, unsigned Alignment=0);
567567 SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue Base,
568568 SDValue Offset, ISD::MemIndexedMode AM);
599599 /// specified node to have the specified return type, Target opcode, and
600600 /// operands. Note that target opcodes are stored as
601601 /// ~TargetOpcode in the node opcode field. The resultant node is returned.
602 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT);
603 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDValue Op1);
604 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
602 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT);
603 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1);
604 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
605605 SDValue Op1, SDValue Op2);
606 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
606 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
607607 SDValue Op1, SDValue Op2, SDValue Op3);
608 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
608 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
609609 const SDValue *Ops, unsigned NumOps);
610 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1, MVT VT2);
611 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
612 MVT VT2, const SDValue *Ops, unsigned NumOps);
613 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
614 MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps);
615 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, MVT VT1,
616 MVT VT2, MVT VT3, MVT VT4, const SDValue *Ops,
610 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2);
611 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
612 EVT VT2, const SDValue *Ops, unsigned NumOps);
613 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
614 EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps);
615 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
616 EVT VT2, EVT VT3, EVT VT4, const SDValue *Ops,
617617 unsigned NumOps);
618 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
619 MVT VT2, SDValue Op1);
620 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
621 MVT VT2, SDValue Op1, SDValue Op2);
622 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
623 MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
624 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
625 MVT VT2, MVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
618 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
619 EVT VT2, SDValue Op1);
620 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
621 EVT VT2, SDValue Op1, SDValue Op2);
622 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
623 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
624 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
625 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
626626 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, SDVTList VTs,
627627 const SDValue *Ops, unsigned NumOps);
628628
629629 /// MorphNodeTo - These *mutate* the specified node to have the specified
630630 /// return type, opcode, and operands.
631 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT);
632 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT, SDValue Op1);
633 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
631 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT);
632 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT, SDValue Op1);
633 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT,
634634 SDValue Op1, SDValue Op2);
635 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
635 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT,
636636 SDValue Op1, SDValue Op2, SDValue Op3);
637 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
637 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT,
638638 const SDValue *Ops, unsigned NumOps);
639 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1, MVT VT2);
640 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
641 MVT VT2, const SDValue *Ops, unsigned NumOps);
642 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
643 MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps);
644 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
645 MVT VT2, SDValue Op1);
646 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
647 MVT VT2, SDValue Op1, SDValue Op2);
648 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
649 MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
639 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1, EVT VT2);
640 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1,
641 EVT VT2, const SDValue *Ops, unsigned NumOps);
642 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1,
643 EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps);
644 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1,
645 EVT VT2, SDValue Op1);
646 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1,
647 EVT VT2, SDValue Op1, SDValue Op2);
648 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1,
649 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
650650 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs,
651651 const SDValue *Ops, unsigned NumOps);
652652
656656 /// Note that getTargetNode returns the resultant node. If there is already a
657657 /// node of the specified opcode and operands, it returns that node instead of
658658 /// the current one.
659 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
660 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1);
661 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1,
659 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT);
660 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1);
661 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1,
662662 SDValue Op2);
663 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
663 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
664664 SDValue Op1, SDValue Op2, SDValue Op3);
665 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
665 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
666666 const SDValue *Ops, unsigned NumOps);
667 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2);
668 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
667 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2);
668 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
669669 SDValue Op1);
670 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
671 MVT VT2, SDValue Op1, SDValue Op2);
672 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
673 MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
674 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
670 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
671 EVT VT2, SDValue Op1, SDValue Op2);
672 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
673 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
674 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
675675 const SDValue *Ops, unsigned NumOps);
676 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
676 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
677677 SDValue Op1, SDValue Op2);
678 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
678 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
679679 SDValue Op1, SDValue Op2, SDValue Op3);
680 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
680 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
681681 const SDValue *Ops, unsigned NumOps);
682 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
683 MVT VT4, const SDValue *Ops, unsigned NumOps);
682 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
683 EVT VT4, const SDValue *Ops, unsigned NumOps);
684684 SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
685 const std::vector<MVT> &ResultTys, const SDValue *Ops,
685 const std::vector<EVT> &ResultTys, const SDValue *Ops,
686686 unsigned NumOps);
687687
688688 /// getNodeIfExists - Get the specified node if it's already available, or
791791 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
792792 /// specified value type. If minAlign is specified, the slot size will have
793793 /// at least that alignment.
794 SDValue CreateStackTemporary(MVT VT, unsigned minAlign = 1);
794 SDValue CreateStackTemporary(EVT VT, unsigned minAlign = 1);
795795
796796 /// CreateStackTemporary - Create a stack temporary suitable for holding
797797 /// either of the specified value types.
798 SDValue CreateStackTemporary(MVT VT1, MVT VT2);
798 SDValue CreateStackTemporary(EVT VT1, EVT VT2);
799799
800800 /// FoldConstantArithmetic -
801801 SDValue FoldConstantArithmetic(unsigned Opcode,
802 MVT VT,
802 EVT VT,
803803 ConstantSDNode *Cst1,
804804 ConstantSDNode *Cst2);
805805
806806 /// FoldSetCC - Constant fold a setcc to true or false.
807 SDValue FoldSetCC(MVT VT, SDValue N1,
807 SDValue FoldSetCC(EVT VT, SDValue N1,
808808 SDValue N2, ISD::CondCode Cond, DebugLoc dl);
809809
810810 /// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
854854 void DeleteNodeNotInCSEMaps(SDNode *N);
855855 void DeallocateNode(SDNode *N);
856856
857 unsigned getMVTAlignment(MVT MemoryVT) const;
857 unsigned getEVTAlignment(EVT MemoryVT) const;
858858
859859 void allnodes_clear();
860860
865865 std::vector CondCodeNodes;
866866
867867 std::vector ValueTypeNodes;
868 std::map<MVT, SDNode*, MVT::compareRawBits> ExtendedValueTypeNodes;
868 std::map<EVT, SDNode*, EVT::compareRawBits> ExtendedValueTypeNodes;
869869 StringMap ExternalSymbols;
870870
871871 std::map,SDNode*> TargetExternalSymbols;
6464
6565 virtual bool runOnMachineFunction(MachineFunction &MF);
6666
67 unsigned MakeReg(MVT VT);
67 unsigned MakeReg(EVT VT);
6868
6969 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
7070 virtual void InstructionSelect() = 0;
5151 /// SelectionDAG::getVTList(...).
5252 ///
5353 struct SDVTList {
54 const MVT *VTs;
54 const EVT *VTs;
5555 unsigned int NumVTs;
5656 };
5757
855855
856856 /// getValueType - Return the ValueType of the referenced return value.
857857 ///
858 inline MVT getValueType() const;
858 inline EVT getValueType() const;
859859
860860 /// getValueSizeInBits - Returns the size of the value in bits.
861861 ///
964964 /// getResNo - Convenience function for get().getResNo().
965965 unsigned getResNo() const { return Val.getResNo(); }
966966 /// getValueType - Convenience function for get().getValueType().
967 MVT getValueType() const { return Val.getValueType(); }
967 EVT getValueType() const { return Val.getValueType(); }
968968
969969 /// operator== - Convenience function for get().operator==
970970 bool operator==(const SDValue &V) const {
10541054
10551055 /// ValueList - The types of the values this node defines. SDNode's may
10561056 /// define multiple values simultaneously.
1057 const MVT *ValueList;
1057 const EVT *ValueList;
10581058
10591059 /// UseList - List of uses for this SDNode.
10601060 SDUse *UseList;
10661066 DebugLoc debugLoc;
10671067
10681068 /// getValueTypeList - Return a pointer to the specified value type.
1069 static const MVT *getValueTypeList(MVT VT);
1069 static const EVT *getValueTypeList(EVT VT);
10701070
10711071 friend class SelectionDAG;
10721072 friend struct ilist_traits;
12401240 /// to which the flag operand points. Otherwise return NULL.
12411241 SDNode *getFlaggedNode() const {
12421242 if (getNumOperands() != 0 &&
1243 getOperand(getNumOperands()-1).getValueType() == MVT::Flag)
1243 getOperand(getNumOperands()-1).getValueType() == EVT::Flag)
12441244 return getOperand(getNumOperands()-1).getNode();
12451245 return 0;
12461246 }
12681268
12691269 /// getValueType - Return the type of a specified result.
12701270 ///
1271 MVT getValueType(unsigned ResNo) const {
1271 EVT getValueType(unsigned ResNo) const {
12721272 assert(ResNo < NumValues && "Illegal result number!");
12731273 return ValueList[ResNo];
12741274 }
12751275
1276 /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)).
1276 /// getValueSizeInBits - Returns EVT::getSizeInBits(getValueType(ResNo)).
12771277 ///
12781278 unsigned getValueSizeInBits(unsigned ResNo) const {
12791279 return getValueType(ResNo).getSizeInBits();
12801280 }
12811281
1282 typedef const MVT* value_iterator;
1282 typedef const EVT* value_iterator;
12831283 value_iterator value_begin() const { return ValueList; }
12841284 value_iterator value_end() const { return ValueList+NumValues; }
12851285
13061306 void addUse(SDUse &U) { U.addToList(&UseList); }
13071307
13081308 protected:
1309 static SDVTList getSDVTList(MVT VT) {
1309 static SDVTList getSDVTList(EVT VT) {
13101310 SDVTList Ret = { getValueTypeList(VT), 1 };
13111311 return Ret;
13121312 }
14001400 inline unsigned SDValue::getOpcode() const {
14011401 return Node->getOpcode();
14021402 }
1403 inline MVT SDValue::getValueType() const {
1403 inline EVT SDValue::getValueType() const {
14041404 return Node->getValueType(ResNo);
14051405 }
14061406 inline unsigned SDValue::getNumOperands() const {
15001500 explicit HandleSDNode(SDValue X)
15011501 #endif
15021502 : SDNode(ISD::HANDLENODE, DebugLoc::getUnknownLoc(),
1503 getSDVTList(MVT::Other)) {
1503 getSDVTList(EVT::Other)) {
15041504 InitOperands(&Op, X);
15051505 }
15061506 ~HandleSDNode();
15111511 class MemSDNode : public SDNode {
15121512 private:
15131513 // MemoryVT - VT of in-memory value.
1514 MVT MemoryVT;
1514 EVT MemoryVT;
15151515
15161516 //! SrcValue - Memory location for alias analysis.
15171517 const Value *SrcValue;
15201520 int SVOffset;
15211521
15221522 public:
1523 MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT,
1523 MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, EVT MemoryVT,
15241524 const Value *srcValue, int SVOff,
15251525 unsigned alignment, bool isvolatile);
15261526
15271527 MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops,
1528 unsigned NumOps, MVT MemoryVT, const Value *srcValue, int SVOff,
1528 unsigned NumOps, EVT MemoryVT, const Value *srcValue, int SVOff,
15291529 unsigned alignment, bool isvolatile);
15301530
15311531 /// Returns alignment and volatility of the memory access
15451545 int getSrcValueOffset() const { return SVOffset; }
15461546
15471547 /// getMemoryVT - Return the type of the in-memory value.
1548 MVT getMemoryVT() const { return MemoryVT; }
1548 EVT getMemoryVT() const { return MemoryVT; }
15491549
15501550 /// getMemOperand - Return a MachineMemOperand object describing the memory
15511551 /// reference performed by operation.
15951595 // Swp: swap value
15961596 // SrcVal: address to update as a Value (used for MemOperand)
15971597 // Align: alignment of memory
1598 AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT,
1598 AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
15991599 SDValue Chain, SDValue Ptr,
16001600 SDValue Cmp, SDValue Swp, const Value* SrcVal,
16011601 unsigned Align=0)
16031603 Align, /*isVolatile=*/true) {
16041604 InitOperands(Ops, Chain, Ptr, Cmp, Swp);
16051605 }
1606 AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT,
1606 AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
16071607 SDValue Chain, SDValue Ptr,
16081608 SDValue Val, const Value* SrcVal, unsigned Align=0)
16091609 : MemSDNode(Opc, dl, VTL, MemVT, SrcVal, /*SVOffset=*/0,
16461646 public:
16471647 MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
16481648 const SDValue *Ops, unsigned NumOps,
1649 MVT MemoryVT, const Value *srcValue, int SVO,
1649 EVT MemoryVT, const Value *srcValue, int SVO,
16501650 unsigned Align, bool Vol, bool ReadMem, bool WriteMem)
16511651 : MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, srcValue, SVO, Align, Vol),
16521652 ReadMem(ReadMem), WriteMem(WriteMem) {
16821682 const int *Mask;
16831683 protected:
16841684 friend class SelectionDAG;
1685 ShuffleVectorSDNode(MVT VT, DebugLoc dl, SDValue N1, SDValue N2,
1685 ShuffleVectorSDNode(EVT VT, DebugLoc dl, SDValue N1, SDValue N2,
16861686 const int *M)
16871687 : SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {
16881688 InitOperands(Ops, N1, N2);
16901690 public:
16911691
16921692 void getMask(SmallVectorImpl &M) const {
1693 MVT VT = getValueType(0);
1693 EVT VT = getValueType(0);
16941694 M.clear();
16951695 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16961696 M.push_back(Mask[i]);
17051705 assert(isSplat() && "Cannot get splat index for non-splat!");
17061706 return Mask[0];
17071707 }
1708 static bool isSplatMask(const int *Mask, MVT VT);
1708 static bool isSplatMask(const int *Mask, EVT VT);
17091709
17101710 static bool classof(const ShuffleVectorSDNode *) { return true; }
17111711 static bool classof(const SDNode *N) {
17161716 class ConstantSDNode : public SDNode {
17171717 const ConstantInt *Value;
17181718 friend class SelectionDAG;
1719 ConstantSDNode(bool isTarget, const ConstantInt *val, MVT VT)
1719 ConstantSDNode(bool isTarget, const ConstantInt *val, EVT VT)
17201720 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
17211721 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Value(val) {
17221722 }
17401740 class ConstantFPSDNode : public SDNode {
17411741 const ConstantFP *Value;
17421742 friend class SelectionDAG;
1743 ConstantFPSDNode(bool isTarget, const ConstantFP *val, MVT VT)
1743 ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
17441744 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,
17451745 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Value(val) {
17461746 }
17691769 }
17701770 bool isExactlyValue(const APFloat& V) const;
17711771
1772 bool isValueValidForType(MVT VT, const APFloat& Val);
1772 bool isValueValidForType(EVT VT, const APFloat& Val);
17731773
17741774 static bool classof(const ConstantFPSDNode *) { return true; }
17751775 static bool classof(const SDNode *N) {
17831783 int64_t Offset;
17841784 unsigned char TargetFlags;
17851785 friend class SelectionDAG;
1786 GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA, MVT VT,
1786 GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA, EVT VT,
17871787 int64_t o, unsigned char TargetFlags);
17881788 public:
17891789
18051805 class FrameIndexSDNode : public SDNode {
18061806 int FI;
18071807 friend class SelectionDAG;
1808 FrameIndexSDNode(int fi, MVT VT, bool isTarg)
1808 FrameIndexSDNode(int fi, EVT VT, bool isTarg)
18091809 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
18101810 DebugLoc::getUnknownLoc(), getSDVTList(VT)), FI(fi) {
18111811 }
18241824 int JTI;
18251825 unsigned char TargetFlags;
18261826 friend class SelectionDAG;
1827 JumpTableSDNode(int jti, MVT VT, bool isTarg, unsigned char TF)
1827 JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned char TF)
18281828 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
18291829 DebugLoc::getUnknownLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
18301830 }
18491849 unsigned Alignment; // Minimum alignment requirement of CP (not log2 value).
18501850 unsigned char TargetFlags;
18511851 friend class SelectionDAG;
1852 ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o, unsigned Align,
1852 ConstantPoolSDNode(bool isTarget, Constant *c, EVT VT, int o, unsigned Align,
18531853 unsigned char TF)
18541854 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
18551855 DebugLoc::getUnknownLoc(),
18581858 Val.ConstVal = c;
18591859 }
18601860 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
1861 MVT VT, int o, unsigned Align, unsigned char TF)
1861 EVT VT, int o, unsigned Align, unsigned char TF)
18621862 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
18631863 DebugLoc::getUnknownLoc(),
18641864 getSDVTList(VT)), Offset(o), Alignment(Align), TargetFlags(TF) {
19091909 /// harder. Let's see if we need it first.
19101910 explicit BasicBlockSDNode(MachineBasicBlock *mbb)
19111911 : SDNode(ISD::BasicBlock, DebugLoc::getUnknownLoc(),
1912 getSDVTList(MVT::Other)), MBB(mbb) {
1912 getSDVTList(EVT::Other)), MBB(mbb) {
19131913 }
19141914 public:
19151915
19601960 /// Create a SrcValue for a general value.
19611961 explicit SrcValueSDNode(const Value *v)
19621962 : SDNode(ISD::SRCVALUE, DebugLoc::getUnknownLoc(),
1963 getSDVTList(MVT::Other)), V(v) {}
1963 getSDVTList(EVT::Other)), V(v) {}
19641964
19651965 public:
19661966 /// getValue - return the contained Value.
19821982 /// Create a MachineMemOperand node
19831983 explicit MemOperandSDNode(const MachineMemOperand &mo)
19841984 : SDNode(ISD::MEMOPERAND, DebugLoc::getUnknownLoc(),
1985 getSDVTList(MVT::Other)), MO(mo) {}
1985 getSDVTList(EVT::Other)), MO(mo) {}
19861986
19871987 public:
19881988 /// MO - The contained MachineMemOperand.
19981998 class RegisterSDNode : public SDNode {
19991999 unsigned Reg;
20002000 friend class SelectionDAG;
2001 RegisterSDNode(unsigned reg, MVT VT)
2001 RegisterSDNode(unsigned reg, EVT VT)
20022002 : SDNode(ISD::Register, DebugLoc::getUnknownLoc(),
20032003 getSDVTList(VT)), Reg(reg) {
20042004 }
20212021 DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c,
20222022 Value *cu)
20232023 : SDNode(ISD::DBG_STOPPOINT, DebugLoc::getUnknownLoc(),
2024 getSDVTList(MVT::Other)), Line(l), Column(c), CU(cu) {
2024 getSDVTList(EVT::Other)), Line(l), Column(c), CU(cu) {
20252025 InitOperands(&Chain, ch);
20262026 }
20272027 public:
20402040 unsigned LabelID;
20412041 friend class SelectionDAG;
20422042 LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id)
2043 : SDNode(NodeTy, dl, getSDVTList(MVT::Other)), LabelID(id) {
2043 : SDNode(NodeTy, dl, getSDVTList(EVT::Other)), LabelID(id) {
20442044 InitOperands(&Chain, ch);
20452045 }
20462046 public:
20582058 unsigned char TargetFlags;
20592059
20602060 friend class SelectionDAG;
2061 ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, MVT VT)
2061 ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, EVT VT)
20622062 : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
20632063 DebugLoc::getUnknownLoc(),
20642064 getSDVTList(VT)), Symbol(Sym), TargetFlags(TF) {
20802080 friend class SelectionDAG;
20812081 explicit CondCodeSDNode(ISD::CondCode Cond)
20822082 : SDNode(ISD::CONDCODE, DebugLoc::getUnknownLoc(),
2083 getSDVTList(MVT::Other)), Condition(Cond) {
2083 getSDVTList(EVT::Other)), Condition(Cond) {
20842084 }
20852085 public:
20862086
20972097 class CvtRndSatSDNode : public SDNode {
20982098 ISD::CvtCode CvtCode;
20992099 friend class SelectionDAG;
2100 explicit CvtRndSatSDNode(MVT VT, DebugLoc dl, const SDValue *Ops,
2100 explicit CvtRndSatSDNode(EVT VT, DebugLoc dl, const SDValue *Ops,
21012101 unsigned NumOps, ISD::CvtCode Code)
21022102 : SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),
21032103 CvtCode(Code) {
22022202 ///
22032203 struct InputArg {
22042204 ArgFlagsTy Flags;
2205 MVT VT;
2205 EVT VT;
22062206 bool Used;
22072207
2208 InputArg() : VT(MVT::Other), Used(false) {}
2209 InputArg(ISD::ArgFlagsTy flags, MVT vt, bool used)
2208 InputArg() : VT(EVT::Other), Used(false) {}
2209 InputArg(ISD::ArgFlagsTy flags, EVT vt, bool used)
22102210 : Flags(flags), VT(vt), Used(used) {
22112211 assert(VT.isSimple() &&
22122212 "InputArg value type must be Simple!");
22312231 };
22322232 }
22332233
2234 /// VTSDNode - This class is used to represent MVT's, which are used
2234 /// VTSDNode - This class is used to represent EVT's, which are used
22352235 /// to parameterize some operations.
22362236 class VTSDNode : public SDNode {
2237 MVT ValueType;
2237 EVT ValueType;
22382238 friend class SelectionDAG;
2239 explicit VTSDNode(MVT VT)
2239 explicit VTSDNode(EVT VT)
22402240 : SDNode(ISD::VALUETYPE, DebugLoc::getUnknownLoc(),
2241 getSDVTList(MVT::Other)), ValueType(VT) {
2242 }
2243 public:
2244
2245 MVT getVT() const { return ValueType; }
2241 getSDVTList(EVT::Other)), ValueType(VT) {
2242 }
2243 public:
2244
2245 EVT getVT() const { return ValueType; }
22462246
22472247 static bool classof(const VTSDNode *) { return true; }
22482248 static bool classof(const SDNode *N) {
22632263 public:
22642264 LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands,
22652265 unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM,
2266 MVT VT, const Value *SV, int SVO, unsigned Align, bool Vol)
2266 EVT VT, const Value *SV, int SVO, unsigned Align, bool Vol)
22672267 : MemSDNode(NodeTy, dl, VTs, VT, SV, SVO, Align, Vol) {
22682268 assert(Align != 0 && "Loads and stores should have non-zero aligment");
22692269 SubclassData |= AM << 2;
23012301 class LoadSDNode : public LSBaseSDNode {
23022302 friend class SelectionDAG;
23032303 LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs,
2304 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT,
2304 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT LVT,
23052305 const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
23062306 : LSBaseSDNode(ISD::LOAD, dl, ChainPtrOff, 3,
23072307 VTs, AM, LVT, SV, O, Align, Vol) {
23302330 class StoreSDNode : public LSBaseSDNode {
23312331 friend class SelectionDAG;
23322332 StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs,
2333 ISD::MemIndexedMode AM, bool isTrunc, MVT SVT,
2333 ISD::MemIndexedMode AM, bool isTrunc, EVT SVT,
23342334 const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
23352335 : LSBaseSDNode(ISD::STORE, dl, ChainValuePtrOff, 4,
23362336 VTs, AM, SVT, SV, O, Align, Vol) {
2424 class Type;
2525 struct LLVMContext;
2626
27 struct MVT { // MVT = Machine Value Type
27 struct EVT { // EVT = Machine Value Type
2828 public:
2929 enum SimpleValueType {
3030 // If you change this numbering, you must change the values in
7777 LAST_VALUETYPE = 34, // This always remains at the end of the list.
7878
7979 // This is the current maximum for LAST_VALUETYPE.
80 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
80 // EVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
8181 // This value must be a multiple of 32.
8282 MAX_ALLOWED_VALUETYPE = 64,
8383
110110 private:
111111 /// This union holds low-level value types. Valid values include any of
112112 /// the values in the SimpleValueType enum, or any value returned from one
113 /// of the MVT methods. Any value type equal to one of the SimpleValueType
113 /// of the EVT methods. Any value type equal to one of the SimpleValueType
114114 /// enum values is a "simple" value type. All others are "extended".
115115 ///
116116 /// Note that simple doesn't necessary mean legal for the target machine.
123123 };
124124
125125 public:
126 MVT() {}
127 MVT(SimpleValueType S) : V(S) {}
128
129 bool operator==(const MVT VT) const {
126 EVT() {}
127 EVT(SimpleValueType S) : V(S) {}
128
129 bool operator==(const EVT VT) const {
130130 return getRawBits() == VT.getRawBits();
131131 }
132 bool operator!=(const MVT VT) const {
132 bool operator!=(const EVT VT) const {
133133 return getRawBits() != VT.getRawBits();
134134 }
135135
136 /// getFloatingPointVT - Returns the MVT that represents a floating point
136 /// getFloatingPointVT - Returns the EVT that represents a floating point
137137 /// type with the given number of bits. There are two floating point types
138138 /// with 128 bits - this returns f128 rather than ppcf128.
139 static MVT getFloatingPointVT(unsigned BitWidth) {
139 static EVT getFloatingPointVT(unsigned BitWidth) {
140140 switch (BitWidth) {
141141 default:
142142 assert(false && "Bad bit width!");
151151 }
152152 }
153153
154 /// getIntegerVT - Returns the MVT that represents an integer with the given
154 /// getIntegerVT - Returns the EVT that represents an integer with the given
155155 /// number of bits.
156 static MVT getIntegerVT(unsigned BitWidth) {
156 static EVT getIntegerVT(unsigned BitWidth) {
157157 switch (BitWidth) {
158158 default:
159159 break;
173173 return getExtendedIntegerVT(BitWidth);
174174 }
175175
176 /// getVectorVT - Returns the MVT that represents a vector NumElements in
176 /// getVectorVT - Returns the EVT that represents a vector NumElements in
177177 /// length, where each element is of type VT.
178 static MVT getVectorVT(MVT VT, unsigned NumElements) {
178 static EVT getVectorVT(EVT VT, unsigned NumElements) {
179179 switch (VT.V) {
180180 default:
181181 break;
217217
218218 /// getIntVectorWithNumElements - Return any integer vector type that has
219219 /// the specified number of elements.
220 static MVT getIntVectorWithNumElements(unsigned NumElts) {
220 static EVT getIntVectorWithNumElements(unsigned NumElts) {
221221 switch (NumElts) {
222222 default: return getVectorVT(i8, NumElts);
223223 case 1: return v1i64;
228228 }
229229 }
230230
231 /// isSimple - Test if the given MVT is simple (as opposed to being
231 /// isSimple - Test if the given EVT is simple (as opposed to being
232232 /// extended).
233233 bool isSimple() const {
234234 return V <= LastSimpleValueType;
235235 }
236236
237 /// isExtended - Test if the given MVT is extended (as opposed to
237 /// isExtended - Test if the given EVT is extended (as opposed to
238238 /// being simple).
239239 bool isExtended() const {
240240 return !isSimple();
295295 }
296296
297297 /// bitsEq - Return true if this has the same number of bits as VT.
298 bool bitsEq(MVT VT) const {
298 bool bitsEq(EVT VT) const {
299299 return getSizeInBits() == VT.getSizeInBits();
300300 }
301301
302302 /// bitsGT - Return true if this has more bits than VT.
303 bool bitsGT(MVT VT) const {
303 bool bitsGT(EVT VT) const {
304304 return getSizeInBits() > VT.getSizeInBits();
305305 }
306306
307307 /// bitsGE - Return true if this has no less bits than VT.
308 bool bitsGE(MVT VT) const {
308 bool bitsGE(EVT VT) const {
309309 return getSizeInBits() >= VT.getSizeInBits();
310310 }
311311
312312 /// bitsLT - Return true if this has less bits than VT.
313 bool bitsLT(MVT VT) const {
313 bool bitsLT(EVT VT) const {
314314 return getSizeInBits() < VT.getSizeInBits();
315315 }
316316
317317 /// bitsLE - Return true if this has no more bits than VT.
318 bool bitsLE(MVT VT) const {
318 bool bitsLE(EVT VT) const {
319319 return getSizeInBits() <= VT.getSizeInBits();
320320 }
321321
322322
323323 /// getSimpleVT - Return the SimpleValueType held in the specified
324 /// simple MVT.
324 /// simple EVT.
325325 SimpleValueType getSimpleVT() const {
326326 assert(isSimple() && "Expected a SimpleValueType!");
327327 return SimpleValueType(V);
329329
330330 /// getVectorElementType - Given a vector type, return the type of
331331 /// each element.
332 MVT getVectorElementType() const {
332 EVT getVectorElementType() const {
333333 assert(isVector() && "Invalid vector type!");
334334 switch (V) {
335335 default:
438438 return (getSizeInBits() + 7)/8*8;
439439 }
440440
441 /// getRoundIntegerType - Rounds the bit-width of the given integer MVT up
441 /// getRoundIntegerType - Rounds the bit-width of the given integer EVT up
442442 /// to the nearest power of two (and at least to eight), and returns the
443 /// integer MVT with that number of bits.
444 MVT getRoundIntegerType() const {
443 /// integer EVT with that number of bits.
444 EVT getRoundIntegerType() const {
445445 assert(isInteger() && !isVector() && "Invalid integer type!");
446446 unsigned BitWidth = getSizeInBits();
447447 if (BitWidth <= 8)
456456 return !(NElts & (NElts - 1));
457457 }
458458
459 /// getPow2VectorType - Widens the length of the given vector MVT up to
459 /// getPow2VectorType - Widens the length of the given vector EVT up to
460460 /// the nearest power of 2 and returns that type.
461 MVT getPow2VectorType() const {
461 EVT getPow2VectorType() const {
462462 if (!isPow2VectorType()) {
463463 unsigned NElts = getVectorNumElements();
464464 unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
465 return MVT::getVectorVT(getVectorElementType(), Pow2NElts);
465 return EVT::getVectorVT(getVectorElementType(), Pow2NElts);
466466 }
467467 else {
468468 return *this;
469469 }
470470 }
471471
472 /// getMVTString - This function returns value type as a string,
472 /// getEVTString - This function returns value type as a string,
473473 /// e.g. "i32".
474 std::string getMVTString() const;
475
476 /// getTypeForMVT - This method returns an LLVM type corresponding to the
477 /// specified MVT. For integer types, this returns an unsigned type. Note
474 std::string getEVTString() const;
475
476 /// getTypeForEVT - This method returns an LLVM type corresponding to the
477 /// specified EVT. For integer types, this returns an unsigned type. Note
478478 /// that this will abort for types that cannot be represented.
479 const Type *getTypeForMVT() const;
480
481 /// getMVT - Return the value type corresponding to the specified type.
479 const Type *getTypeForEVT() const;
480
481 /// getEVT - Return the value type corresponding to the specified type.
482482 /// This returns all pointers as iPTR. If HandleUnknown is true, unknown
483483 /// types are returned as Other, otherwise they are invalid.
484 static MVT getMVT(const Type *Ty, bool HandleUnknown = false);
484 static EVT getEVT(const Type *Ty, bool HandleUnknown = false);
485485
486486 /// getRawBits - Represent the type as a bunch of bits.
487487 uintptr_t getRawBits() const { return V; }
489489 /// compareRawBits - A meaningless but well-behaved order, useful for
490490 /// constructing containers.
491491 struct compareRawBits {
492 bool operator()(MVT L, MVT R) const {
492 bool operator()(EVT L, EVT R) const {
493493 return L.getRawBits() < R.getRawBits();
494494 }
495495 };
498498 // Methods for handling the Extended-type case in functions above.
499499 // These are all out-of-line to prevent users of this header file
500500 // from having a dependency on Type.h.
501 static MVT getExtendedIntegerVT(unsigned BitWidth);
502 static MVT getExtendedVectorVT(MVT VT, unsigned NumElements);
501 static EVT getExtendedIntegerVT(unsigned BitWidth);
502 static EVT getExtendedVectorVT(EVT VT, unsigned NumElements);
503503 bool isExtendedFloatingPoint() const;
504504 bool isExtendedInteger() const;
505505 bool isExtendedVector() const;
506506 bool isExtended64BitVector() const;
507507 bool isExtended128BitVector() const;
508508 bool isExtended256BitVector() const;
509 MVT getExtendedVectorElementType() const;
509 EVT getExtendedVectorElementType() const;
510510 unsigned getExtendedVectorNumElements() const;
511511 unsigned getExtendedSizeInBits() const;
512512 };
110110
111111 bool isBigEndian() const { return !IsLittleEndian; }
112112 bool isLittleEndian() const { return IsLittleEndian; }
113 MVT::SimpleValueType getPointerTy() const { return PointerTy; }
114 MVT::SimpleValueType getShiftAmountTy() const { return ShiftAmountTy; }
113 EVT::SimpleValueType getPointerTy() const { return PointerTy; }
114 EVT::SimpleValueType getShiftAmountTy() const { return ShiftAmountTy; }
115115
116116 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
117117 /// codegen.
132132 /// getSetCCResultType - Return the ValueType of the result of SETCC
133133 /// operations. Also used to obtain the target's preferred type for
134134 /// the condition operand of SELECT and BRCOND nodes. In the case of
135 /// BRCOND the argument passed is MVT::Other since there are no other
135 /// BRCOND the argument passed is EVT::Other since there are no other
136136 /// operands to get a type hint from.
137137 virtual
138 MVT::SimpleValueType getSetCCResultType(MVT VT) const;
138 EVT::SimpleValueType getSetCCResultType(EVT VT) const;
139139
140140 /// getBooleanContents - For targets without i1 registers, this gives the
141141 /// nature of the high-bits of boolean values held in types wider than i1.
151151
152152 /// getRegClassFor - Return the register class that should be used for the
153153 /// specified value type. This may only be called on legal types.
154 TargetRegisterClass *getRegClassFor(MVT VT) const {
154 TargetRegisterClass *getRegClassFor(EVT VT) const {
155155 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
156156 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
157157 assert(RC && "This value type is not natively supported!");
161161 /// isTypeLegal - Return true if the target has native support for the
162162 /// specified value type. This means that it has a register that directly
163163 /// holds it without promotions or expansions.
164 bool isTypeLegal(MVT VT) const {
164 bool isTypeLegal(EVT VT) const {
165165 assert(!VT.isSimple() ||
166166 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
167167 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
171171 /// ValueTypeActions - This is a bitvector that contains two bits for each
172172 /// value type, where the two bits correspond to the LegalizeAction enum.
173173 /// This can be queried with "getTypeAction(VT)".
174 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
175 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
174 /// dimension by (EVT::MAX_ALLOWED_VALUETYPE/32) * 2
175 uint32_t ValueTypeActions[(EVT::MAX_ALLOWED_VALUETYPE/32)*2];
176176 public:
177177 ValueTypeActionImpl() {
178178 ValueTypeActions[0] = ValueTypeActions[1] = 0;
185185 ValueTypeActions[3] = RHS.ValueTypeActions[3];
186186 }
187187
188 LegalizeAction getTypeAction(MVT VT) const {
188 LegalizeAction getTypeAction(EVT VT) const {
189189 if (VT.isExtended()) {
190190 if (VT.isVector()) {
191191 return VT.isPow2VectorType() ? Expand : Promote;
200200 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
201201 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
202202 }
203 void setTypeAction(MVT VT, LegalizeAction Action) {
203 void setTypeAction(EVT VT, LegalizeAction Action) {
204204 unsigned I = VT.getSimpleVT();
205205 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
206206 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
215215 /// it is already legal (return 'Legal') or we need to promote it to a larger
216216 /// type (return 'Promote'), or we need to expand it into multiple registers
217217 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
218 LegalizeAction getTypeAction(MVT VT) const {
218 LegalizeAction getTypeAction(EVT VT) const {
219219 return ValueTypeActions.getTypeAction(VT);
220220 }
221221
225225 /// than the largest integer register, this contains one step in the expansion
226226 /// to get to the smaller register. For illegal floating point types, this
227227 /// returns the integer type to transform to.
228 MVT getTypeToTransformTo(MVT VT) const {
228 EVT getTypeToTransformTo(EVT VT) const {
229229 if (VT.isSimple()) {
230230 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
231 MVT NVT = TransformToType[VT.getSimpleVT()];
231 EVT NVT = TransformToType[VT.getSimpleVT()];
232232 assert(getTypeAction(NVT) != Promote &&
233233 "Promote may not follow Expand or Promote");
234234 return NVT;
235235 }
236236
237237 if (VT.isVector()) {
238 MVT NVT = VT.getPow2VectorType();
238 EVT NVT = VT.getPow2VectorType();
239239 if (NVT == VT) {
240240 // Vector length is a power of 2 - split to half the size.
241241 unsigned NumElts = VT.getVectorNumElements();
242 MVT EltVT = VT.getVectorElementType();
243 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2);
242 EVT EltVT = VT.getVectorElementType();
243 return (NumElts == 1) ? EltVT : EVT::getVectorVT(EltVT, NumElts / 2);
244244 }
245245 // Promote to a power of two size, avoiding multi-step promotion.
246246 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
247247 } else if (VT.isInteger()) {
248 MVT NVT = VT.getRoundIntegerType();
248 EVT NVT = VT.getRoundIntegerType();
249249 if (NVT == VT)
250250 // Size is a power of two - expand to half the size.
251 return MVT::getIntegerVT(VT.getSizeInBits() / 2);
251 return EVT::getIntegerVT(VT.getSizeInBits() / 2);
252252 else
253253 // Promote to a power of two size, avoiding multi-step promotion.
254254 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
255255 }
256256 assert(0 && "Unsupported extended type!");
257 return MVT(MVT::Other); // Not reached
257 return EVT(EVT::Other); // Not reached
258258 }
259259
260260 /// getTypeToExpandTo - For types supported by the target, this is an
261261 /// identity function. For types that must be expanded (i.e. integer types
262262 /// that are larger than the largest integer register or illegal floating
263263 /// point types), this returns the largest legal type it will be expanded to.
264 MVT getTypeToExpandTo(MVT VT) const {
264 EVT getTypeToExpandTo(EVT VT) const {
265265 assert(!VT.isVector());
266266 while (true) {
267267 switch (getTypeAction(VT)) {
279279 }
280280
281281 /// getVectorTypeBreakdown - Vector types are broken down into some number of
282 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
283 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
284 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
282 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
283 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
284 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
285285 ///
286286 /// This method returns the number of registers needed, and the VT for each
287287 /// register. It also returns the VT and quantity of the intermediate values
288288 /// before they are promoted/expanded.
289289 ///
290 unsigned getVectorTypeBreakdown(MVT VT,
291 MVT &IntermediateVT,
290 unsigned getVectorTypeBreakdown(EVT VT,
291 EVT &IntermediateVT,
292292 unsigned &NumIntermediates,
293 MVT &RegisterVT) const;
293 EVT &RegisterVT) const;
294294
295295 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
296296 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
298298 /// information into the IntrinsicInfo that was passed to the function.
299299 typedef struct IntrinsicInfo {
300300 unsigned opc; // target opcode
301 MVT memVT; // memory VT
301 EVT memVT; // memory VT
302302 const Value* ptrVal; // value representing memory location
303303 int offset; // offset off of ptrVal
304304 unsigned align; // alignment
314314
315315 /// getWidenVectorType: given a vector type, returns the type to widen to
316316 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
317 /// If there is no vector type that we want to widen to, returns MVT::Other
317 /// If there is no vector type that we want to widen to, returns EVT::Other
318318 /// When and were to widen is target dependent based on the cost of
319319 /// scalarizing vs using the wider vector type.
320 virtual MVT getWidenVectorType(MVT VT) const;
320 virtual EVT getWidenVectorType(EVT VT) const;
321321
322322 typedef std::vector::const_iterator legal_fpimm_iterator;
323323 legal_fpimm_iterator legal_fpimm_begin() const {
332332 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
333333 /// are assumed to be legal.
334334 virtual bool isShuffleMaskLegal(const SmallVectorImpl &Mask,
335 MVT VT) const {
335 EVT VT) const {
336336 return true;
337337 }
338338
341341 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
342342 /// pool entry.
343343 virtual bool isVectorClearMaskLegal(const SmallVectorImpl &Mask,
344 MVT VT) const {
344 EVT VT) const {
345345 return false;
346346 }
347347
349349 /// it is legal, needs to be promoted to a larger size, needs to be
350350 /// expanded to some other code sequence, or the target has a custom expander
351351 /// for it.
352 LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
352 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
353353 if (VT.isExtended()) return Expand;
354354 assert(Op < array_lengthof(OpActions[0]) &&
355355 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 &&
363363 /// isOperationLegalOrCustom - Return true if the specified operation is
364364 /// legal on this target or can be made legal with custom lowering. This
365365 /// is used to help guide high-level lowering decisions.
366 bool isOperationLegalOrCustom(unsigned Op, MVT VT) const {
367 return (VT == MVT::Other || isTypeLegal(VT)) &&
366 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
367 return (VT == EVT::Other || isTypeLegal(VT)) &&
368368 (getOperationAction(Op, VT) == Legal ||
369369 getOperationAction(Op, VT) == Custom);
370370 }
371371
372372 /// isOperationLegal - Return true if the specified operation is legal on this
373373 /// target.
374 bool isOperationLegal(unsigned Op, MVT VT) const {
375 return (VT == MVT::Other || isTypeLegal(VT)) &&
374 bool isOperationLegal(unsigned Op, EVT VT) const {
375 return (VT == EVT::Other || isTypeLegal(VT)) &&
376376 getOperationAction(Op, VT) == Legal;
377377 }
378378
380380 /// either it is legal, needs to be promoted to a larger size, needs to be
381381 /// expanded to some other code sequence, or the target has a custom expander
382382 /// for it.
383 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const {
383 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
384384 assert(LType < array_lengthof(LoadExtActions) &&
385385 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
386386 "Table isn't big enough!");
389389
390390 /// isLoadExtLegal - Return true if the specified load with extension is legal
391391 /// on this target.
392 bool isLoadExtLegal(unsigned LType, MVT VT) const {
392 bool isLoadExtLegal(unsigned LType, EVT VT) const {
393393 return VT.isSimple() &&
394394 (getLoadExtAction(LType, VT) == Legal ||
395395 getLoadExtAction(LType, VT) == Custom);
399399 /// treated: either it is legal, needs to be promoted to a larger size, needs
400400 /// to be expanded to some other code sequence, or the target has a custom
401401 /// expander for it.
402 LegalizeAction getTruncStoreAction(MVT ValVT,
403 MVT MemVT) const {
402 LegalizeAction getTruncStoreAction(EVT ValVT,
403 EVT MemVT) const {
404404 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
405405 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
406406 "Table isn't big enough!");
410410
411411 /// isTruncStoreLegal - Return true if the specified store with truncation is
412412 /// legal on this target.
413 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
413 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
414414 return isTypeLegal(ValVT) && MemVT.isSimple() &&
415415 (getTruncStoreAction(ValVT, MemVT) == Legal ||
416416 getTruncStoreAction(ValVT, MemVT) == Custom);
421421 /// expanded to some other code sequence, or the target has a custom expander
422422 /// for it.
423423 LegalizeAction
424 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
424 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
425425 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
426 ((unsigned)VT.getSimpleVT()) < MVT::LAST_VALUETYPE &&
426 ((unsigned)VT.getSimpleVT()) < EVT::LAST_VALUETYPE &&
427427 "Table isn't big enough!");
428428 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode]));
429429 }
430430
431431 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
432432 /// on this target.
433 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
433 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
434434 return VT.isSimple() &&
435435 (getIndexedLoadAction(IdxMode, VT) == Legal ||
436436 getIndexedLoadAction(IdxMode, VT) == Custom);
441441 /// expanded to some other code sequence, or the target has a custom expander
442442 /// for it.
443443 LegalizeAction
444 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
444 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
445445 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
446 (unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
446 (unsigned)VT.getSimpleVT() < EVT::LAST_VALUETYPE &&
447447 "Table isn't big enough!");
448448 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode]));
449449 }
450450
451451 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
452452 /// on this target.
453 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
453 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
454454 return VT.isSimple() &&
455455 (getIndexedStoreAction(IdxMode, VT) == Legal ||
456456 getIndexedStoreAction(IdxMode, VT) == Custom);
461461 /// expanded to some other code sequence, or the target has a custom expander
462462 /// for it.
463463 LegalizeAction
464 getConvertAction(MVT FromVT, MVT ToVT) const {
464 getConvertAction(EVT FromVT, EVT ToVT) const {
465465 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
466466 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
467467 "Table isn't big enough!");
471471
472472 /// isConvertLegal - Return true if the specified conversion is legal
473473 /// on this target.
474 bool isConvertLegal(MVT FromVT, MVT ToVT) const {
474 bool isConvertLegal(EVT FromVT, EVT ToVT) const {
475475 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
476476 (getConvertAction(FromVT, ToVT) == Legal ||
477477 getConvertAction(FromVT, ToVT) == Custom);
481481 /// either it is legal, needs to be expanded to some other code sequence,
482482 /// or the target has a custom expander for it.
483483 LegalizeAction
484 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
484 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
485485 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
486486 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
487487 "Table isn't big enough!");
493493
494494 /// isCondCodeLegal - Return true if the specified condition code is legal
495495 /// on this target.
496 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
496 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
497497 return getCondCodeAction(CC, VT) == Legal ||
498498 getCondCodeAction(CC, VT) == Custom;
499499 }
501501
502502 /// getTypeToPromoteTo - If the action for this operation is to promote, this
503503 /// method returns the ValueType to promote to.
504 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
504 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
505505 assert(getOperationAction(Op, VT) == Promote &&
506506 "This operation isn't promoted!");
507507
508508 // See if this has an explicit type specified.
509 std::map,
510 MVT::SimpleValueType>::const_iterator PTTI =
509 std::map,
510 EVT::SimpleValueType>::const_iterator PTTI =
511511 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
512512 if (PTTI != PromoteToType.end()) return PTTI->second;
513513
514514 assert((VT.isInteger() || VT.isFloatingPoint()) &&
515515 "Cannot autopromote this type, add it with AddPromotedToType.");
516516
517 MVT NVT = VT;
517 EVT NVT = VT;
518518 do {
519 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
520 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
519 NVT = (EVT::SimpleValueType)(NVT.getSimpleVT()+1);
520 assert(NVT.isInteger() == VT.isInteger() && NVT != EVT::isVoid &&
521521 "Didn't find type to promote to!");
522522 } while (!isTypeLegal(NVT) ||
523523 getOperationAction(Op, NVT) == Promote);
524524 return NVT;
525525 }
526526
527 /// getValueType - Return the MVT corresponding to this LLVM type.
527 /// getValueType - Return the EVT corresponding to this LLVM type.
528528 /// This is fixed by the LLVM operations except for the pointer size. If
529 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
529 /// AllowUnknown is true, this will return EVT::Other for types with no EVT
530530 /// counterpart (e.g. structs), otherwise it will assert.
531 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
532 MVT VT = MVT::getMVT(Ty, AllowUnknown);
533 return VT == MVT::iPTR ? PointerTy : VT;
531 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
532 EVT VT = EVT::getEVT(Ty, AllowUnknown);
533 return VT == EVT::iPTR ? PointerTy : VT;
534534 }
535535
536536 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
540540
541541 /// getRegisterType - Return the type of registers that this ValueType will
542542 /// eventually require.
543 MVT getRegisterType(MVT VT) const {
543 EVT getRegisterType(EVT VT) const {
544544 if (VT.isSimple()) {
545545 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
546546 return RegisterTypeForVT[VT.getSimpleVT()];
547547 }
548548 if (VT.isVector()) {
549 MVT VT1, RegisterVT;
549 EVT VT1, RegisterVT;
550550 unsigned NumIntermediates;
551551 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
552552 return RegisterVT;
555555 return getRegisterType(getTypeToTransformTo(VT));
556556 }
557557 assert(0 && "Unsupported extended type!");
558 return MVT(MVT::Other); // Not reached
558 return EVT(EVT::Other); // Not reached
559559 }
560560
561561 /// getNumRegisters - Return the number of registers that this ValueType will
564564 /// into pieces. For types like i140, which are first promoted then expanded,
565565 /// it is the number of registers needed to hold all the bits of the original
566566 /// type. For an i140 on a 32 bit machine this means 5 registers.
567 unsigned getNumRegisters(MVT VT) const {
567 unsigned getNumRegisters(EVT VT) const {
568568 if (VT.isSimple()) {
569569 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
570570 return NumRegistersForVT[VT.getSimpleVT()];
571571 }
572572 if (VT.isVector()) {
573 MVT VT1, VT2;
573 EVT VT1, VT2;
574574 unsigned NumIntermediates;
575575 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
576576 }
586586 /// ShouldShrinkFPConstant - If true, then instruction selection should
587587 /// seek to shrink the FP constant of the specified type to a smaller type
588588 /// in order to save space and / or reduce runtime.
589 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
589 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
590590
591591 /// hasTargetDAGCombine - If true, the target has custom DAG combine
592592 /// transformations that it can perform for the specified node.
632632
633633 /// getOptimalMemOpType - Returns the target specific optimal type for load
634634 /// and store operations as a result of memset, memcpy, and memmove lowering.
635 /// It returns MVT::iAny if SelectionDAG should be responsible for
635 /// It returns EVT::iAny if SelectionDAG should be responsible for
636636 /// determining it.
637 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
637 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
638638 bool isSrcConst, bool isSrcStr,
639639 SelectionDAG &DAG) const {
640 return MVT::iAny;
640 return EVT::iAny;
641641 }
642642
643643 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
826826
827827 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
828828 /// and cc. If it is unable to simplify it, return a null SDValue.
829 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
829 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
830830 ISD::CondCode Cond, bool foldBooleans,
831831 DAGCombinerInfo &DCI, DebugLoc dl) const;
832832
868868
869869 /// setShiftAmountType - Describe the type that should be used for shift
870870 /// amounts. This type defaults to the pointer type.
871 void setShiftAmountType(MVT::SimpleValueType VT) { ShiftAmountTy = VT; }
871 void setShiftAmountType(EVT::SimpleValueType VT) { ShiftAmountTy = VT; }
872872
873873 /// setBooleanContents - Specify how the target extends the result of a
874874 /// boolean value from i1 to a wider type. See getBooleanContents.
931931 /// addRegisterClass - Add the specified register class as an available
932932 /// regclass for the specified value type. This indicates the selector can
933933 /// handle values of that class natively.
934 void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
934 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
935935 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
936936 AvailableRegClasses.push_back(std::make_pair(VT, RC));
937937 RegClassForVT[VT.getSimpleVT()] = RC;
943943
944944 /// setOperationAction - Indicate that the specified operation does not work
945945 /// with the specified type and indicate what to do about it.
946 void setOperationAction(unsigned Op, MVT::SimpleValueType VT,
946 void setOperationAction(unsigned Op, EVT::SimpleValueType VT,
947947 LegalizeAction Action) {
948948 unsigned I = (unsigned)VT;
949949 unsigned J = I & 31;
954954
955955 /// setLoadExtAction - Indicate that the specified load with extension does
956956 /// not work with the with specified type and indicate what to do about it.
957 void setLoadExtAction(unsigned ExtType, MVT::SimpleValueType VT,
957 void setLoadExtAction(unsigned ExtType, EVT::SimpleValueType VT,
958958 LegalizeAction Action) {
959959 assert((unsigned)VT < sizeof(LoadExtActions[0])*4 &&
960960 ExtType < array_lengthof(LoadExtActions) &&
965965
966966 /// setTruncStoreAction - Indicate that the specified truncating store does
967967 /// not work with the with specified type and indicate what to do about it.
968 void setTruncStoreAction(MVT::SimpleValueType ValVT,
969 MVT::SimpleValueType MemVT,
968 void setTruncStoreAction(EVT::SimpleValueType ValVT,
969 EVT::SimpleValueType MemVT,
970970 LegalizeAction Action) {
971971 assert((unsigned)ValVT < array_lengthof(TruncStoreActions) &&
972972 (unsigned)MemVT < sizeof(TruncStoreActions[0])*4 &&
979979 /// does not work with the with specified type and indicate what to do abort
980980 /// it. NOTE: All indexed mode loads are initialized to Expand in
981981 /// TargetLowering.cpp
982 void setIndexedLoadAction(unsigned IdxMode, MVT::SimpleValueType VT,
982 void setIndexedLoadAction(unsigned IdxMode, EVT::SimpleValueType VT,
983983 LegalizeAction Action) {
984 assert((unsigned)VT < MVT::LAST_VALUETYPE &&
984 assert((unsigned)VT < EVT::LAST_VALUETYPE &&
985985 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
986986 "Table isn't big enough!");
987987 IndexedModeActions[(unsigned)VT][0][IdxMode] = (uint8_t)Action;
991991 /// does not work with the with specified type and indicate what to do about
992992 /// it. NOTE: All indexed mode stores are initialized to Expand in
993993 /// TargetLowering.cpp
994 void setIndexedStoreAction(unsigned IdxMode, MVT::SimpleValueType VT,
994 void setIndexedStoreAction(unsigned IdxMode, EVT::SimpleValueType VT,
995995 LegalizeAction Action) {
996 assert((unsigned)VT < MVT::LAST_VALUETYPE &&
996 assert((unsigned)VT < EVT::LAST_VALUETYPE &&
997997 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
998998 "Table isn't big enough!");
999999 IndexedModeActions[(unsigned)VT][1][IdxMode] = (uint8_t)Action;
10011001
10021002 /// setConvertAction - Indicate that the specified conversion does or does
10031003 /// not work with the with specified type and indicate what to do about it.
1004 void setConvertAction(MVT::SimpleValueType FromVT, MVT::SimpleValueType ToVT,
1004 void setConvertAction(EVT::SimpleValueType FromVT, EVT::SimpleValueType ToVT,
10051005 LegalizeAction Action) {
10061006 assert((unsigned)FromVT < array_lengthof(ConvertActions) &&
10071007 (unsigned)ToVT < sizeof(ConvertActions[0])*4 &&
10121012
10131013 /// setCondCodeAction - Indicate that the specified condition code is or isn't
10141014 /// supported on the target and indicate what to do about it.
1015 void setCondCodeAction(ISD::CondCode CC, MVT::SimpleValueType VT,
1015 void setCondCodeAction(ISD::CondCode CC, EVT::SimpleValueType VT,
10161016 LegalizeAction Action) {
10171017 assert((unsigned)VT < sizeof(CondCodeActions[0])*4 &&
10181018 (unsigned)CC < array_lengthof(CondCodeActions) &&
10251025 /// promotion code defaults to trying a larger integer/fp until it can find
10261026 /// one that works. If that default is insufficient, this method can be used
10271027 /// by the target to override the default.
1028 void AddPromotedToType(unsigned Opc, MVT::SimpleValueType OrigVT,
1029 MVT::SimpleValueType DestVT) {
1028 void AddPromotedToType(unsigned Opc, EVT::SimpleValueType OrigVT,
1029 EVT::SimpleValueType DestVT) {
10301030 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
10311031 }
10321032
13411341 Value *CallOperandVal;
13421342
13431343 /// ConstraintVT - The ValueType for the operand value.
1344 MVT ConstraintVT;
1344 EVT ConstraintVT;
13451345
13461346 /// isMatchingInputConstraint - Return true of this is an input operand that
13471347 /// is a matching constraint like "4".
13541354 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
13551355 : InlineAsm::ConstraintInfo(info),
13561356 ConstraintType(TargetLowering::C_Unknown),
1357 CallOperandVal(0), ConstraintVT(MVT::Other) {
1357 CallOperandVal(0), ConstraintVT(EVT::Other) {
13581358 }
13591359 };
13601360
13781378 /// This should only be used for C_RegisterClass constraints.
13791379 virtual std::vector
13801380 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1381 MVT VT) const;
1381 EVT VT) const;
13821382
13831383 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
13841384 /// {edx}), return the register number and the register class for the
13921392 /// this returns a register number of 0 and a null register class pointer..
13931393 virtual std::pair
13941394 getRegForInlineAsmConstraint(const std::string &Constraint,
1395 MVT VT) const;
1395 EVT VT) const;
13961396
13971397 /// LowerXConstraint - try to replace an X constraint, which matches anything,
13981398 /// with another that has more specific requirements based on the type of the
13991399 /// corresponding operand. This returns null if there is no replacement to
14001400 /// make.
1401 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
1401 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
14021402
14031403 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14041404 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
14551455 return false;
14561456 }
14571457
1458 virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
1458 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
14591459 return false;
14601460 }
14611461
14711471 return false;
14721472 }
14731473
1474 virtual bool isZExtFree(MVT VT1, MVT VT2) const {
1474 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
14751475 return false;
14761476 }
14771477
14781478 /// isNarrowingProfitable - Return true if it's profitable to narrow
14791479 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
14801480 /// from i32 to i8 but not from i32 to i16.
1481 virtual bool isNarrowingProfitable(MVT VT1, MVT VT2) const {
1481 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
14821482 return false;
14831483 }
14841484
15261526
15271527 /// PointerTy - The type to use for pointers, usually i32 or i64.
15281528 ///
1529 MVT::SimpleValueType PointerTy;
1529 EVT::SimpleValueType PointerTy;
15301530
15311531 /// IsLittleEndian - True if this is a little endian target.
15321532 ///
15611561
15621562 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
15631563 /// PointerTy is.
1564 MVT::SimpleValueType ShiftAmountTy;
1564 EVT::SimpleValueType ShiftAmountTy;
15651565
15661566 /// BooleanContents - Information about the contents of the high-bits in
15671567 /// boolean values held in a type wider than i1. See getBooleanContents.
16071607
16081608 /// RegClassForVT - This indicates the default register class to use for
16091609 /// each ValueType the target supports natively.
1610 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1611 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1612 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1610 TargetRegisterClass *RegClassForVT[EVT::LAST_VALUETYPE];
1611 unsigned char NumRegistersForVT[EVT::LAST_VALUETYPE];
1612 EVT RegisterTypeForVT[EVT::LAST_VALUETYPE];
16131613
16141614 /// TransformToType - For any value types we are promoting or expanding, this
16151615 /// contains the value type that we are changing to. For Expanded types, this
16161616 /// contains one step of the expand (e.g. i64 -> i32), even if there are
16171617 /// multiple steps required (e.g. i64 -> i16). For types natively supported
16181618 /// by the system, this holds the same type (e.g. i32 -> i32).
1619 MVT TransformToType[MVT::LAST_VALUETYPE];
1619 EVT TransformToType[EVT::LAST_VALUETYPE];
16201620
16211621 /// OpActions - For each operation and each value type, keep a LegalizeAction
16221622 /// that indicates how instruction selection should deal with the operation.
16241624 /// operations that are not should be described. Note that operations on
16251625 /// non-legal value types are not described here.
16261626 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1627 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1628 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
1627 /// the EVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1628 uint64_t OpActions[EVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
16291629
16301630 /// LoadExtActions - For each load of load extension type and each value type,
16311631 /// keep a LegalizeAction that indicates how instruction selection should deal
16341634
16351635 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
16361636 /// indicates how instruction selection should deal with the store.
1637 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1637 uint64_t TruncStoreActions[EVT::LAST_VALUETYPE];
16381638
16391639 /// IndexedModeActions - For each indexed mode and each value type,
16401640 /// keep a pair of LegalizeAction that indicates how instruction
16421642 /// dimension is now the value_type for the reference. The second
16431643 /// dimension is the load [0] vs. store[1]. The third dimension
16441644 /// represents the various modes for load store.
1645 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1645 uint8_t IndexedModeActions[EVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
16461646
16471647 /// ConvertActions - For each conversion from source type to destination type,
16481648 /// keep a LegalizeAction that indicates how instruction selection should
16491649 /// deal with the conversion.
16501650 /// Currently, this is used only for floating->floating conversions
16511651 /// (FP_EXTEND and FP_ROUND).
1652 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1652 uint64_t ConvertActions[EVT::LAST_VALUETYPE];
16531653
16541654 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
16551655 /// LegalizeAction that indicates how instruction selection should
16601660
16611661 std::vector LegalFPImmediates;
16621662
1663 std::vectorMVT, TargetRegisterClass*> > AvailableRegClasses;
1663 std::vectorEVT, TargetRegisterClass*> > AvailableRegClasses;
16641664
16651665 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
16661666 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
16741674 ///
16751675 /// Targets add entries to this map with AddPromotedToType(..), clients access
16761676 /// this with getTypeToPromoteTo(..).
1677 std::mapMVT::SimpleValueType>, MVT::SimpleValueType>
1677 std::mapEVT::SimpleValueType>, EVT::SimpleValueType>
16781678 PromoteToType;
16791679
16801680 /// LibcallRoutineNames - Stores the name each libcall.
5252 typedef const unsigned* iterator;
5353 typedef const unsigned* const_iterator;
5454
55 typedef const MVT* vt_iterator;
55 typedef const EVT* vt_iterator;
5656 typedef const TargetRegisterClass* const * sc_iterator;
5757 private:
5858 unsigned ID;
6969 public:
7070 TargetRegisterClass(unsigned id,
7171 const char *name,
72 const MVT *vts,
72 const EVT *vts,
7373 const TargetRegisterClass * const *subcs,
7474 const TargetRegisterClass * const *supcs,
7575 const TargetRegisterClass * const *subregcs,
116116
117117 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
118118 ///
119 bool hasType(MVT vt) const {
120 for(int i = 0; VTs[i] != MVT::Other; ++i)
119 bool hasType(EVT vt) const {
120 for(int i = 0; VTs[i] != EVT::Other; ++i)
121121 if (VTs[i] == vt)
122122 return true;
123123 return false;
131131
132132 vt_iterator vt_end() const {
133133 vt_iterator I = VTs;
134 while (*I != MVT::Other) ++I;
134 while (*I != EVT::Other) ++I;
135135 return I;
136136 }
137137
317317 }
318318
319319 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
320 /// register of the given type. If type is MVT::Other, then just return any
320 /// register of the given type. If type is EVT::Other, then just return any
321321 /// register class the register belongs to.
322322 virtual const TargetRegisterClass *
323 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
323 getPhysicalRegisterRegClass(unsigned Reg, EVT VT = EVT::Other) const;
324324
325325 /// getAllocatableSet - Returns a bitset indexed by register number
326326 /// indicating if a register is allocatable or not. If a register class is
511511 }]>;
512512
513513 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
514 return cast(N)->getMemoryVT() == MVT::i1;
514 return cast(N)->getMemoryVT() == EVT::i1;
515515 }]>;
516516 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
517 return cast(N)->getMemoryVT() == MVT::i8;
517 return cast(N)->getMemoryVT() == EVT::i8;
518518 }]>;
519519 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
520 return cast(N)->getMemoryVT() == MVT::i16;
520 return cast(N)->getMemoryVT() == EVT::i16;
521521 }]>;
522522 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
523 return cast(N)->getMemoryVT() == MVT::i32;
523 return cast(N)->getMemoryVT() == EVT::i32;
524524 }]>;
525525 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
526 return cast(N)->getMemoryVT() == MVT::f32;
526 return cast(N)->getMemoryVT() == EVT::f32;
527527 }]>;
528528 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
529 return cast(N)->getMemoryVT() == MVT::f64;
529 return cast(N)->getMemoryVT() == EVT::f64;
530530 }]>;
531531
532532 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
533 return cast(N)->getMemoryVT() == MVT::i1;
533 return cast(N)->getMemoryVT() == EVT::i1;
534534 }]>;
535535 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
536 return cast(N)->getMemoryVT() == MVT::i8;
536 return cast(N)->getMemoryVT() == EVT::i8;
537537 }]>;
538538 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
539 return cast(N)->getMemoryVT() == MVT::i16;
539 return cast(N)->getMemoryVT() == EVT::i16;
540540 }]>;
541541 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
542 return cast(N)->getMemoryVT() == MVT::i32;
542 return cast(N)->getMemoryVT() == EVT::i32;
543543 }]>;
544544
545545 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
546 return cast(N)->getMemoryVT() == MVT::i1;
546 return cast(N)->getMemoryVT() == EVT::i1;
547547 }]>;
548548 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
549 return cast(N)->getMemoryVT() == MVT::i8;
549 return cast(N)->getMemoryVT() == EVT::i8;
550550 }]>;
551551 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
552 return cast(N)->getMemoryVT() == MVT::i16;
552 return cast(N)->getMemoryVT() == EVT::i16;
553553 }]>;
554554 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
555 return cast(N)->getMemoryVT() == MVT::i32;
555 return cast(N)->getMemoryVT() == EVT::i32;
556556 }]>;
557557
558558 // store fragments.
572572 }]>;
573573 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
574574 (truncstore node:$val, node:$ptr), [{
575 return cast(N)->getMemoryVT() == MVT::i8;
575 return cast(N)->getMemoryVT() == EVT::i8;
576576 }]>;
577577 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
578578 (truncstore node:$val, node:$ptr), [{
579 return cast(N)->getMemoryVT() == MVT::i16;
579 return cast(N)->getMemoryVT() == EVT::i16;
580580 }]>;
581581 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
582582 (truncstore node:$val, node:$ptr), [{
583 return cast(N)->getMemoryVT() == MVT::i32;
583 return cast(N)->getMemoryVT() == EVT::i32;
584584 }]>;
585585 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
586586 (truncstore node:$val, node:$ptr), [{
587 return cast(N)->getMemoryVT() == MVT::f32;
587 return cast(N)->getMemoryVT() == EVT::f32;
588588 }]>;
589589 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
590590 (truncstore node:$val, node:$ptr), [{
591 return cast(N)->getMemoryVT() == MVT::f64;
591 return cast(N)->getMemoryVT() == EVT::f64;
592592 }]>;
593593
594594 // indexed store fragments.
614614 }]>;
615615 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
616616 (pre_truncst node:$val, node:$base, node:$offset), [{
617 return cast(N)->getMemoryVT() == MVT::i1;
617 return cast(N)->getMemoryVT() == EVT::i1;
618618 }]>;
619619 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
620620 (pre_truncst node:$val, node:$base, node:$offset), [{
621 return cast(N)->getMemoryVT() == MVT::i8;
621 return cast(N)->getMemoryVT() == EVT::i8;
622622 }]>;
623623 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
624624 (pre_truncst node:$val, node:$base, node:$offset), [{
625 return cast(N)->getMemoryVT() == MVT::i16;
625 return cast(N)->getMemoryVT() == EVT::i16;
626626 }]>;
627627 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
628628 (pre_truncst node:$val, node:$base, node:$offset), [{
629 return cast(N)->getMemoryVT() == MVT::i32;
629 return cast(N)->getMemoryVT() == EVT::i32;
630630 }]>;
631631 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
632632 (pre_truncst node:$val, node:$base, node:$offset), [{
633 return cast(N)->getMemoryVT() == MVT::f32;
633 return cast(N)->getMemoryVT() == EVT::f32;
634634 }]>;
635635
636636 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
646646 }]>;
647647 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
648648 (post_truncst node:$val, node:$base, node:$offset), [{
649 return cast(N)->getMemoryVT() == MVT::i1;
649 return cast(N)->getMemoryVT() == EVT::i1;
650650 }]>;
651651 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
652652 (post_truncst node:$val, node:$base, node:$offset), [{
653 return cast(N)->getMemoryVT() == MVT::i8;
653 return cast(N)->getMemoryVT() == EVT::i8;
654654 }]>;
655655 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
656656 (post_truncst node:$val, node:$base, node:$offset), [{
657 return cast(N)->getMemoryVT() == MVT::i16;
657 return cast(N)->getMemoryVT() == EVT::i16;
658658 }]>;
659659 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
660660 (post_truncst node:$val, node:$base, node:$offset), [{
661 return cast(N)->getMemoryVT() == MVT::i32;
661 return cast(N)->getMemoryVT() == EVT::i32;
662662 }]>;
663663 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
664664 (post_truncst node:$val, node:$base, node:$offset), [{
665 return cast(N)->getMemoryVT() == MVT::f32;
665 return cast(N)->getMemoryVT() == EVT::f32;
666666 }]>;
667667
668668 // setcc convenience fragments.
710710 def atomic_cmp_swap_8 :
711711 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
712712 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
713 return cast(N)->getMemoryVT() == MVT::i8;
713 return cast(N)->getMemoryVT() == EVT::i8;
714714 }]>;
715715 def atomic_cmp_swap_16 :
716716 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
717717 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
718 return cast(N)->getMemoryVT() == MVT::i16;
718 return cast(N)->getMemoryVT() == EVT::i16;
719719 }]>;
720720 def atomic_cmp_swap_32 :
721721 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
722722 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
723 return cast(N)->getMemoryVT() == MVT::i32;
723 return cast(N)->getMemoryVT() == EVT::i32;
724724 }]>;
725725 def atomic_cmp_swap_64 :
726726 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
727727 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
728 return cast(N)->getMemoryVT() == MVT::i64;
728 return cast(N)->getMemoryVT() == EVT::i64;
729729 }]>;
730730
731731 multiclass binary_atomic_op {
732732 def _8 : PatFrag<(ops node:$ptr, node:$val),
733733 (atomic_op node:$ptr, node:$val), [{
734 return cast(N)->getMemoryVT() == MVT::i8;
734 return cast(N)->getMemoryVT() == EVT::i8;
735735 }]>;
736736 def _16 : PatFrag<(ops node:$ptr, node:$val),
737737 (atomic_op node:$ptr, node:$val), [{
738 return cast(N)->getMemoryVT() == MVT::i16;
738 return cast(N)->getMemoryVT() == EVT::i16;
739739 }]>;
740740 def _32 : PatFrag<(ops node:$ptr, node:$val),
741741 (atomic_op node:$ptr, node:$val), [{
742 return cast(N)->getMemoryVT() == MVT::i32;
742 return cast(N)->getMemoryVT() == EVT::i32;
743743 }]>;
744744 def _64 : PatFrag<(ops node:$ptr, node:$val),
745745 (atomic_op node:$ptr, node:$val), [{
746 return cast(N)->getMemoryVT() == MVT::i64;
746 return cast(N)->getMemoryVT() == EVT::i64;
747747 }]>;
748748 }
749749
3232 // HandleByVal - Allocate a stack slot large enough to pass an argument by
3333 // value. The size and alignment information of the argument is encoded in its
3434 // parameter attribute.
35 void CCState::HandleByVal(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
35 void CCState::HandleByVal(unsigned ValNo, EVT ValVT,
36 EVT LocVT, CCValAssign::LocInfo LocInfo,
3737 int MinSize, int MinAlign,
3838 ISD::ArgFlagsTy ArgFlags) {
3939 unsigned Align = ArgFlags.getByValAlign();
6464 unsigned NumArgs = Ins.size();
6565
6666 for (unsigned i = 0; i != NumArgs; ++i) {
67 MVT ArgVT = Ins[i].VT;
67 EVT ArgVT = Ins[i].VT;
6868 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
6969 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
7070 #ifndef NDEBUG
7171 cerr << "Formal argument #" << i << " has unhandled type "
72 << ArgVT.getMVTString();
72 << ArgVT.getEVTString();
7373 #endif
7474 llvm_unreachable(0);
7575 }
8282 CCAssignFn Fn) {
8383 // Determine which register each value should be copied into.
8484 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
85 MVT VT = Outs[i].Val.getValueType();
85 EVT VT = Outs[i].Val.getValueType();
8686 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
8787 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
8888 #ifndef NDEBUG
8989 cerr << "Return operand #" << i << " has unhandled type "
90 << VT.getMVTString();
90 << VT.getEVTString();
9191 #endif
9292 llvm_unreachable(0);
9393 }
101101 CCAssignFn Fn) {
102102 unsigned NumOps = Outs.size();
103103 for (unsigned i = 0; i != NumOps; ++i) {
104 MVT ArgVT = Outs[i].Val.getValueType();
104 EVT ArgVT = Outs[i].Val.getValueType();
105105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
106106 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
107107 #ifndef NDEBUG
108108 cerr << "Call operand #" << i << " has unhandled type "
109 << ArgVT.getMVTString();
109 << ArgVT.getEVTString();
110110 #endif
111111 llvm_unreachable(0);
112112 }
115115
116116 /// AnalyzeCallOperands - Same as above except it takes vectors of types
117117 /// and argument flags.
118 void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
118 void CCState::AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs,
119119 SmallVectorImpl &Flags,
120120 CCAssignFn Fn) {
121121 unsigned NumOps = ArgVTs.size();
122122 for (unsigned i = 0; i != NumOps; ++i) {
123 MVT ArgVT = ArgVTs[i];
123 EVT ArgVT = ArgVTs[i];
124124 ISD::ArgFlagsTy ArgFlags = Flags[i];
125125 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
126126 #ifndef NDEBUG
127127 cerr << "Call operand #" << i << " has unhandled type "
128 << ArgVT.getMVTString();
128 << ArgVT.getEVTString();
129129 #endif
130130 llvm_unreachable(0);
131131 }
137137 void CCState::AnalyzeCallResult(const SmallVectorImpl &Ins,
138138 CCAssignFn Fn) {
139139 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
140 MVT VT = Ins[i].VT;
140 EVT VT = Ins[i].VT;
141141 ISD::ArgFlagsTy Flags = Ins[i].Flags;
142142 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) {
143143 #ifndef NDEBUG
144144 cerr << "Call result #" << i << " has unhandled type "
145 << VT.getMVTString();
145 << VT.getEVTString();
146146 #endif
147147 llvm_unreachable(0);
148148 }
151151
152152 /// AnalyzeCallResult - Same as above except it's specialized for calls which
153153 /// produce a single value.
154 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) {
154 void CCState::AnalyzeCallResult(EVT VT, CCAssignFn Fn) {
155155 if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
156156 #ifndef NDEBUG
157157 cerr << "Call result has unhandled type "
158 << VT.getMVTString();
158 << VT.getEVTString();
159159 #endif
160160 llvm_unreachable(0);
161161 }
214214 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
215215 SDValue N3, ISD::CondCode CC,
216216 bool NotExtCompare = false);
217 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
217 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
218218 DebugLoc DL, bool foldBooleans = true);
219219 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
220220 unsigned HiOp);
221 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
222 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
221 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
222 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
223223 SDValue BuildSDIV(SDNode *N);
224224 SDValue BuildUDIV(SDNode *N);
225225 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
252252
253253 /// getShiftAmountTy - Returns a type large enough to hold any valid
254254 /// shift amount - before type legalization these can be huge.
255 MVT getShiftAmountTy() {
255 EVT getShiftAmountTy() {
256256 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
257257 }
258258
330330 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
331331 unsigned Depth = 0) {
332332 // No compile time optimizations on this type.
333 if (Op.getValueType() == MVT::ppcf128)
333 if (Op.getValueType() == EVT::ppcf128)
334334 return 0;
335335
336336 // fneg is removable even if it has multiple uses.
496496
497497 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
498498 SDValue N0, SDValue N1) {
499 MVT VT = N0.getValueType();
499 EVT VT = N0.getValueType();
500500 if (N0.getOpcode() == Opc && isa(N0.getOperand(1))) {
501501 if (isa(N1)) {
502502 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
832832 /// otherwise return a null sd operand.
833833 static SDValue getInputChainForNode(SDNode *N) {
834834 if (unsigned NumOps = N->getNumOperands()) {
835 if (N->getOperand(0).getValueType() == MVT::Other)
835 if (N->getOperand(0).getValueType() == EVT::Other)
836836 return N->getOperand(0);
837 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
837 else if (N->getOperand(NumOps-1).getValueType() == EVT::Other)
838838 return N->getOperand(NumOps-1);
839839 for (unsigned i = 1; i < NumOps-1; ++i)
840 if (N->getOperand(i).getValueType() == MVT::Other)
840 if (N->getOperand(i).getValueType() == EVT::Other)
841841 return N->getOperand(i);
842842 }
843843 return SDValue();
910910 } else {
911911 // New and improved token factor.
912912 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
913 MVT::Other, &Ops[0], Ops.size());
913 EVT::Other, &Ops[0], Ops.size());
914914 }
915915
916916 // Don't add users to work list.
934934 static
935935 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
936936 SelectionDAG &DAG) {
937 MVT VT = N0.getValueType();
937 EVT VT = N0.getValueType();
938938 SDValue N00 = N0.getOperand(0);
939939 SDValue N01 = N0.getOperand(1);
940940 ConstantSDNode *N01C = dyn_cast(N01);
958958 SDValue N1 = N->getOperand(1);
959959 ConstantSDNode *N0C = dyn_cast(N0);
960960 ConstantSDNode *N1C = dyn_cast(N1);
961 MVT VT = N0.getValueType();
961 EVT VT = N0.getValueType();
962962
963963 // fold vector ops
964964 if (VT.isVector()) {
10811081 SDValue N1 = N->getOperand(1);
10821082 ConstantSDNode *N0C = dyn_cast(N0);
10831083 ConstantSDNode *N1C = dyn_cast(N1);
1084 MVT VT = N0.getValueType();
1084 EVT VT = N0.getValueType();
10851085
10861086 // If the flag result is dead, turn this into an ADD.
10871087 if (N->hasNUsesOfValue(0, 1))
10881088 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
10891089 DAG.getNode(ISD::CARRY_FALSE,
1090 N->getDebugLoc(), MVT::Flag));
1090 N->getDebugLoc(), EVT::Flag));
10911091
10921092 // canonicalize constant to RHS.
10931093 if (N0C && !N1C)
10961096 // fold (addc x, 0) -> x + no carry out
10971097 if (N1C && N1C->isNullValue())
10981098 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1099 N->getDebugLoc(), MVT::Flag));
1099 N->getDebugLoc(), EVT::Flag));
11001100
11011101 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
11021102 APInt LHSZero, LHSOne;
11131113 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
11141114 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
11151115 DAG.getNode(ISD::CARRY_FALSE,
1116 N->getDebugLoc(), MVT::Flag));
1116 N->getDebugLoc(), EVT::Flag));
11171117 }
11181118
11191119 return SDValue();
11431143 SDValue N1 = N->getOperand(1);
11441144 ConstantSDNode *N0C = dyn_cast(N0.getNode());
11451145 ConstantSDNode *N1C = dyn_cast(N1.getNode());
1146 MVT VT = N0.getValueType();
1146 EVT VT = N0.getValueType();
11471147
11481148 // fold vector ops
11491149 if (VT.isVector()) {
12161216 SDValue N1 = N->getOperand(1);
12171217 ConstantSDNode *N0C = dyn_cast(N0);
12181218 ConstantSDNode *N1C = dyn_cast(N1);
1219 MVT VT = N0.getValueType();
1219 EVT VT = N0.getValueType();
12201220
12211221 // fold vector ops
12221222 if (VT.isVector()) {
13091309 SDValue N1 = N->getOperand(1);
13101310 ConstantSDNode *N0C = dyn_cast(N0.getNode());
13111311 ConstantSDNode *N1C = dyn_cast(N1.getNode());
1312 MVT VT = N->getValueType(0);
1312 EVT VT = N->getValueType(0);
13131313
13141314 // fold vector ops
13151315 if (VT.isVector()) {
13961396 SDValue N1 = N->getOperand(1);
13971397 ConstantSDNode *N0C = dyn_cast(N0.getNode());
13981398 ConstantSDNode *N1C = dyn_cast(N1.getNode());
1399 MVT VT = N->getValueType(0);
1399 EVT VT = N->getValueType(0);
14001400
14011401 // fold vector ops
14021402 if (VT.isVector()) {
14161416 if (N1.getOpcode() == ISD::SHL) {
14171417 if (ConstantSDNode *SHC = dyn_cast(N1.getOperand(0))) {
14181418 if (SHC->getAPIntValue().isPowerOf2()) {
1419 MVT ADDVT = N1.getOperand(1).getValueType();
1419 EVT ADDVT = N1.getOperand(1).getValueType();
14201420 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
14211421 N1.getOperand(1),
14221422 DAG.getConstant(SHC->getAPIntValue()
14481448 SDValue N1 = N->getOperand(1);
14491449 ConstantSDNode *N0C = dyn_cast(N0);
14501450 ConstantSDNode *N1C = dyn_cast(N1);
1451 MVT VT = N->getValueType(0);
1451 EVT VT = N->getValueType(0);
14521452
14531453 // fold (srem c1, c2) -> c1%c2
14541454 if (N0C && N1C && !N1C->isNullValue())
14901490 SDValue N1 = N->getOperand(1);
14911491 ConstantSDNode *N0C = dyn_cast(N0);
14921492 ConstantSDNode *N1C = dyn_cast(N1);
1493 MVT VT = N->getValueType(0);
1493 EVT VT = N->getValueType(0);
14941494
14951495 // fold (urem c1, c2) -> c1%c2
14961496 if (N0C && N1C && !N1C->isNullValue())
15421542 SDValue N0 = N->getOperand(0);
15431543 SDValue N1 = N->getOperand(1);
15441544 ConstantSDNode *N1C = dyn_cast(N1);
1545 MVT VT = N->getValueType(0);
1545 EVT VT = N->getValueType(0);
15461546
15471547 // fold (mulhs x, 0) -> 0
15481548 if (N1C && N1C->isNullValue())
15631563 SDValue N0 = N->getOperand(0);
15641564 SDValue N1 = N->getOperand(1);
15651565 ConstantSDNode *N1C = dyn_cast(N1);
1566 MVT VT = N->getValueType(0);
1566 EVT VT = N->getValueType(0);
15671567
15681568 // fold (mulhu x, 0) -> 0
15691569 if (N1C && N1C->isNullValue())
16661666 /// two operands of the same opcode, try to simplify it.
16671667 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
16681668 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1669 MVT VT = N0.getValueType();
1669 EVT VT = N0.getValueType();
16701670 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
16711671
16721672 // For each of OP in AND/OR/XOR:
17121712 SDValue LL, LR, RL, RR, CC0, CC1;
17131713 ConstantSDNode *N0C = dyn_cast(N0);
17141714 ConstantSDNode *N1C = dyn_cast(N1);
1715 MVT VT = N1.getValueType();
1715 EVT VT = N1.getValueType();
17161716 unsigned BitWidth = VT.getSizeInBits();
17171717
17181718 // fold vector ops
18231823 // fold (zext_inreg (extload x)) -> (zextload x)
18241824 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
18251825 LoadSDNode *LN0 = cast(N0);
1826 MVT EVT = LN0->getMemoryVT();
1826 EVT EVT = LN0->getMemoryVT();
18271827 // If we zero all the possible extended bits, then we can turn this into
18281828 // a zextload if we are running before legalize or the operation is legal.
18291829 unsigned BitWidth = N1.getValueSizeInBits();
18451845 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
18461846 N0.hasOneUse()) {
18471847 LoadSDNode *LN0 = cast(N0);
1848 MVT EVT = LN0->getMemoryVT();
1848 EVT EVT = LN0->getMemoryVT();
18491849 // If we zero all the possible extended bits, then we can turn this into
18501850 // a zextload if we are running before legalize or the operation is legal.
18511851 unsigned BitWidth = N1.getValueSizeInBits();
18721872 LN0->isUnindexed() && N0.hasOneUse() &&
18731873 // Do not change the width of a volatile load.
18741874 !LN0->isVolatile()) {
1875 MVT EVT = MVT::Other;
1875 EVT ExtVT = EVT::Other;
18761876 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
18771877 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1878 EVT = MVT::getIntegerVT(ActiveBits);
1879
1880 MVT LoadedVT = LN0->getMemoryVT();
1878 ExtVT = EVT::getIntegerVT(ActiveBits);
1879
1880 EVT LoadedVT = LN0->getMemoryVT();
18811881
18821882 // Do not generate loads of non-round integer types since these can
18831883 // be expensive (and would be wrong if the type is not byte sized).
1884 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
1885 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1886 MVT PtrType = N0.getOperand(1).getValueType();
1884 if (ExtVT != EVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
1885 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
1886 EVT PtrType = N0.getOperand(1).getValueType();
18871887
18881888 // For big endian targets, we need to add an offset to the pointer to
18891889 // load the correct bytes. For little endian systems, we merely need to
18901890 // read fewer bytes from the same pointer.
18911891 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1892 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
1892 unsigned EVTStoreBytes = ExtVT.getStoreSizeInBits()/8;
18931893 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
18941894 unsigned Alignment = LN0->getAlignment();
18951895 SDValue NewPtr = LN0->getBasePtr();
19041904 SDValue Load =
19051905 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(),
19061906 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(),
1907 EVT, LN0->isVolatile(), Alignment);
1907 ExtVT, LN0->isVolatile(), Alignment);
19081908 AddToWorkList(N);
19091909 CombineTo(N0.getNode(), Load, Load.getValue(1));
19101910 return SDValue(N, 0); // Return N so it doesn't get rechecked!
19211921 SDValue LL, LR, RL, RR, CC0, CC1;
19221922 ConstantSDNode *N0C = dyn_cast(N0);
19231923 ConstantSDNode *N1C = dyn_cast(N1);
1924 MVT VT = N1.getValueType();
1924 EVT VT = N1.getValueType();
19251925
19261926 // fold vector ops
19271927 if (VT.isVector()) {
20612061 // a rot[lr].
20622062 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
20632063 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2064 MVT VT = LHS.getValueType();
2064 EVT VT = LHS.getValueType();
20652065 if (!TLI.isTypeLegal(VT)) return 0;
20662066
20672067 // The target must have at least one rotate flavor.
22222222 SDValue LHS, RHS, CC;
22232223 ConstantSDNode *N0C = dyn_cast(N0);
22242224 ConstantSDNode *N1C = dyn_cast(N1);
2225 MVT VT = N0.getValueType();
2225 EVT VT = N0.getValueType();
22262226
22272227 // fold vector ops
22282228 if (VT.isVector()) {
22832283 }
22842284
22852285 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2286 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2286 if (N1C && N1C->getAPIntValue() == 1 && VT == EVT::i1 &&
22872287 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
22882288 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
22892289 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
23902390 !isa(BinOpLHSVal->getOperand(1)))
23912391 return SDValue();
23922392
2393 MVT VT = N->getValueType(0);
2393 EVT VT = N->getValueType(0);
23942394
23952395 // If this is a signed shift right, and the high bit is modified by the
23962396 // logical operation, do not perform the transformation. The highBitSet
24202420 SDValue N1 = N->getOperand(1);
24212421 ConstantSDNode *N0C = dyn_cast(N0);
24222422 ConstantSDNode *N1C = dyn_cast(N1);
2423 MVT VT = N0.getValueType();
2423 EVT VT = N0.getValueType();
24242424 unsigned OpSizeInBits = VT.getSizeInBits();
24252425
24262426 // fold (shl c1, c2) -> c1<
24452445 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
24462446 SDValue N101 = N1.getOperand(0).getOperand(1);
24472447 if (ConstantSDNode *N101C = dyn_cast(N101)) {
2448 MVT TruncVT = N1.getValueType();
2448 EVT TruncVT = N1.getValueType();
24492449 SDValue N100 = N1.getOperand(0).getOperand(0);
24502450 APInt TruncC = N101C->getAPIntValue();
24512451 TruncC.trunc(TruncVT.getSizeInBits());
25122512 SDValue N1 = N->getOperand(1);
25132513 ConstantSDNode *N0C = dyn_cast(N0);
25142514 ConstantSDNode *N1C = dyn_cast(N1);
2515 MVT VT = N0.getValueType();
2515 EVT VT = N0.getValueType();
25162516
25172517 // fold (sra c1, c2) -> (sra c1, c2)
25182518 if (N0C && N1C)
25332533 // sext_inreg.
25342534 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
25352535 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
2536 MVT EVT = MVT::getIntegerVT(LowBits);
2536 EVT EVT = EVT::getIntegerVT(LowBits);
25372537 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
25382538 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
25392539 N0.getOperand(0), DAG.getValueType(EVT));
25602560 if (N01C && N1C) {
25612561 // Determine what the truncate's result bitsize and type would be.
25622562 unsigned VTValSize = VT.getSizeInBits();
2563 MVT TruncVT =
2564 MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
2563 EVT TruncVT =
2564 EVT::getIntegerVT(VTValSize - N1C->getZExtValue());
25652565 // Determine the residual right-shift amount.
25662566 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
25672567
25912591 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
25922592 SDValue N101 = N1.getOperand(0).getOperand(1);
25932593 if (ConstantSDNode *N101C = dyn_cast(N101)) {
2594 MVT TruncVT = N1.getValueType();
2594 EVT TruncVT = N1.getValueType();
25952595 SDValue N100 = N1.getOperand(0).getOperand(0);
25962596 APInt TruncC = N101C->getAPIntValue();
25972597 TruncC.trunc(TruncVT.getSizeInBits());
26222622 SDValue N1 = N->getOperand(1);
26232623 ConstantSDNode *N0C = dyn_cast(N0);
26242624 ConstantSDNode *N1C = dyn_cast(N1);
2625 MVT VT = N0.getValueType();
2625 EVT VT = N0.getValueType();
26262626 unsigned OpSizeInBits = VT.getSizeInBits();
26272627
26282628 // fold (srl c1, c2) -> c1 >>u c2
26562656 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
26572657 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
26582658 // Shifting in all undef bits?
2659 MVT SmallVT = N0.getOperand(0).getValueType();
2659 EVT SmallVT = N0.getOperand(0).getValueType();
26602660 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
26612661 return DAG.getUNDEF(VT);
26622662
27152715 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
27162716 SDValue N101 = N1.getOperand(0).getOperand(1);
27172717 if (ConstantSDNode *N101C = dyn_cast(N101)) {
2718 MVT TruncVT = N1.getValueType();
2718 EVT TruncVT = N1.getValueType();
27192719 SDValue N100 = N1.getOperand(0).getOperand(0);
27202720 APInt TruncC = N101C->getAPIntValue();
27212721 TruncC.trunc(TruncVT.getSizeInBits());
27392739
27402740 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
27412741 SDValue N0 = N->getOperand(0);
2742 MVT VT = N->getValueType(0);
2742 EVT VT = N->getValueType(0);
27432743
27442744 // fold (ctlz c1) -> c2
27452745 if (isa(N0))
27492749
27502750 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
27512751 SDValue N0 = N->getOperand(0);
2752 MVT VT = N->getValueType(0);
2752 EVT VT = N->getValueType(0);
27532753
27542754 // fold (cttz c1) -> c2
27552755 if (isa(N0))
27592759
27602760 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
27612761 SDValue N0 = N->getOperand(0);
2762 MVT VT = N->getValueType(0);
2762 EVT VT = N->getValueType(0);
27632763
27642764 // fold (ctpop c1) -> c2
27652765 if (isa(N0))
27742774 ConstantSDNode *N0C = dyn_cast(N0);
27752775 ConstantSDNode *N1C = dyn_cast(N1);
27762776 ConstantSDNode *N2C = dyn_cast(N2);
2777 MVT VT = N->getValueType(0);
2778 MVT VT0 = N0.getValueType();
2777 EVT VT = N->getValueType(0);
2778 EVT VT0 = N0.getValueType();
27792779
27802780 // fold (select C, X, X) -> X
27812781 if (N1 == N2)
27872787 if (N0C && N0C->isNullValue())
27882788 return N2;
27892789 // fold (select C, 1, X) -> (or C, X)
2790 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2790 if (VT == EVT::i1 && N1C && N1C->getAPIntValue() == 1)
27912791 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
27922792 // fold (select C, 0, 1) -> (xor C, 1)
27932793 if (VT.isInteger() &&
2794 (VT0 == MVT::i1 ||
2794 (VT0 == EVT::i1 ||
27952795 (VT0.isInteger() &&
27962796 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
27972797 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
28072807 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
28082808 }
28092809 // fold (select C, 0, X) -> (and (not C), X)
2810 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2810 if (VT == VT0 && VT == EVT::i1 && N1C && N1C->isNullValue()) {
28112811 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
28122812 AddToWorkList(NOTNode.getNode());
28132813 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
28142814 }
28152815 // fold (select C, X, 1) -> (or (not C), X)
2816 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2816 if (VT == VT0 && VT == EVT::i1 && N2C && N2C->getAPIntValue() == 1) {
28172817 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
28182818 AddToWorkList(NOTNode.getNode());
28192819 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
28202820 }
28212821 // fold (select C, X, 0) -> (and C, X)
2822 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2822 if (VT == EVT::i1 && N2C && N2C->isNullValue())
28232823 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
28242824 // fold (select X, X, Y) -> (or X, Y)
28252825 // fold (select X, 1, Y) -> (or X, Y)
2826 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2826 if (VT == EVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
28272827 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
28282828 // fold (select X, Y, X) -> (and X, Y)
28292829 // fold (select X, Y, 0) -> (and X, Y)
2830 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2830 if (VT == EVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
28312831 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
28322832
28332833 // If we can fold this based on the true/false value, do so.
28372837 // fold selects based on a setcc into other things, such as min/max/abs
28382838 if (N0.getOpcode() == ISD::SETCC) {
28392839 // FIXME:
2840 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2840 // Check against EVT::Other for SELECT_CC, which is a workaround for targets
28412841 // having to say they don't support SELECT_CC on every type the DAG knows
28422842 // about, since there is no way to mark an opcode illegal at all value types
2843 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
2843 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, EVT::Other) &&
28442844 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
28452845 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
28462846 N0.getOperand(0), N0.getOperand(1),
29612961
29622962 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
29632963 SDValue N0 = N->getOperand(0);
2964 MVT VT = N->getValueType(0);
2964 EVT VT = N->getValueType(0);
29652965
29662966 // fold (sext c1) -> c1
29672967 if (isa(N0))
30703070 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
30713071 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
30723072 LoadSDNode *LN0 = cast(N0);
3073 MVT EVT = LN0->getMemoryVT();
3073 EVT EVT = LN0->getMemoryVT();
30743074 if ((!LegalOperations && !LN0->isVolatile()) ||
30753075 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
30763076 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
31263126
31273127 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
31283128 SDValue N0 = N->getOperand(0);
3129 MVT VT = N->getValueType(0);
3129 EVT VT = N->getValueType(0);
31303130
31313131 // fold (zext c1) -> c1
31323132 if (isa(N0))
32303230 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
32313231 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
32323232 LoadSDNode *LN0 = cast(N0);
3233 MVT EVT = LN0->getMemoryVT();
3233 EVT EVT = LN0->getMemoryVT();
32343234 if ((!LegalOperations && !LN0->isVolatile()) ||
32353235 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
32363236 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
32613261
32623262 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
32633263 SDValue N0 = N->getOperand(0);
3264 MVT VT = N->getValueType(0);
3264 EVT VT = N->getValueType(0);
32653265
32663266 // fold (aext c1) -> c1
32673267 if (isa(N0))
33663366 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
33673367 N0.hasOneUse()) {
33683368 LoadSDNode *LN0 = cast(N0);
3369 MVT EVT = LN0->getMemoryVT();
3369 EVT EVT = LN0->getMemoryVT();
33703370 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
33713371 VT, LN0->getChain(), LN0->getBasePtr(),
33723372 LN0->getSrcValue(),
34363436 unsigned Opc = N->getOpcode();
34373437 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
34383438 SDValue N0 = N->getOperand(0);
3439 MVT VT = N->getValueType(0);
3440 MVT EVT = VT;
3439 EVT VT = N->getValueType(0);
3440 EVT ExtVT = VT;
34413441
34423442 // This transformation isn't valid for vector loads.
34433443 if (VT.isVector())
34473447 // extended to VT.
34483448 if (Opc == ISD::SIGN_EXTEND_INREG) {
34493449 ExtType = ISD::SEXTLOAD;
3450 EVT = cast(N->getOperand(1))->getVT();
3451 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))
3450 ExtVT = cast(N->getOperand(1))->getVT();
3451 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
34523452 return SDValue();
34533453 }
34543454
3455 unsigned EVTBits = EVT.getSizeInBits();
3455 unsigned EVTBits = ExtVT.getSizeInBits();
34563456 unsigned ShAmt = 0;
34573457 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
34583458 if (ConstantSDNode *N01 = dyn_cast(N0.getOperand(1))) {
34683468
34693469 // Do not generate loads of non-round integer types since these can
34703470 // be expensive (and would be wrong if the type is not byte sized).
3471 if (isa(N0) && N0.hasOneUse() && EVT.isRound() &&
3471 if (isa(N0) && N0.hasOneUse() && ExtVT.isRound() &&
34723472 cast(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
34733473 // Do not change the width of a volatile load.
34743474 !cast(N0)->isVolatile()) {
34753475 LoadSDNode *LN0 = cast(N0);
3476 MVT PtrType = N0.getOperand(1).getValueType();
3476 EVT PtrType = N0.getOperand(1).getValueType();
34773477
34783478 // For big endian targets, we need to adjust the offset to the pointer to
34793479 // load the correct bytes.
34803480 if (TLI.isBigEndian()) {
34813481 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3482 unsigned EVTStoreBits = EVT.getStoreSizeInBits();
3482 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
34833483 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
34843484 }
34853485
34963496 LN0->isVolatile(), NewAlign)
34973497 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
34983498 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3499 EVT, LN0->isVolatile(), NewAlign);
3499 ExtVT, LN0->isVolatile(), NewAlign);
35003500