llvm.org GIT mirror llvm / e4f3b1f
[SLP] Fix crash after r358519, by V. Porpodas. Summary: The code did not check if operand was undef before casting it to Instruction. Reviewers: RKSimon, ABataev, dtemirbulatov Reviewed By: ABataev Subscribers: uabelho Tags: #llvm Differential Revision: https://reviews.llvm.org/D61024 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359136 91177308-0d34-0410-b5e6-96231b3b80d8 Alexey Bataev 4 months ago
2 changed file(s) with 49 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
784784 break;
785785 case ReorderingMode::Opcode:
786786 // We accept both Instructions and Undefs, but with different scores.
787 if ((isa(Op) &&
787 if ((isa(Op) && isa(OpLastLane) &&
788788 cast(Op)->getOpcode() ==
789789 cast(OpLastLane)->getOpcode()) ||
790 (isa(OpLastLane) && isa(Op)) ||
790791 isa(Op)) {
791792 // An instruction has a higher score than an undef.
792793 unsigned Score = (isa(Op)) ? GoodScore : BestScore;
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt -slp-vectorizer -S < %s -mtriple=x86_64-unknown-linux -mcpu=corei7-avx | FileCheck %s
2
3 define i32 @crash_reordering_undefs() {
4 ; CHECK-LABEL: @crash_reordering_undefs(
5 ; CHECK-NEXT: entry:
6 ; CHECK-NEXT: [[OR0:%.*]] = or i64 undef, undef
7 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i64 undef, [[OR0]]
8 ; CHECK-NEXT: [[ADD0:%.*]] = select i1 [[CMP0]], i32 65536, i32 65537
9 ; CHECK-NEXT: [[ADD1:%.*]] = add i32 undef, [[ADD0]]
10 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 undef, undef
11 ; CHECK-NEXT: [[ADD2:%.*]] = select i1 [[CMP1]], i32 65536, i32 65537
12 ; CHECK-NEXT: [[ADD3:%.*]] = add i32 [[ADD1]], [[ADD2]]
13 ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i64 undef, undef
14 ; CHECK-NEXT: [[ADD4:%.*]] = select i1 [[CMP2]], i32 65536, i32 65537
15 ; CHECK-NEXT: [[ADD5:%.*]] = add i32 [[ADD3]], [[ADD4]]
16 ; CHECK-NEXT: [[ADD6:%.*]] = add i32 [[ADD5]], undef
17 ; CHECK-NEXT: [[ADD7:%.*]] = add i32 [[ADD6]], undef
18 ; CHECK-NEXT: [[ADD8:%.*]] = add i32 [[ADD7]], undef
19 ; CHECK-NEXT: [[OR1:%.*]] = or i64 undef, undef
20 ; CHECK-NEXT: [[CMP3:%.*]] = icmp eq i64 undef, [[OR1]]
21 ; CHECK-NEXT: [[ADD9:%.*]] = select i1 [[CMP3]], i32 65536, i32 65537
22 ; CHECK-NEXT: [[ADD10:%.*]] = add i32 [[ADD8]], [[ADD9]]
23 ; CHECK-NEXT: [[ADD11:%.*]] = add i32 [[ADD10]], undef
24 ; CHECK-NEXT: ret i32 [[ADD11]]
25 ;
26 entry:
27 %or0 = or i64 undef, undef
28 %cmp0 = icmp eq i64 undef, %or0
29 %add0 = select i1 %cmp0, i32 65536, i32 65537
30 %add1 = add i32 undef, %add0
31 %cmp1 = icmp eq i64 undef, undef
32 %add2 = select i1 %cmp1, i32 65536, i32 65537
33 %add3 = add i32 %add1, %add2
34 %cmp2 = icmp eq i64 undef, undef
35 %add4 = select i1 %cmp2, i32 65536, i32 65537
36 %add5 = add i32 %add3, %add4
37 %add6 = add i32 %add5, undef
38 %add7 = add i32 %add6, undef
39 %add8 = add i32 %add7, undef
40 %or1 = or i64 undef, undef
41 %cmp3 = icmp eq i64 undef, %or1
42 %add9 = select i1 %cmp3, i32 65536, i32 65537
43 %add10 = add i32 %add8, %add9
44 %add11 = add i32 %add10, undef
45 ret i32 %add11
46 }