llvm.org GIT mirror llvm / e4d9699
[MIPS GlobalISel] Select floating point to integer conversions Select G_FPTOSI and G_FPTOUI for MIPS32. Differential Revision: https://reviews.llvm.org/D63541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363911 91177308-0d34-0410-b5e6-96231b3b80d8 Petar Avramovic 29 days ago
8 changed file(s) with 709 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
419419 // FIXME: Support other types
420420 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
421421 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
422 if (ToSize != 32 || (FromSize != 32 && FromSize != 64))
422 if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
423423 return UnableToLegalize;
424424 LegalizeResult Status = conversionLibcall(
425 MI, MIRBuilder, Type::getInt32Ty(Ctx),
425 MI, MIRBuilder,
426 ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
426427 FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
427428 if (Status != Legalized)
428429 return Status;
365365 .add(I.getOperand(0))
366366 .add(I.getOperand(1));
367367 break;
368 }
369 case G_FPTOSI: {
370 unsigned FromSize = MRI.getType(I.getOperand(1).getReg()).getSizeInBits();
371 unsigned ToSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
372 assert((ToSize == 32) && "Unsupported integer size for G_FPTOSI");
373 assert((FromSize == 32 || FromSize == 64) &&
374 "Unsupported floating point size for G_FPTOSI");
375
376 unsigned Opcode;
377 if (FromSize == 32)
378 Opcode = Mips::TRUNC_W_S;
379 else
380 Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32;
381 unsigned ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass);
382 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
383 .addDef(ResultInFPR)
384 .addUse(I.getOperand(1).getReg());
385 if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI))
386 return false;
387
388 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1))
389 .addDef(I.getOperand(0).getReg())
390 .addUse(ResultInFPR);
391 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
392 return false;
393
394 I.eraseFromParent();
395 return true;
368396 }
369397 case G_GLOBAL_VALUE: {
370398 const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
109109 getActionDefinitionsBuilder(G_FPTRUNC)
110110 .legalFor({{s32, s64}});
111111
112 // FP to int conversion instructions
113 getActionDefinitionsBuilder(G_FPTOSI)
114 .legalForCartesianProduct({s32}, {s64, s32})
115 .libcallForCartesianProduct({s64}, {s64, s32})
116 .minScalar(0, s32);
117
118 getActionDefinitionsBuilder(G_FPTOUI)
119 .libcallForCartesianProduct({s64}, {s64, s32})
120 .minScalar(0, s32);
121
112122 computeTables();
113123 verify(*ST.getInstrInfo());
114124 }
169169 OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::SPRIdx],
170170 &Mips::ValueMappings[Mips::DPRIdx]});
171171 break;
172 case G_FPTOSI: {
173 unsigned SizeInt = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
174 unsigned SizeFP = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
175 assert((SizeInt == 32) && "Unsupported integer size");
176 assert((SizeFP == 32 || SizeFP == 64) && "Unsupported floating point size");
177 OperandsMapping = getOperandsMapping({
178 &Mips::ValueMappings[Mips::GPRIdx],
179 SizeFP == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
180 : &Mips::ValueMappings[Mips::DPRIdx],
181 });
182 break;
183 }
172184 case G_CONSTANT:
173185 case G_FRAME_INDEX:
174186 case G_GLOBAL_VALUE:
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
2 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
3 --- |
4
5 define void @f32toi32() {entry: ret void}
6 define void @f64toi32() {entry: ret void}
7
8 ...
9 ---
10 name: f32toi32
11 alignment: 2
12 legalized: true
13 regBankSelected: true
14 tracksRegLiveness: true
15 body: |
16 bb.1.entry:
17 liveins: $f12
18
19 ; FP32-LABEL: name: f32toi32
20 ; FP32: liveins: $f12
21 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
22 ; FP32: [[TRUNC_W_S:%[0-9]+]]:fgr32 = TRUNC_W_S [[COPY]]
23 ; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
24 ; FP32: $v0 = COPY [[MFC1_]]
25 ; FP32: RetRA implicit $v0
26 ; FP64-LABEL: name: f32toi32
27 ; FP64: liveins: $f12
28 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
29 ; FP64: [[TRUNC_W_S:%[0-9]+]]:fgr32 = TRUNC_W_S [[COPY]]
30 ; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
31 ; FP64: $v0 = COPY [[MFC1_]]
32 ; FP64: RetRA implicit $v0
33 %0:fprb(s32) = COPY $f12
34 %1:gprb(s32) = G_FPTOSI %0(s32)
35 $v0 = COPY %1(s32)
36 RetRA implicit $v0
37
38 ...
39 ---
40 name: f64toi32
41 alignment: 2
42 legalized: true
43 regBankSelected: true
44 tracksRegLiveness: true
45 body: |
46 bb.1.entry:
47 liveins: $d6
48
49 ; FP32-LABEL: name: f64toi32
50 ; FP32: liveins: $d6
51 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
52 ; FP32: [[TRUNC_W_D32_:%[0-9]+]]:fgr32 = TRUNC_W_D32 [[COPY]]
53 ; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_D32_]]
54 ; FP32: $v0 = COPY [[MFC1_]]
55 ; FP32: RetRA implicit $v0
56 ; FP64-LABEL: name: f64toi32
57 ; FP64: liveins: $d6
58 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
59 ; FP64: [[TRUNC_W_D64_:%[0-9]+]]:fgr32 = TRUNC_W_D64 [[COPY]]
60 ; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_D64_]]
61 ; FP64: $v0 = COPY [[MFC1_]]
62 ; FP64: RetRA implicit $v0
63 %0:fprb(s64) = COPY $d6
64 %1:gprb(s32) = G_FPTOSI %0(s64)
65 $v0 = COPY %1(s32)
66 RetRA implicit $v0
67
68 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
2 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
3 --- |
4
5 define void @f32toi64() {entry: ret void}
6 define void @f32toi32() {entry: ret void}
7 define void @f32toi16() {entry: ret void}
8 define void @f32toi8() {entry: ret void}
9 define void @f64toi64() {entry: ret void}
10 define void @f64toi32() {entry: ret void}
11 define void @f64toi16() {entry: ret void}
12 define void @f64toi8() {entry: ret void}
13 define void @f32tou64() {entry: ret void}
14 define void @f64tou64() {entry: ret void}
15
16 ...
17 ---
18 name: f32toi64
19 alignment: 2
20 tracksRegLiveness: true
21 body: |
22 bb.1.entry:
23 liveins: $f12
24
25 ; FP32-LABEL: name: f32toi64
26 ; FP32: liveins: $f12
27 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
28 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
29 ; FP32: $f12 = COPY [[COPY]](s32)
30 ; FP32: JAL &__fixsfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
31 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
32 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
33 ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
34 ; FP32: $v0 = COPY [[COPY1]](s32)
35 ; FP32: $v1 = COPY [[COPY2]](s32)
36 ; FP32: RetRA implicit $v0, implicit $v1
37 ; FP64-LABEL: name: f32toi64
38 ; FP64: liveins: $f12
39 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
40 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
41 ; FP64: $f12 = COPY [[COPY]](s32)
42 ; FP64: JAL &__fixsfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
43 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
44 ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
45 ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
46 ; FP64: $v0 = COPY [[COPY1]](s32)
47 ; FP64: $v1 = COPY [[COPY2]](s32)
48 ; FP64: RetRA implicit $v0, implicit $v1
49 %0:_(s32) = COPY $f12
50 %1:_(s64) = G_FPTOSI %0(s32)
51 %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
52 $v0 = COPY %2(s32)
53 $v1 = COPY %3(s32)
54 RetRA implicit $v0, implicit $v1
55
56 ...
57 ---
58 name: f32toi32
59 alignment: 2
60 tracksRegLiveness: true
61 body: |
62 bb.1.entry:
63 liveins: $f12
64
65 ; FP32-LABEL: name: f32toi32
66 ; FP32: liveins: $f12
67 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
68 ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
69 ; FP32: $v0 = COPY [[FPTOSI]](s32)
70 ; FP32: RetRA implicit $v0
71 ; FP64-LABEL: name: f32toi32
72 ; FP64: liveins: $f12
73 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
74 ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
75 ; FP64: $v0 = COPY [[FPTOSI]](s32)
76 ; FP64: RetRA implicit $v0
77 %0:_(s32) = COPY $f12
78 %1:_(s32) = G_FPTOSI %0(s32)
79 $v0 = COPY %1(s32)
80 RetRA implicit $v0
81
82 ...
83 ---
84 name: f32toi16
85 alignment: 2
86 tracksRegLiveness: true
87 body: |
88 bb.1.entry:
89 liveins: $f12
90
91 ; FP32-LABEL: name: f32toi16
92 ; FP32: liveins: $f12
93 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
94 ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
95 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
96 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
97 ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
98 ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
99 ; FP32: $v0 = COPY [[ASHR]](s32)
100 ; FP32: RetRA implicit $v0
101 ; FP64-LABEL: name: f32toi16
102 ; FP64: liveins: $f12
103 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
104 ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
105 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
106 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
107 ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
108 ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
109 ; FP64: $v0 = COPY [[ASHR]](s32)
110 ; FP64: RetRA implicit $v0
111 %0:_(s32) = COPY $f12
112 %1:_(s16) = G_FPTOSI %0(s32)
113 %2:_(s32) = G_SEXT %1(s16)
114 $v0 = COPY %2(s32)
115 RetRA implicit $v0
116
117 ...
118 ---
119 name: f32toi8
120 alignment: 2
121 tracksRegLiveness: true
122 body: |
123 bb.1.entry:
124 liveins: $f12
125
126 ; FP32-LABEL: name: f32toi8
127 ; FP32: liveins: $f12
128 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
129 ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
130 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
131 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
132 ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
133 ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
134 ; FP32: $v0 = COPY [[ASHR]](s32)
135 ; FP32: RetRA implicit $v0
136 ; FP64-LABEL: name: f32toi8
137 ; FP64: liveins: $f12
138 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
139 ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
140 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
141 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
142 ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
143 ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
144 ; FP64: $v0 = COPY [[ASHR]](s32)
145 ; FP64: RetRA implicit $v0
146 %0:_(s32) = COPY $f12
147 %1:_(s8) = G_FPTOSI %0(s32)
148 %2:_(s32) = G_SEXT %1(s8)
149 $v0 = COPY %2(s32)
150 RetRA implicit $v0
151
152 ...
153 ---
154 name: f64toi64
155 alignment: 2
156 tracksRegLiveness: true
157 body: |
158 bb.1.entry:
159 liveins: $d6
160
161 ; FP32-LABEL: name: f64toi64
162 ; FP32: liveins: $d6
163 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
164 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
165 ; FP32: $d6 = COPY [[COPY]](s64)
166 ; FP32: JAL &__fixdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
167 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
168 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
169 ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
170 ; FP32: $v0 = COPY [[COPY1]](s32)
171 ; FP32: $v1 = COPY [[COPY2]](s32)
172 ; FP32: RetRA implicit $v0, implicit $v1
173 ; FP64-LABEL: name: f64toi64
174 ; FP64: liveins: $d6
175 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
176 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
177 ; FP64: $d12_64 = COPY [[COPY]](s64)
178 ; FP64: JAL &__fixdfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
179 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
180 ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
181 ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
182 ; FP64: $v0 = COPY [[COPY1]](s32)
183 ; FP64: $v1 = COPY [[COPY2]](s32)
184 ; FP64: RetRA implicit $v0, implicit $v1
185 %0:_(s64) = COPY $d6
186 %1:_(s64) = G_FPTOSI %0(s64)
187 %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
188 $v0 = COPY %2(s32)
189 $v1 = COPY %3(s32)
190 RetRA implicit $v0, implicit $v1
191
192 ...
193 ---
194 name: f64toi32
195 alignment: 2
196 tracksRegLiveness: true
197 body: |
198 bb.1.entry:
199 liveins: $d6
200
201 ; FP32-LABEL: name: f64toi32
202 ; FP32: liveins: $d6
203 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
204 ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
205 ; FP32: $v0 = COPY [[FPTOSI]](s32)
206 ; FP32: RetRA implicit $v0
207 ; FP64-LABEL: name: f64toi32
208 ; FP64: liveins: $d6
209 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
210 ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
211 ; FP64: $v0 = COPY [[FPTOSI]](s32)
212 ; FP64: RetRA implicit $v0
213 %0:_(s64) = COPY $d6
214 %1:_(s32) = G_FPTOSI %0(s64)
215 $v0 = COPY %1(s32)
216 RetRA implicit $v0
217
218 ...
219 ---
220 name: f64toi16
221 alignment: 2
222 tracksRegLiveness: true
223 body: |
224 bb.1.entry:
225 liveins: $d6
226
227 ; FP32-LABEL: name: f64toi16
228 ; FP32: liveins: $d6
229 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
230 ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
231 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
232 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
233 ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
234 ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
235 ; FP32: $v0 = COPY [[ASHR]](s32)
236 ; FP32: RetRA implicit $v0
237 ; FP64-LABEL: name: f64toi16
238 ; FP64: liveins: $d6
239 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
240 ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
241 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
242 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
243 ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
244 ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
245 ; FP64: $v0 = COPY [[ASHR]](s32)
246 ; FP64: RetRA implicit $v0
247 %0:_(s64) = COPY $d6
248 %1:_(s16) = G_FPTOSI %0(s64)
249 %2:_(s32) = G_SEXT %1(s16)
250 $v0 = COPY %2(s32)
251 RetRA implicit $v0
252
253 ...
254 ---
255 name: f64toi8
256 alignment: 2
257 tracksRegLiveness: true
258 body: |
259 bb.1.entry:
260 liveins: $d6
261
262 ; FP32-LABEL: name: f64toi8
263 ; FP32: liveins: $d6
264 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
265 ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
266 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
267 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
268 ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
269 ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
270 ; FP32: $v0 = COPY [[ASHR]](s32)
271 ; FP32: RetRA implicit $v0
272 ; FP64-LABEL: name: f64toi8
273 ; FP64: liveins: $d6
274 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
275 ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
276 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
277 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
278 ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
279 ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
280 ; FP64: $v0 = COPY [[ASHR]](s32)
281 ; FP64: RetRA implicit $v0
282 %0:_(s64) = COPY $d6
283 %1:_(s8) = G_FPTOSI %0(s64)
284 %2:_(s32) = G_SEXT %1(s8)
285 $v0 = COPY %2(s32)
286 RetRA implicit $v0
287
288 ...
289 ---
290 name: f32tou64
291 alignment: 2
292 tracksRegLiveness: true
293 body: |
294 bb.1.entry:
295 liveins: $f12
296
297 ; FP32-LABEL: name: f32tou64
298 ; FP32: liveins: $f12
299 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
300 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
301 ; FP32: $f12 = COPY [[COPY]](s32)
302 ; FP32: JAL &__fixunssfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
303 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
304 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
305 ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
306 ; FP32: $v0 = COPY [[COPY1]](s32)
307 ; FP32: $v1 = COPY [[COPY2]](s32)
308 ; FP32: RetRA implicit $v0, implicit $v1
309 ; FP64-LABEL: name: f32tou64
310 ; FP64: liveins: $f12
311 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
312 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
313 ; FP64: $f12 = COPY [[COPY]](s32)
314 ; FP64: JAL &__fixunssfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
315 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
316 ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
317 ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
318 ; FP64: $v0 = COPY [[COPY1]](s32)
319 ; FP64: $v1 = COPY [[COPY2]](s32)
320 ; FP64: RetRA implicit $v0, implicit $v1
321 %0:_(s32) = COPY $f12
322 %1:_(s64) = G_FPTOUI %0(s32)
323 %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
324 $v0 = COPY %2(s32)
325 $v1 = COPY %3(s32)
326 RetRA implicit $v0, implicit $v1
327
328 ...
329 ---
330 name: f64tou64
331 alignment: 2
332 tracksRegLiveness: true
333 body: |
334 bb.1.entry:
335 liveins: $d6
336
337 ; FP32-LABEL: name: f64tou64
338 ; FP32: liveins: $d6
339 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
340 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
341 ; FP32: $d6 = COPY [[COPY]](s64)
342 ; FP32: JAL &__fixunsdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
343 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
344 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
345 ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
346 ; FP32: $v0 = COPY [[COPY1]](s32)
347 ; FP32: $v1 = COPY [[COPY2]](s32)
348 ; FP32: RetRA implicit $v0, implicit $v1
349 ; FP64-LABEL: name: f64tou64
350 ; FP64: liveins: $d6
351 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
352 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
353 ; FP64: $d12_64 = COPY [[COPY]](s64)
354 ; FP64: JAL &__fixunsdfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
355 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
356 ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
357 ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
358 ; FP64: $v0 = COPY [[COPY1]](s32)
359 ; FP64: $v1 = COPY [[COPY2]](s32)
360 ; FP64: RetRA implicit $v0, implicit $v1
361 %0:_(s64) = COPY $d6
362 %1:_(s64) = G_FPTOUI %0(s64)
363 %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
364 $v0 = COPY %2(s32)
365 $v1 = COPY %3(s32)
366 RetRA implicit $v0, implicit $v1
367
368 ...
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
2 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
3
4 define i64 @f32toi64(float %a) {
5 ; MIPS32-LABEL: f32toi64:
6 ; MIPS32: # %bb.0: # %entry
7 ; MIPS32-NEXT: addiu $sp, $sp, -24
8 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
9 ; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
10 ; MIPS32-NEXT: .cfi_offset 31, -4
11 ; MIPS32-NEXT: jal __fixsfdi
12 ; MIPS32-NEXT: nop
13 ; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
14 ; MIPS32-NEXT: addiu $sp, $sp, 24
15 ; MIPS32-NEXT: jr $ra
16 ; MIPS32-NEXT: nop
17 entry:
18 %conv = fptosi float %a to i64
19 ret i64 %conv
20 }
21
22 define i32 @f32toi32(float %a) {
23 ; MIPS32-LABEL: f32toi32:
24 ; MIPS32: # %bb.0: # %entry
25 ; MIPS32-NEXT: trunc.w.s $f0, $f12
26 ; MIPS32-NEXT: mfc1 $2, $f0
27 ; MIPS32-NEXT: jr $ra
28 ; MIPS32-NEXT: nop
29 entry:
30 %conv = fptosi float %a to i32
31 ret i32 %conv
32 }
33
34 define signext i16 @f32toi16(float %a) {
35 ; MIPS32-LABEL: f32toi16:
36 ; MIPS32: # %bb.0: # %entry
37 ; MIPS32-NEXT: trunc.w.s $f0, $f12
38 ; MIPS32-NEXT: mfc1 $1, $f0
39 ; MIPS32-NEXT: sll $1, $1, 16
40 ; MIPS32-NEXT: sra $2, $1, 16
41 ; MIPS32-NEXT: jr $ra
42 ; MIPS32-NEXT: nop
43 entry:
44 %conv = fptosi float %a to i16
45 ret i16 %conv
46 }
47
48 define signext i8 @f32toi8(float %a) {
49 ; MIPS32-LABEL: f32toi8:
50 ; MIPS32: # %bb.0: # %entry
51 ; MIPS32-NEXT: trunc.w.s $f0, $f12
52 ; MIPS32-NEXT: mfc1 $1, $f0
53 ; MIPS32-NEXT: sll $1, $1, 24
54 ; MIPS32-NEXT: sra $2, $1, 24
55 ; MIPS32-NEXT: jr $ra
56 ; MIPS32-NEXT: nop
57 entry:
58 %conv = fptosi float %a to i8
59 ret i8 %conv
60 }
61
62 define i64 @f64toi64(double %a) {
63 ; MIPS32-LABEL: f64toi64:
64 ; MIPS32: # %bb.0: # %entry
65 ; MIPS32-NEXT: addiu $sp, $sp, -24
66 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
67 ; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
68 ; MIPS32-NEXT: .cfi_offset 31, -4
69 ; MIPS32-NEXT: jal __fixdfdi
70 ; MIPS32-NEXT: nop
71 ; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
72 ; MIPS32-NEXT: addiu $sp, $sp, 24
73 ; MIPS32-NEXT: jr $ra
74 ; MIPS32-NEXT: nop
75 entry:
76 %conv = fptosi double %a to i64
77 ret i64 %conv
78 }
79
80 define i32 @f64toi32(double %a) {
81 ; MIPS32-LABEL: f64toi32:
82 ; MIPS32: # %bb.0: # %entry
83 ; MIPS32-NEXT: trunc.w.d $f0, $f12
84 ; MIPS32-NEXT: mfc1 $2, $f0
85 ; MIPS32-NEXT: jr $ra
86 ; MIPS32-NEXT: nop
87 entry:
88 %conv = fptosi double %a to i32
89 ret i32 %conv
90 }
91
92 define signext i16 @f64toi16(double %a) {
93 ; MIPS32-LABEL: f64toi16:
94 ; MIPS32: # %bb.0: # %entry
95 ; MIPS32-NEXT: trunc.w.d $f0, $f12
96 ; MIPS32-NEXT: mfc1 $1, $f0
97 ; MIPS32-NEXT: sll $1, $1, 16
98 ; MIPS32-NEXT: sra $2, $1, 16
99 ; MIPS32-NEXT: jr $ra
100 ; MIPS32-NEXT: nop
101 entry:
102 %conv = fptosi double %a to i16
103 ret i16 %conv
104 }
105
106 define signext i8 @f64toi8(double %a) {
107 ; MIPS32-LABEL: f64toi8:
108 ; MIPS32: # %bb.0: # %entry
109 ; MIPS32-NEXT: trunc.w.d $f0, $f12
110 ; MIPS32-NEXT: mfc1 $1, $f0
111 ; MIPS32-NEXT: sll $1, $1, 24
112 ; MIPS32-NEXT: sra $2, $1, 24
113 ; MIPS32-NEXT: jr $ra
114 ; MIPS32-NEXT: nop
115 entry:
116 %conv = fptosi double %a to i8
117 ret i8 %conv
118 }
119
120 define i64 @f32tou64(float %a) {
121 ; MIPS32-LABEL: f32tou64:
122 ; MIPS32: # %bb.0: # %entry
123 ; MIPS32-NEXT: addiu $sp, $sp, -24
124 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
125 ; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
126 ; MIPS32-NEXT: .cfi_offset 31, -4
127 ; MIPS32-NEXT: jal __fixunssfdi
128 ; MIPS32-NEXT: nop
129 ; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
130 ; MIPS32-NEXT: addiu $sp, $sp, 24
131 ; MIPS32-NEXT: jr $ra
132 ; MIPS32-NEXT: nop
133 entry:
134 %conv = fptoui float %a to i64
135 ret i64 %conv
136 }
137
138 define i64 @f64tou64(double %a) {
139 ; MIPS32-LABEL: f64tou64:
140 ; MIPS32: # %bb.0: # %entry
141 ; MIPS32-NEXT: addiu $sp, $sp, -24
142 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
143 ; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
144 ; MIPS32-NEXT: .cfi_offset 31, -4
145 ; MIPS32-NEXT: jal __fixunsdfdi
146 ; MIPS32-NEXT: nop
147 ; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
148 ; MIPS32-NEXT: addiu $sp, $sp, 24
149 ; MIPS32-NEXT: jr $ra
150 ; MIPS32-NEXT: nop
151 entry:
152 %conv = fptoui double %a to i64
153 ret i64 %conv
154 }
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
2 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
3 --- |
4
5 define void @f32toi32() {entry: ret void}
6 define void @f64toi32() {entry: ret void}
7
8 ...
9 ---
10 name: f32toi32
11 alignment: 2
12 legalized: true
13 tracksRegLiveness: true
14 body: |
15 bb.1.entry:
16 liveins: $f12
17
18 ; FP32-LABEL: name: f32toi32
19 ; FP32: liveins: $f12
20 ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
21 ; FP32: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
22 ; FP32: $v0 = COPY [[FPTOSI]](s32)
23 ; FP32: RetRA implicit $v0
24 ; FP64-LABEL: name: f32toi32
25 ; FP64: liveins: $f12
26 ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
27 ; FP64: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
28 ; FP64: $v0 = COPY [[FPTOSI]](s32)
29 ; FP64: RetRA implicit $v0
30 %0:_(s32) = COPY $f12
31 %1:_(s32) = G_FPTOSI %0(s32)
32 $v0 = COPY %1(s32)
33 RetRA implicit $v0
34
35 ...
36 ---
37 name: f64toi32
38 alignment: 2
39 legalized: true
40 tracksRegLiveness: true
41 body: |
42 bb.1.entry:
43 liveins: $d6
44
45 ; FP32-LABEL: name: f64toi32
46 ; FP32: liveins: $d6
47 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
48 ; FP32: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
49 ; FP32: $v0 = COPY [[FPTOSI]](s32)
50 ; FP32: RetRA implicit $v0
51 ; FP64-LABEL: name: f64toi32
52 ; FP64: liveins: $d6
53 ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
54 ; FP64: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
55 ; FP64: $v0 = COPY [[FPTOSI]](s32)
56 ; FP64: RetRA implicit $v0
57 %0:_(s64) = COPY $d6
58 %1:_(s32) = G_FPTOSI %0(s64)
59 $v0 = COPY %1(s32)
60 RetRA implicit $v0
61
62 ...